MAX6301ESA+T - Maxim Integrated

_______________General Description

The MAX6301–MAX6304* low-power microprocessor

(µP) supervisory circuits provide maximum adjustability

for reset and watchdog functions. The reset threshold

can be adjusted to any voltage above 1.22V, using

external resistors. In addition, the reset and watchdog

timeout periods are adjustable using external capaci-

tors. A watchdog select pin extends the watchdog time-

out period to 500x. The reset function features immunity

to power-supply transients.

These four devices differ only in the structure of their reset

outputs (see the

Selector Guide

). The MAX6301–MAX6304

are available in the space-saving 8-pin µMAX®package,

as well as 8-pin PDIP and SO packages.

Applications

Medical Equipment Embedded Controllers

Intelligent Instruments Critical µP Monitoring

Portable Equipment Set-Top Boxes

Battery-Powered Computers

Computers/Controllers

____________________________Features

oAdjustable Reset Threshold

oAdjustable Reset Timeout

oAdjustable Watchdog Timeout

o500x Watchdog Timeout Multiplier

o4µA Supply Current

oRESET or RESET Output Options

oPush-Pull or Open-Drain Output Options

oGuaranteed RESET Asserted At or Above

VCC = 1V (MAX6301/MAX6303)

oPower-Supply Transient Immunity

oWatchdog Function can be Disabled

oPDIP/SO/µMAX Packages Available

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

________________________________________________________________

Maxim Integrated Products

0.1µF

MAX6301

MAX6302

MAX6303

MAX6304

VCC

RESET IN

VIN

CSWT

CSRT

SRT

GND

SWT

WDI

WDS

RESET

µP

I/O

RESET

(RESET)

MAX6301

ONLY

MAX6302

ONLY

WDS = 0 FOR NORMAL MODE

WDS = 1 FOR EXTENDED MODE

( ) ARE FOR MAX6302/MAX6304.

Pin Configuration

VCC

RESET (RESET)

WDI

WDS

RESET IN

GND

SRT

SWT

MAX6301

MAX6302

MAX6303

MAX6304

DIP/SO/µMAX

TOP VIEW

( ) ARE FOR MAX6302/MAX6304.

Typical Operating Circuit

19-1078; Rev 4; 9/10

Ordering Information

Ordering Information continued at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Selector Guide

FEATURE MAX6301 MAX6302 MAX6303 MAX6304

Acti ve-Low

Reset √—√—

Acti ve-H i g h

Reset —√—√

Op en- D rai n

Reset Outp ut √√——

P ush- P ul l

Reset Outp ut —— √√

P i n- P ackag e8- PD IP /S O/

µM AX

8- PD IP /S O/

µM AX

8- PD IP /S O/

µM AX

8- PD IP /S O/

µM AX

µMAX is a registered trademark of Maxim Integrated Products, Inc.

PART TEMP RANGE PIN-PACKAGE

MAX6301CPA 0°C to +70°C 8 PDIP

MAX6301CSA 0°C to +70°C 8 SO

MAX6301CUA 0°C to +70°C 8 µMAX

MAX6301EPA -40°C to +85°C 8 PDIP

MAX6301ESA -40°C to +85°C 8 SO

Devices are available in both leaded and lead(Pb)-free/RoHS-

compliant packaging. Specify lead-free by adding the “+

”

symbol at the end of the part number when ordering.

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC = +2V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VCC ....................................................................................-0.3V to +7.0V

RESET IN, SWT, SRT..................................-0.3V to (VCC + 0.3V)

WDI, WDS..............................................................-0.3V to +7.0V

RESET, RESET

MAX6301… .......................................................-0.3V to +7.0V

MAX6302/MAX6303/MAX6304...............-0.3V to (VCC + 0.3V)

Input Current

VCC ...............................................................................±20mA

GND..............................................................................±20mA

Output Current

RESET, RESET..............................................................±20mA

Continuous Power Dissipation (TA= +70°C)

PDIP (derate 9.09mW/°C above +70°C)......................727mW

SO (derate 5.88mW/°C above +70°C).........................471mW

µMAX (derate 4.10mW/°C above +70°C) ....................330mW

Operating Temperature Range

MAX630_C_A......................................................0°C to +70°C

MAX630_E_A ...................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +160°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow)

Lead(Pb)-free...............................................................+260°C

Containing Lead (Pb)...................................................+240°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MAX6301C/MAX6303C 1.00 5.50

MAX6301E/MAX6303E 1.20 5.50

Operating Voltage Range

(Note 1) VCC

MAX6302/MAX6304 1.31 5.50

Supply Current (Note 2) ICC No load 4.0 7.0 µA

RESET TIMER

VRESET IN falling, VCC = 5.0V 1.195 1.220 1.245

Reset Input Threshold Voltage VTH VRESET IN rising, VCC = 5.0V 1.240 1.265 V

Reset Input Hysteresis VHYST 20 mV

Reset Input Leakage Current IRESET IN ±0.01 ±1 nA

VCC ≥ 4.5V, ISOURCE = 0.8mA VCC - 0.4

VCC = 2V, ISOURCE = 0.4mA VCC - 0.4

Reset Output-Voltage High

(MAX6302/MAX6303/MAX6304) VOH MAX6302/MAX6304, VCC = 1.31V,

RL = 10kΩ

VCC -

0.3

VCC ≥ 4.5V, ISINK = 3.2mA 0.4

VCC = 2V, ISINK = 1.6mA 0.4

VCC = 1V, ISINK = 50µA,

TA = 0°C to +70°C 0.3

Reset Output-Voltage Low

(MAX6301/MAX6303/MAX6304 VOL

MAX6301/

MAX6303 VCC = 1.2V, ISINK = 100µA,

TA = -40°C to +85°C 0.3

VCC to Reset Delay tRD VCC = falling at 1mV/µs 63 µs

Reset Input Pulse Width tRI Comparator overdrive = 50mV 26 µs

Reset Timeout Period (Note 3) tRP CSRT = 1500pF 2.8 4.0 5.2 ms

MAX6301, VRESET = VCC ±1

Reset Output Leakage Current MAX6302, VRESET = VGND ±1 µA

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

_______________________________________________________________________________________

10,000

0.001 0.01 0.1 1 10 100 1000

RESET TIMEOUT PERIOD

vs. CSRT

MAX6301-4 toc01

CSRT (nF)

RESET TIMEOUT PERIOD (ms)

100

1000

VCC = 5V 10,000

0.001 0.01 0.1 1 10 100 1000

EXTENDED-MODE

WATCHDOG TIMEOUT PERIOD vs. CSWT

(WDS = VCC)

MAX6301-4 toc02

CSWT (nF)

WATCHDOG TIMEOUT PERIOD (s)

100

1000

VCC = 5V 10,000

0.1

0.001 0.01 0.1 1 10 100 1000

NORMAL-MODE

WATCHDOG TIMEOUT PERIOD vs. CSWT

(WDS = GND)

MAX6301-4 toc03

CSWT (nF)

WATCHDOG TIMEOUT PERIOD (ms)

100

1000

VCC = 5V

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +2V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA= +25°C.)

Note 1: Reset is guaranteed valid from the selected reset threshold voltage down to the minimum VCC.

Note 2: WDS = VCC, WDI unconnected.

Note 3: Precision timing currents of 500nA are present at both the SRT and SWT pins. Timing capacitors connected to these nodes

must have low leakage consistent with these currents to prevent timing errors.

Note 4: The sink/source is supplied through a resistor, and is proportional to VCC (Figure 8). At VCC = 2V, it is typically ±24µA.

__________________________________________Typical Operating Characteristics

(CSWT = CSRT = 1500pF, TA= +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

WATCHDOG TIMER

VIH 0.7 x VCC

WDI, WDS Input Threshold VIL 0.3 x VCC

VCC = 4.5V to 5.5V 30

WDI Pulse Width tWP VCC = 2V to 4.5V 60 ns

WDI, WDS Leakage Current Extended mode disabled ±1 µA

WDI Sink/Source Current (Note 4) Extended mode enabled ±70 µA

WDS = GND, CSWT = 1500pF 2.8 4.0 5.2 ms

Watchdog Timeout Period

(Note 3) tWD WDS = VCC, CSWT = 1500pF 1.4 2.0 2.6 s

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

4 _______________________________________________________________________________________

____________________________Typical Operating Characteristics (continued)

(CSWT = CSRT = 1500pF, TA= +25°C, unless otherwise noted.)

4.25

2.50

-40 40

SUPPLY CURRENT

vs. TEMPERATURE

3.25

3.00

2.75

4.00

MAX6301-4 toc07

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

080-60 -20 6020 100

3.75

3.50

4.50

5.00

4.75

VCC = 5.0V

VCC = 2.0V

RESET DEASSERTED

NO LOAD

1.220

-40 40

RESET IN THRESHOLD VOLTAGE

vs. TEMPERATURE

1.218

MAX6301-4 toc08

TEMPERATURE (°C)

RESET REFERENCE VOLTAGE (V)

080-60 -20 6020 100

1.216

1.214

1.222

1.226

1.224

-40 40

VCC TO RESET DELAY

vs. TEMPERATURE (VCC FALLING)

MAX6301-4 toc09

TEMPERATURE (°C)

PROPAGATION DELAY (µs)

080-60 -20 6020 100

VCC FALLING AT 1mV/µs

RESET AND WATCHDOG

TIMEOUT vs. SUPPLY VOLTAGE

4.12

MAX6301-4 toc10

VCC (V)

tRP/tWP (ms)

23 546

4.08

4.04

4.00

3.96

4.16

3.6

2.6

6.02.0 4.0

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

2.8

3.4

MAX6301-4 toc04

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

3.0 5.01.5 2.5 4.53.5 5.5

3.2

3.0

3.8

4.2

4.0

RESET DEASSERTED

NO LOAD

4.05

3.80

-40 40

RESET AND NORMAL-MODE

WATCHDOG TIMEOUT PERIOD

vs. TEMPERATURE

3.85

4.00

MAX6301-4 toc05

TEMPERATURE (°C)

tRP/tWD (ms)

080-60 -20 6020 100

3.95

3.90

4.10

4.20

4.15 VCC = 5.0V

0 200 400 600 1000800

MAX6301-4 toc06

RESET THRESHOLD OVERDRIVE (mV)

TRANSIENT DURATION (µs)

120

110

100

RESET OCCURS

ABOVE THE CURVE

SEE THE NEGATIVE-GOING

VCC TRANSIENTS SECTION

VRST = 4.60V

MAXIMUM TRANSIENT DURATION

vs. RESET THRESHOLD OVERDRIVE (VRST)

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

_______________________________________________________________________________________ 5

Pin Description

PIN NAME FUNCTION

1 RESET IN

Reset Input. High-impedance input to the reset comparator. Connect this pin to the center point of an

external resistor voltage-divider network to set the reset threshold voltage. The reset threshold voltage is

calculated as follows: VRST = 1.22 x (R1 + R2)/R2 (see the Typical Operating Circuit).

2 GND Ground

3 SRT

Set Reset-Timeout Input. Connect a capacitor between this input and ground to select the reset timeout

period (tRP). Determine the period as follows: tRP = 2.67 x CSRT, with CSRT in pF and tRP in µs (see the

Typical Operating Circuit).

4SWT

Set Watchdog-Timeout Input. Connect a capacitor between this input and ground to select the basic

watchdog timeout period (tWD). Determine the period as follows: tWD = 2.67 x CSWT, with CSWT in pF and

tWD in µs. The watchdog function can be disabled by connecting this pin to ground.

5 WDS

Watchdog-Select Input. This input selects the watchdog mode. Connect to ground to select normal mode

and the basic watchdog timeout period. Connect to VCC to select extended mode, multiplying the basic

timeout period by a factor of 500. A change in the state of this pin resets the watchdog timer to zero.

6 WDI

Watchdog Input. A rising or falling transition must occur on this input within the selected watchdog timeout

period, or a reset pulse will occur. The capacitor value selected for SWT and the state of WDS determine

the watchdog timeout period. The watchdog timer clears and restarts when a transition occurs on WDI or

WDS. The watchdog timer is cleared when reset is asserted and restarted after reset deasserts. In the

extended watchdog mode (WDS = VCC), the watchdog function can be disabled by driving WDI with a

three-stated driver or by leaving WDI unconnected.

Open-Drain, Active-Low Reset

Output (MAX6301)

RESET

(MAX6301/

MAX6303) Push-Pull, Active-Low Reset

Output (MAX6303)

RESET changes from high to low whenever the monitored voltage (VIN)

drops below the selected reset threshold (VRST). RESET remains low as

long as VIN is below VRST. Once VIN exceeds VRST, RESET remains low

for the reset timeout period and then goes high. The watchdog timer

triggers a reset pulse (tRP) whenever the watchdog timeout period (tWD)

is exceeded.

Open-Drain, Active-High Reset

Output (MAX6302)

RESET

(MAX6302/

MAX6304 Push-Pull, Active-High Reset

Output (MAX6304)

RESET changes from low to high whenever the monitored voltage (VIN)

drops below the selected reset threshold (VRST). RESET remains high as

long as VIN is below VRST. Once VIN exceeds VRST, RESET remains high

for the reset timeout period and then goes low. The watchdog timer

triggers a reset pulse (tRP) whenever the watchdog timeout period (tWD)

is exceeded.

CC Supply Voltage. Bypass to ground with a 0.1µF capacitor placed as close as possible to the pin.

Detailed Description

Reset Function/Output

The reset output is typically connected to the reset input

of a µP. A µP’s reset input starts or restarts the µP in a

known state. The MAX6301–MAX6304 µP supervisory

circuits provide the reset logic to prevent code-execution

errors during power-up, power-down, and brownout

conditions (see the

Typical Operating Circuit

For the MAX6301/MAX6303, RESET changes from high

to low whenever the monitored voltage (VIN) drops

below the reset threshold voltage (VRST). RESET

remains low as long as VIN is below VRST. Once VIN

exceeds VRST, RESET remains low for the reset timeout

period, then goes high. When a reset is asserted due to

a watchdog timeout condition, RESET stays low for the

reset timeout period. Any time reset asserts, the watch-

dog timer clears. At the end of the reset timeout period,

RESET goes high and the watchdog timer is restarted

from zero. If the watchdog timeout period is exceeded

again, then RESET goes low again. This cycle contin-

ues unless WDI receives a transition.

On power-up, once VCC reaches 1V, RESET is guaran-

teed to be a logic-low. For information about applica-

tions where VCC is less than 1V, see the

Ensuring a

Valid RESET/RESET Output Down to V

= 0V (MAX6303/

MAX6304)

section. As VCC rises, RESET remains low.

When VIN rises above VRST, the reset timer starts and

RESET remains low. When the reset timeout period

ends, RESET goes high.

On power-down, once VIN goes below VRST, RESET

goes low and is guaranteed to be low until VCC drops

below 1V. For information about applications where

VCC is less than 1V, see the

Ensuring a Valid

RESET/RESET Output Down to V

= 0V (MAX6303/

MAX6304)

section.

The MAX6302/MAX6304 active-high RESET output is

the inverse of the MAX6301/MAX6303 active-low

RESET output, and is guaranteed valid for VCC > 1.31V.

Reset Threshold

These supervisors monitor the voltage on RESET IN.

The MAX6301–MAX6304 have an adjustable reset

threshold voltage (VRST) set with an external resistor

voltage-divider (Figure 1). Use the following formula to

calculate VRST (the point at which the monitored voltage

triggers a reset):

where VRST is the desired reset threshold voltage and

VTH is the reset input threshold (1.22V). Resistors R1

and R2 can have very high values to minimize current

consumption. Set R2 to some conveniently high value

(1MΩ, for example) and calculate R1 based on the desired

reset threshold voltage, using the following formula:

Watchdog Timer

The watchdog circuit monitors the µP’s activity. If the µP

does not toggle the watchdog input (WDI) within tWD

(user selected), reset asserts. The internal watchdog

timer is cleared by reset, by a transition at WDI (which

can detect pulses as short as 30ns), or by a transition

at WDS. The watchdog timer remains cleared while

reset is asserted; as soon as reset is released, the timer

starts counting (Figure 2).

The MAX6301–MAX6304 feature two modes of watchdog

timer operation: normal mode and extended mode. In

normal mode (WDS = GND), the watchdog timeout

period is determined by the value of the capacitor con-

nected between SWT and ground (see the

Selecting

the Reset and Watchdog Timeout Capacitor

section). In

extended mode (WDS = VCC), the watchdog timeout

period is multiplied by 500. For example, in the extended

mode, a 1µF capacitor gives a watchdog timeout period

of 22 minutes (see the Extended-Mode Watchdog

Timeout Period vs. CSWT graph in the

Typical

Operating Characteristics

In extended mode, the watchdog function can be

disabled by leaving WDI unconnected or by three-stating

the driver connected to WDI. In this mode, the watchdog

input is internally driven low during the watchdog timeout

period, then momentarily pulses high, resetting the

R1 R2 V

RST

=× −

⎛

⎝

⎜⎞

⎠

⎟

()

Ω

VVR1R2

R2 V

RST

=×+

()

0.1µF

MAX6301

MAX6302

MAX6303

MAX6304

VCC

RESET IN

VIN

VRST = 1.22

(

R1 + R2

)

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

6 _______________________________________________________________________________________

Figure 1. Calculating the Reset Threshold Voltage (VRST)

watchdog counter. When WDI is left unconnected, the

watchdog timer is cleared by this internal driver just

before the timeout period is reached (the internal driver

pulls WDI high at about 94% of tWD). When WDI is

three-stated, the maximum allowable leakage current of

the device driving WDI is 10µA.

In normal mode (WDS = GND), the watchdog timer

cannot be disabled by three-stating WDI. WDI is a

high-impedance input in this mode. Do not leave WDI

unconnected in normal mode.

Applications Information

Selecting the Reset and Watchdog

Timeout Capacitor

The reset timeout period is adjustable to accommodate

a variety of µP applications. Adjust the reset timeout

period (tRP) by connecting a specific value capacitor

(CSRT) between SRT and ground (Figure 3). Calculate

the reset timeout capacitor as follows:

CSRT = tRP/2.67

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

_______________________________________________________________________________________ 7

VCC

WDI

RESET

NORMAL MODE (WDS = GND)

tWD tRP

VCC

WDI

RESET

EXTENDED MODE (WDS = VCC)

tWD x 500 tRP

Figure 2a. Watchdog Timing Diagram, WDS = GND

Figure 2b. Watchdog Timing Diagram, WDS = VCC

0.1µF

MAX6301

MAX6302

MAX6303

MAX6304

VCC

GND

CSRT = tRP

2.67

VCC

CSWT

CSRT

CSRT in pF

tRP in µs

CSWT = tWD

2.67

CSWT in pF

tWD in µs

SRT

SWT

Figure 3. Calculating the Reset (CSRT) and Watchdog (CSWT)

Timeout Capacitor Values

MAX6301–MAX6304

with CSRT in pF and tRP in µs. CSRT must be a low-leak-

age (< 10nA) type capacitor. Ceramic is recommended.

The watchdog timeout period is adjustable to accom-

modate a variety of µP applications. With this feature,

the watchdog timeout can be optimized for software

execution. The programmer can determine how often

the watchdog timer should be serviced. Adjust the

watchdog timeout period (tWD) by connecting a specif-

ic value capacitor (CSWT) between SWT and ground

(Figure 3). For normal-mode operation, calculate the

watchdog timeout capacitor as follows:

CSWT = tWD/2.67

where CSWT is in pF and tWD is in µs. CSWT must be a

low-leakage (< 10nA) type capacitor. Ceramic is

recommended.

Monitoring Voltages Other than VCC

The

Typical Operating Circuit

monitors VCC. Voltages

other than VCC can easily be monitored, as shown in

Figure 4. Calculate VRST as shown in the

Reset

Threshold

section.

Wake-Up Timer

In some applications, it is advantageous to put a µP

into sleep mode, periodically wake it up to perform

checks and/or tasks, then put it back into sleep mode.

The MAX6301 family of supervisors can easily accom-

modate this technique. Figure 5 illustrates an example

using the MAX6302 and an 80C51.

In Figure 5, just before the µC puts itself into sleep

mode, it pulls WDS high. The µC’s I/O pins maintain

their logic levels while in sleep mode and WDS remains

high. This places the MAX6302 in extended mode,

increasing the watchdog timeout 500 times. When the

watchdog timeout period ends, a reset is applied on

the 80C51, waking it up to perform tasks. While the µP

is performing tasks, the 80C51 pulls WDS low (select-

ing normal mode), and the MAX6302 monitors the µP

for hang-ups. When the µP finishes its tasks, it puts

itself back into sleep mode, drives WDS high, and

starts the cycle over again. This is a power-saving tech-

nique, since the µP is operating only part of the time

and the MAX6302 has very low quiescent current.

Adding a Manual Reset Function

A manual reset option can easily be implemented by con-

necting a normally open momentary switch in parallel with

R2 (Figure 6). When the switch is closed, the voltage on

RESET IN goes to zero, initiating a reset. When the

switch is released, the reset remains asserted for the

reset timeout period and then is cleared. The pushbut-

ton switch is effectively debounced by the reset timer.

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

8 _______________________________________________________________________________________

0.1µF

MAX6301

MAX6302

MAX6303

MAX6304

VCC

RESET IN

VIN

VRST = 1.22

(

R1 + R2

)

VCC

Figure 4. Monitoring Votlages Other than V

MAX6302

VCC

RESET

WDI

WDS

VCC

I/O

GND

80C51

VCC

GND

RST

*THREE-STATE LEAKAGE MUST BE < 10µA.

Figure 5. Wake-Up Timer

0.1µF

MAX6301

MAX6302

MAX6303

MAX6304

VCC

RESET IN

VCC

Figure 6. Adding a Manual Reset Function

Interfacing to µPs with

Bidirectional Reset Pins

Since RESET is open-drain, the MAX6301 interfaces

easily with µPs that have bidirectional reset pins, such

as the Motorola 68HC11 (Figure 7). Connecting RESET

directly to the µP’s reset pin with a single pullup allows

either device to assert reset.

Negative-Going VCC Transients

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, these supervisors

are relatively immune to short-duration negative-going

transients (glitches). The Maximum Transient Duration vs.

Reset Threshold Overdrive graph in the

Typical

Operating Characteristics

shows this relationship.

The area below the curves of the graph is the region in

which these devices typically do not generate a reset

pulse. This graph was generated using a negative-

going pulse applied to VIN, starting above the actual

reset threshold (VRST) and ending below it by the mag-

nitude indicated (reset-threshold overdrive). As the

magnitude of the transient increases (farther below the

reset threshold), the maximum allowable pulse width

decreases. Typically, a VCC transient that goes 100mV

below the reset threshold and lasts 50µs or less will not

cause a reset pulse to be issued.

Watchdog Input Current

Extended Mode

In extended mode (WDS = VCC), the WDI input is inter-

nally driven through a buffer and series resistor from

the watchdog counter (Figure 8). When WDI is left

unconnected, the watchdog timer is serviced within the

watchdog timeout period by a very brief low-high-low

pulse from the counter chain. For minimum watchdog

input current (minimum overall power consumption),

leave WDI low for the majority of the watchdog timeout

period, pulsing it low-high-low (> 30ns) once within the

period to reset the watchdog timer. If instead WDI is

externally driven high for the majority of the timeout

period, typically 70µA can flow into WDI.

Normal Mode

In normal mode (WDS = GND), the internal buffer that

drives WDI is disabled. In this mode, WDI is a standard

CMOS input and leakage current is typically 100pA,

regardless of whether WDI is high or low.

Ensuring a Valid

RESET

/RESET Output

Down to VCC = 0V (MAX6303/MAX6304)

When VCC falls below 1V, RESET/RESET current sinking

(sourcing) capabilities decline drastically. In the case

of the MAX6303, high-impedance CMOS-logic inputs

connected to RESET can drift to undetermined

voltages. This presents no problem in most applica-

tions, since most µPs and other circuitry do not operate

with VCC below 1V.

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

_______________________________________________________________________________________ 9

MAX6301

VCC

RESET

VCC VCC

RESET

GND

µP

RESET TO

OTHER SYSTEM

COMPONENTS

0.1µF4.7kΩ

Figure 7. Interfacing to µPs with Bidirectional Reset I/O Pins

MAX6301

MAX6302

MAX6303

MAX6304

WATCHDOG

TIMER

TO RESET

GENERATOR

TO MODE

CONTROL

WDI

WDS

Figure 8. Watchdog Input Structure

MAX6301–MAX6304

In those applications where RESET must be valid down

to 0V, adding a pulldown resistor between RESET and

ground sinks any stray leakage currents, holding

RESET low (Figure 9). The value of the pulldown resistor

is not critical; 100kΩis large enough not to load RESET

and small enough to pull RESET to ground. For applica-

tions using the MAX6304, a 100kΩpullup resistor

between RESET and VCC will hold RESET high when

VCC falls below 1V (Figure 10).

Watchdog-Software Considerations

To help the watchdog timer monitor software execution

more closely, set and reset the watchdog input at differ-

ent points in the program, rather than pulsing the

watchdog input high-low-high or low-high-low. This

technique avoids a stuck loop in which the watchdog

timer would continue to be reset within the loop, keeping

the watchdog from timing out.

Figure 11 shows an example of a flow diagram where

the I/O driving the watchdog input is set high at the

beginning of the program, set low at the beginning of

every subroutine or loop, then set high again when the

program returns to the beginning. If the program should

hang in any subroutine the problem would quickly be

corrected, since the I/O is continually set low and the

watchdog timer is allowed to time out, causing a reset

or interrupt to be issued. When using extended mode,

as described in the

Watchdog Input Current

section,

this scheme does result in higher average WDI input

current than does the method of leaving WDI low for the

majority of the timeout period and periodically pulsing it

low-high-low.

Layout Considerations

SRT and SWT are precision current sources. When

developing the layout for the application, be careful to

minimize board capacitance and leakage currents

around these pins. Traces connected to these pins

should be kept as short as possible. Traces carrying

high-speed digital signals and traces with large voltage

potentials should be routed as far from these pins as

possible. Leakage currents and stray capacitance

(e.g., a scope probe) at these pins could cause errors

in the reset and/or watchdog timeout period. When

evaluating these parts, use clean prototype boards to

ensure accurate reset and watchdog timeout periods.

RESET IN is a high-impedance input that is typically

driven by a high-impedance resistor-divider network

(e.g., 1MΩto 10MΩ). Minimize coupling to transient sig-

nals by keeping the connections to this input short. Any

DC leakage current at RESET IN (e.g., a scope probe)

causes errors in the programmed reset threshold. Note

that sensitive pins are located on the GND side of the

device, away from the digital I/O, to simplify board layout.

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

10 ______________________________________________________________________________________

MAX6303

VCC

RESET

VCC

GND

0.1µF

100kΩ

Figure 9. Ensuring RESET Valid to VCC = 0V

MAX6304

VCC

RESET

GND

VCC

100kΩ

0.1µF

Figure 10. Ensuring RESET Valid to VCC = 0V

START

SET WDI

LOW

SUBROUTINE OR

PROGRAM LOOP

SET WDI HIGH

RETURN

END

Figure 11. Watchdog Flow Diagram

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

______________________________________________________________________________________ 11

Ordering Information (continued) Chip Information

PROCESS: CMOS

PART TEMP RANGE PIN-PACKAGE

MAX6302CPA 0°C to +70°C 8 PDIP

MAX6302CSA 0°C to +70°C 8 SO

MAX6302CUA 0°C to +70°C 8 µMAX

MAX6302EPA -40°C to +85°C 8 PDIP

MAX6302ESA -40°C to +85°C 8 SO

MAX6303CPA 0°C to +70°C 8 PDIP

MAX6303CSA 0°C to +70°C 8 SO

MAX6303CUA 0°C to +70°C 8 µMAX

MAX6303EPA -40°C to +85°C 8 PDIP

MAX6303ESA -40°C to +85°C 8 SO

MAX6304CPA 0°C to +70°C 8 PDIP

MAX6304CSA 0°C to +70°C 8 SO

MAX6304CUA 0°C to +70°C 8 µMAX

MAX6304EPA -40°C to +85°C 8 PDIP

MAX6304ESA -40°C to +85°C 8 SO

Devices are available in both leaded and lead(Pb)-free/RoHS-

compliant packaging. Specify lead-free by adding the “+

”

symbol at the end of the part number when ordering.

Package Information

For the latest package outline information and land patterns, go

to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in

the package code indicates RoHS status only. Package draw-

ings may show a different suffix character, but the drawing per-

tains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE OUTLINE NO. LAND

PATTERN NO.

8 PDIP P8-1 21-0043 —

8 SO S8-2 21-0041 90-0096

8 µMAX U8-1 21-0036 90-0092

MAX6301–MAX6304

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 7/96 Initial release —

1 12/05 Added lead-free notation. 1, 11

2 3/07 Updated Typical Operating Circuit.1

3 3/09 Updated Pin Description, Applications Information, Figure 3, and Package

Information.5, 7, 11

4 9/10 Updated Absolute Maximum Ratings, correct part number. 2, 9, 11, 12