PE43602MLI-Z - Peregrine Semiconductor Corp.

Page 1 of 11

The PE 43 602 is a HaR P™-enhanced, high linearity, 6-bit RF

Digital Step Attenuator (DSA) covering a 31.5 dB attenuation

range in 0.5 dB steps. This Peregrine 50Ω RF DSA provides

both a serial and parallel CMOS control interface. It maintains

high attenuation accuracy over frequency and temperature and

exhibits very low insertion loss and low power consumption.

Performance does not change with VDD due to on-board

regulator. This next generation Peregrine DSA is available in a

4x4 mm 24 lead QFN footprint.

The PE43602 is manufactured on Peregrine’s UltraCMOS™

pro c ess, a patented variation of silicon -on-insulator (SOI)

technology on a sapphire substrate, offering the performance

of GaAs with the eco nom y an d i nte gr ation of co nventi on al

CMOS.

Pro duct Specificat ion

50 Ω RF Di gital Attenuator

6-bit, 31.5 dB, 9 kHz - 5.0 GHz

Product Description

PE43602

Features

• HaRP ™-enha nced UltraCMOS™ device

• Attenuati on: 0. 5 dB ste ps to 31 .5- d B

• Hi gh Li ne ar it y: Typical + 5 8 dBm IIP3

• Excellent low-frequency performance

• 3.3 V or 5.0 V Power Supply Voltage

• Fast swit ch sett ling time

• Programming Modes:

• Direct Parallel

• Latc he d Par al lel

• Serial

• High-attenuation state @ power-up (PUP)

• CMOS Compatible

• No DC b locking capacitors required

• Packaged in a 24-lead 4x4x0.85 mm QFN

Figure 1. Package Photo

24-l e ad 4x 4x 0. 85 mm QFN Packag e

Figure 2. Functional Schematic Dia gram

Control Logic Interface

RF Input RF Output

Serial In

LE

CLK

Parallel Control

7

P/S

Product Specification

PE43602

Page 2 of 11

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 4 8 121620242832

Atte nuation Setting (dB)

Attenuation Error (dB)

200MHz 900MHz 1800MHz 2200MHz

3000MHz 4000MHz 5000MHz

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 1000 2000 3000 4000 5000

Frequency (MHz)

Bit Error (dB)

0.5dB State 1dB State 2dB State 4dB State

8dB State 16dB State 31.5dB State

51015202530035

5

10

15

20

25

30

0

35

Attenuation State

Attenuation dB

PE43602 Attenuation

900 MHz

1800 MHz

2200 MHz

3800 MHz

5000 MHz

(dB)

-0.5

0

0.5

1

0 4 8 12 16 20 24 28 32

Attenuation Setting (dB)

Step Error (dB)

200MHz 900MHz 1800MHz 2200MHz

3000MHz 4000MHz 5000MHz

Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V

Parameter Test Condit ions Frequency Min Typical Max Units

Frequency Range 9 kHz 5 GHz

Attenuation Range 0.5 dB Step 0 – 31.5 dB

Insertion Loss 9 kHz ≤ 5 GHz 2.2 2.7 dB

Attenuation Error 0 dB - 31.5 dB Atten uatio n se tt i ngs

0 dB - 31.5 dB Atten uatio n se tt i ngs

9 kH z < 4 G Hz

4 GHz ≤ 5 GHz

±(0.3 + 3)%

+0. 4 + 5%

-0.3 - 3%

dB

Return Loss 9 kHz - 5 GHz 18 dB

Relative Phase All States 9 kHz - 5 GHz 55 deg

P1dB (note 1) Input 20 MHz - 5 GHz 30 32 dBm

IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 5 GHz 58 dBm

Typical Spurious Value 1 MHz -110 dBm

Video Feed Through 10 mVpp

Switching Time 50% DC CTRL to 10% / 90% RF 650 ns

RF Trise/Tfall 10% / 90% RF 400 ns

Sett ling Time RF settled to within 0.05 dB of final value

RBW = 5 MHz, Averaging ON. 4 µs

Performance Plots

*Monotonicity is held so long as Step-Error does not cross below -0.5

Figure 3. 0.5dB Step Error vs. Frequency*

Fig ur e 5. 0. 5d B Major Stat e Bit Erro r Fig ur e 6. 0. 5d B At t enu ati on Err or vs. Frequency

Figure 4. 1dB Atte nuation vs. Attenuation State

Note 1. Please note Maximum Operating Pin (50Ω) of +2 3d Bm as sh ow n in Table 3.

Product Specification

PE43602

Page 3 of 11

30

35

40

45

50

55

60

65

70

0 500 1000 1500 2000 2500 3000 3500 4000 4500

Frequency (MHz)

Input IP3 (dBm)

0dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.5dB

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 4 8 12162024 2832

Attenuation Setting (dB)

Attenuation E rror (dB)

-40C +25C +85C

0

20

40

60

80

100

120

140

012 345678

Frequency (GHz)

Relative Phase Error (Deg)

0dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.5dB

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

0123456789

Frequency (GHz)

Return Loss (dB)

0dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.5dB

-40

-35

-30

-25

-20

-15

-10

-5

0

0123456789

Freque ncy (GHz)

Input Return Loss (dB)

0dB 0.5dB 1dB 2dB

4dB 8dB 16dB 31.5dB

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

01 23456789

Frequency (GHz)

Insertion Loss (dB)

-40C +25C +85C

Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenua tion

@ T = +25C

Figure 9. Output Return Loss vs. Atte nuation

@ T = +25C Figure 10. Relative Phase vs. Frequency

Figure 11. Attenua tion Error vs. Temperature

@ 5 GHz Figure 12. Input IP3 vs. Frequency

Product Specification

PE43602

Page 4 of 11

0

5

10

15

20

25

30

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09

Hz

Pin dBm

Exposed

Solder

Pad

NC

VDD

P/S

GND GND

LE

CLK

SI

C4

C2

C1

C 0.5

C8

RF1

24

23

22

21

20

19

18

17

16

15

14

13

2

3

4

5

6

1

C16

RF2

GND GND

GND

7

8

9

10

11

12

Figure 13. Pin Configurati on (Top View)

Table 2 . Pin Descriptions

Pin No. Pin Name Description

1 GND Ground

2 VDD Power supply pin

3 P/S Seri al/P ar alle l mo de sel ec t

4 GND Ground

5 RF1 RF1 port

6 - 13 GND Ground

14 RF2 RF2 port

15 GND Ground

16 LE Seri al in t er f ac e Latc h Enab le in put

17 CLK Serial interface Clock input

18 SI Seri al in t er f ac e Dat a in put

19 C16 (D6) Parallel control bit, 16 dB

20 C8 (D5) Parallel control bit, 8 dB

21 C4 (D4) Parallel control bit, 4 dB

22 C2 (D3) Parallel control bit, 2 dB

23 C1 (D2) Parallel control bit, 1 dB

24 C0.5 (D1) Parallel control bit, 0.5 dB

Pad dl e G N D Ground f or pr op er operati on

Electrostatic Discharge (ESD) Precautions

When handling t his Ultr aCM OS™ device, obs er v e the

same pr ec autions t hat you would us e with other ESD-

sensit ive devices . Alt hough this devic e contains

circ uitry to protect it from dam age due to ES D,

precautions should be taken t o av oid ex c eeding the

specif ied rating.

Expose d Solder Pad Connection

The exposed solder pad on the bottom of t he pac k age

must be grounded f or pr oper dev ic e oper ation.

Latc h-Up Avoidance

Unlike conventional CMO S devices, UltraCMOS™

devices ar e im m une to latc h- up.

Swi tc hing Frequency

The PE 43602 has a maxim um 25 kHz switc hing r ate.

Switc hing rate is defined to be the speed at which the

DSA can be toggled across attenuation st ates.

Exceeding absolute m ax im um r atings may cause

permanent damage. Operation should be res tricted to

the limits in t he Operating Ranges t able. Operat ion

between operating range m ax im um and abs olute

maxim um for extended periods m ay r educ e r eliability.

Moist u re Sen sit i vit y L evel

The Moisture Sensitivity Level rating for the PE43602 in

the 24-lead 4x4 QFN package is MSL1.

Note : 1. H u ma n B ody M od el (H BM, MIL_STD 88 3 Meth od 301 5. 7)

Figure 14. Maximum Power Handling Capability

Table 3. Operating Ranges

Table 4. Absolute Maximum Ratings

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 6.0 V

VI Voltage on any Digital input -0.3 5.8 V

TST Storage temperature range -65 150 °C

PIN Input power (50Ω)

9 kH z ≤ 20 MHz

20 MHz ≤ 5 GHz

Fig. 14

+23

dBm

VESD ESD voltage ( HBM)1

ESD voltage ( M achine Mod el) 500

100 V

V

Parameter Min Typ Max Units

VDD Power Supply Voltage 3.0 3.3 V

IDD Power Supply Current 70 350 µA

Digital Input High 2.6 5.5 V

PIN Input power ( 50Ω):

9 kHz ≤ 20 MHz

20 MHz ≤ 5 GHz

Fig. 14

+23

dBm

TOP Opera ti ng te m perat u re r a ng e -40 25 85 °C

Digital Input Low 0 1 V

Digital Input Leakage1 15

µA

VDD Power Supply Voltage 5.0 5.5 V

Note 1. Input leakage current per Control pin

Note: Ground C0.5, C1, C2, C4, C8, C16 if not in use.

Product Specification

PE43602

Page 5 of 11

Table 5. Control Voltage

State Bias Condition

Low 0 to +1.0 Vdc at 2 µA (typ)

High +2.6 to +5 Vdc at 10 µA (typ)

Table 6. Latch and Clock Specifications

Latch Enable Function

X Shift Regi st er Cl ocked

↑ Contents of shif t register

trans ferr ed t o attenuat or cor e

Shift Clock

↑

X

Attenuation Wor d Attenuation

Setting

RF1-RF2

D7 D6 D5 D4 D3 D2 D1 D0

(LSB)

L L L L L L L L Reference I.L.

L L L L L L H L 0.5 dB

L L L L L H L L 1 dB

L L L L H L L L 2 dB

L L L H L L L L 4 dB

L L H L L L L L 8 dB

L H L L L L L L 16 dB

L H H H H H H L 31.5 dB

Table 8. Serial Attenuation Word Truth Table

Table 9. Se rial Register Map

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

D7 D6 D5 D4 D3 D2 D1 D0

Attenuation Word

LSB (first in)

MSB (last in)

Bits mus t be set to lo gic low

Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:

Atte nuation Word: Multiply by 4 and convert to binary → 4 * 12.5 dB → 50 → 00110010

Serial Input: 00110010

Parallel Control Setting Attenuation

Setting

RF1-RF2

D5 D4 D3 D2 D1

L L L L L Reference I.L.

L L L L H 0.5 dB

L L L H L 1 dB

L L H L L 2 dB

L H L L L 4 dB

H L L L L 8 dB

L L L L L 16 dB

D6

L

H

H H H H H H 31.5 dB

Table 7. Parallel Truth Table

Product Specification

PE43602

Page 6 of 11

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE43602. The P/S bit provides this

selection, with P/ S=LOW selecting the parallel

interface and P/S=HIGH selecting the serial

interface.

Parallel Mode Interface

The parallel interface consists of six CMOS-

compatible control lines that select the desired

attenuation state, as shown in T abl e 7.

The parallel interface timing requirements are

defined by Fig. 16 (Parallel Interface Timing

Diagram), Table 11 (Pa rallel Interface AC

Characteristics), and switching speed (Table 1).

For latched-parallel programming the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Fig. 16) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

at tenuation state control v alues will change devic e

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

Seri al Int er face

The serial interface is a 8-bit serial-in, parallel-out

shift register buffered by a transparent latch. The 8-

bits make up the Attenuation Word that controls the

DSA. Fig. 15 illustrates a example timing d i agram for

programming a state.

The serial-interface is controlled using three CMOS-

compatible signals: Serial-In (SI), Clock (CLK), and

Latch Enable (LE). The SI and CLK inputs allow

data to be serially entered into the shift register.

Serial data is clocked in LSB first.

The shift register must be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data into the DSA. Attenuation Word truth table

is listed in Table 8. A programming example of the

serial reg i s ter is illustrated in Table 9. The serial

timin g dia gram is illustrated in Fig. 15. It is required

that all parallel pins be grounded when the DSA is

used in serial mode.

Power-up Control Settings

The PE4602 will always init ialize t o the maximum

attenuation setting (31.5 dB) on power-up for both

the serial and latched-parallel modes of operation

and will rema in in this setting un til the u s er latches in

the next programming word. In direct-parallel mode,

the DSA can be preset to any state within the 31.5

dB range by pre-setting the parallel control pins prior

to power-up. In this mode, there is a 400-µs delay

between the time the DSA is powered-up to the time

the desired state is set. During this power-up delay,

the device attenuates to the maximum attenuation

setting (31.5 dB) before defaulting to the user

defined state. If the control pins are left floating in

this mode during power-up, the device will de fault to

the minimum attenuation setting (insertion loss

state).

Dynamic operation between serial and parallel

programming modes is possible.

If the DSA powers up in serial mode (P/S = HIGH),

all the parallel control inputs DI[6:1] must be set to

logic low. Prior to toggling to parallel mode, the DSA

must be programmed serially to ensure D[7] is set to

logic low.

If the DSA powers up in either latched or direct-

parallel mode, all parallel pins DI[6:1] must be set to

logic low prior to toggling to serial mode (P/S

= HIGH), and held low until the DSA has been

programmed serially to ensure bit D[7] is set to logic

low.

The sequencing is only required once on power-

up. Once completed, the DSA may be toggled

between serial and parallel programming modes at

will.

Product Specification

PE43602

Page 7 of 11

Table 11. Parallel and Direct Interface AC Table 10. Serial Interface AC Characteristics

VDD = 3. 3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified

Figure 15. Serial Timing Diagram

Figure 16. Latched-Parallel/Direc t-Parallel Timing Diagram

Symbol Parameter Min Max Unit

TLEPW Latch Enable minimum

pulse width 30 - ns

TDISU Par a ll el da ta set up time 10 0 - ns

TDIH Parallel data hold time 100 - ns

TPSSU Parallel/Serial setup time 100 - ns

TPSIH Parallel/Serial hold time 100 - ns

TPD Digital register delay

(internal) - 10 ns

TDIPD Digital register delay

(internal, direct mode only) - 5 ns

Characteristics

VALID

T

DISU

T

DIH

DI[6:1]

LE

P/S

T

PSSU

T

PSIH

T

LEPW

VALID

DO[6:1]

T

DIPD

T

PD

Symbol Parameter Min. Max. Unit

FCLK Serial clock frequency - 10 MHz

TCLKH Serial clock HIGH time 30 - ns

TCLKL Serial clock LOW time 30 - ns

TLESU Last ser ial clock rising edge

setup time to Latch Enable

rising edge 10 - ns

TLEPW Latch Ena bl e mi ni mu m puls e

width 30 - ns

TSISU Seri al data setup time 10 - ns

TSIH Serial data hold time 10 - ns

TDISU Para llel da ta set up t i me 100 - ns

TDIH Parallel data hold time 100 - ns

TASU Address setup time 100 - ns

TAH Address hold time 100 - ns

TPSSU Parallel/Serial setup time 100 - ns

TPSH Parallel/Serial hold time 100 - ns

TPD Digital register delay (internal) - 10 ns

D[0] and D[7] must be set to logic low

Bits can either be set to logic high or logic low

D[0] D[1] D[2] D[3] D[4] D[5] D[7]

T

SISU

T

CLKL

T

LEPW

T

SIH

T

CLKH

SI

CLK

LE

P/S

T

LESU

T

PSSU

T

PSIH

VALID

T

DIS U

T

PD

T

DIH

D[6]

DI[6:1]

DO[6:0]

Product Specification

PE43602

Page 8 of 11

Evaluation Kit

The Di gi tal Att en ua t or E val u ation Kit boar d was

designed to ease cus t om er ev aluati on of th e

PE43602 Digital Step Attenuator.

Direct-Parallel Programming Procedure

For automated direct-parallel programming,

connect the test harness provided with the EVK

from the parallel port of the PC to the J1 & Serial

header pin and set the D0-D6 SP3T switches to

the ‘MIDDLE’ toggle position. Position the

Pa rallel/S erial (P/ S) select switch to the Para llel

(or left) position. The evaluation software is

written to operate the DSA in either Parallel or

Serial-Addressable Mode. Ensure that the

software is set to program in Direct-Parallel mode.

Using the software, enable or disable each setting

to the desired attenuation state. The software

automatically programs the DSA each time an

attenuation state is enabled or disabled.

For manual direct-parallel programming,

disconnect the test harness provided with the EVK

from the J1 and Serial header pins. Position the

Pa rallel/S erial (P/ S) select switch to the Para llel

(or left) position. The LE pin on the Serial header

must be tied to VDD. Switches D0-D6 are SP3T

switches which enable the user to manually

program the parallel bits. When any input D0-D6

is toggled ‘UP’, logic high is presented to the

paralle l input. When toggled ‘DOWN’, logic low is

presented to the parallel input. Setting D0-D6 to

the ‘MID DL E’ toggle pos iti on pr esents an OPEN,

which forces an on-chip logic low. Table 9 depicts

the parallel programming truth table and Fig. 16

illust rate s the pa ralle l programming timing

diagram.

Latc he d- P ar al l el Programm ing Pr ocedure

For automated latched-parallel programming, the

procedure is identical to the direct-parallel

method. The user only must ensure that Latched-

Parallel is selected in the so ftware.

For manual latched-parallel programming, the

procedure is identical to direct-parallel except now

the LE pin on the Serial header must be logic low

Figure 17. Evaluati on Board Layout

Peregr ine S pec ificat ion 101- 0310

as the parallel bits are applied. The user must

then pulse LE from 0V to VDD and back to 0V to

latch the programming word into the DSA. LE

must be logic low prior to programming the next

word.

Seri al Pr ogramm i ng Pr ocedur e

Po sition the Parallel/Serial (P/S) select switch to

the Serial (or right) position. The evaluation

software is written to operate the DSA in either

Parallel or Serial Mode. Ensure that the software

is set to program in Serial mode. Using the

software, enable or disable each setting to the

desired attenuation state. The software

automatically programs the DSA each time an

attenuation state is enabled or disabled.

Note: Refer ence Figur e 18 f or Evaluation Boar d Schem atic

Product Specification

PE43602

Page 9 of 11

Figure 19. Package Drawing

Figure 18. Evaluation Board Schematic

Peregr ine S pec ificat ion 102- 0379

Z=50 Ohm

De-embeding trace

Z=50 Ohm

43X0X D S A 5 0 Oh m 4x4 ML P24

3

1

2

4

D3

C7

100pF

C1

100pF

3

1

2

4

D0

1

2

J4

SMA

5

4

6

P/S

C6

100pF

3

1

2

4

D4

C4

100pF

3

1

2

4

D5

1

13

3

5

7

22

44

66

88

10 10

12 12

14 14 13

13

9

11

J1

HE ADER 14

1

2

J7

SMA

C3

100pF

C10

100pF

3

1

2

4

D6

1

2

J5

SMA

3

1

2

4

D1

1

2

J6

SMA

C2

100pF

C8

100p F

C9

0.1µ F

3

1

2

4

D2

C5

100pF

1

2

J3

CON 2

1CLOCK

2DATA

3LE

4GND

SERIAL

HE ADER 4

C13

100pF

C14

100p F

1CP25

2VDD

3S/P

4GND

5RF1

6GND

7GND

8GND

9GND

10 GND

11 GND

12 GND

13

GND

14

RF2

15

GND

16

LE

17

CLK

18

SI

19

C16

20

C8

21

C4

22

C2

23

C1

24

CP5

U1

VDD

P/S

D3

D1

D4

D5

P/S

D6

D3

D2

D1

D4

D5

D0

D2

D6

CLK

DATA

LE

D1

D2

D3

D4

D5

D6

D0

VDD

Product Specification

PE43602

Page 10 of 11

Table 12. Ordering Information

Orde r Code Part Marking Des cripti on Package Shipping Method

PE43602 MLI 43602 PE43602G-24QFN 4x4mm-75A Green 24-lead 4x4mm QFN Bulk or tape cut from reel

PE43602 MLI-Z 43602 PE43602G-24QFN 4x4mm-3000C Green 24-lead 4x4mm QFN 3000 units / T&R

EK43602-01 PE43602 -EK PE43602-24QFN 4x4mm-EK Evaluation Kit 1 / Box

Figure 21. Marking Specifications

43602

YYWW

ZZZZZ

YYWW = Date Code

ZZZZZ = Last five digits of Lot Number

Figure 20. Tape and Reel Draw ing

Device Orientation in Tape

Top of

Device

Pin 1

Tape Feed Dire c t ion

A0 = 4.35

B0 = 4.35

K0 = 1.1

Product Specification

PE43602

Page 11 of 11

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Car r oll Par k Drive

San Diego, CA 92121

Tel: 858-731- 9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Q uatre Vents

F-92380 Garches , France

Tel: +33-1- 4741-9173

Fax : +33-1 -4741 -917 3

For a list of r epresentatives in your area, please ref er to our Web site at: www.psem i.com

Data Sheet Identification

Advance Information

The product is in a format ive or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the r ight

to change specificat ions at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data . In the event Peregrine

dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify

customer s of t he intended changes by issuing a CNF

(Customer Notification Form).

The inform ation in t his dat a sheet is believed to be reliable.

Howeve r, Peregrine assum es no liability f or th e use of this

information. Use shall be entirely at t he user’s own r isk.

No pat ent rights or licenses to any circuits described in this

data sheet are im plied or granted t o any third party.

Peregrine’s products are not designed or intended f or use in

devices or system s intended for sur gical im plant, or in other

applications intended to support or sustain life, or in any

application in which t he failur e of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregr ine assum es no liability for damages, including

consequential or incident al damages, arising out of the use of

its product s in such applicat ions.

The Per egr ine name, logo, and UTSi are register ed t r ademarks

and Ultr aCMOS, HaRP, MultiSwitch and DuNE are trademar ks

of Peregr ine Semiconductor Corp.

High-Reliability and Defense Products

Americas

San Diego, CA, USA

Phone: 858-731-9475

Fax: 848-731-9499

Europe/Asia-Pacific

Aix-En-Pr ovence Cedex 3, France

Phone: +33-4- 4239-3361

Fax: +33-4- 4239-7227

Peregri ne Semiconduc tor, Asia Pacific (AP AC)

Shanghai, 200040, P.R. China

Tel: +86-21- 5836-8276

Fax: +86-21-5836-7652

Peregrine Semiconductor, Korea

#B-2607, Kolon Tripolis, 210

Geumgok-dong, Bundang- gu, Seongnam-si

Gyeonggi-do, 463-943 South Korea

Tel: +82-31- 728-3939

Fax: +82-31-728-3940

Peregrine Semiconductor K.K., Japan

Teiko k u Hote l Tower 10B-6

1- 1-1 Uchisa iwa i-ch o, Ch iy o da-k u

Tokyo 100-0011 Japan

Tel: +81-3- 3502-5211

Fax: +81-3- 3502-5213