FSD200M - Fairchild Semiconductor

www.fairchildsemi.com

Rev.1.0.3

Features

• Single Chip 700V Sense FET Power Switch

• Precision Fixed Operating Frequency (134kHz)

• Advanced Burst-Mode operation Consumes under 0.1W

at 265Vac an d no load (FSD210 only )

• Internal Start-up Switch and Soft Start

• Under Voltage Lock Out (UVLO) with Hysteresis

• Pulse by Pulse Current Limit

• Over Load Protection (OLP)

• Internal Thermal Shutdown Function (TSD)

• Auto - Re sta rt Mode

• Freque ncy Modulation for EMI

• FSD200 does not require an auxiliary bias winding

Applications

• Charger & Adaptor for Mobile Phone, PDA & MP3

• Auxiliary Power for White Goods, PC, C-TV & Monitor

Description

The FSD200 and FSD210 are integrated Pulse Width Modu-

lators (PWM) and Sense FETs specially designed for high

performance off-line Switch Mode Power Supplies (SMPS)

with minimal extern al components. Both devices are mono-

lithic high voltage power switching regulators which com-

bine an LDMOS Sense FET with a voltage mode PWM

control block. The integrated PWM controller features in-

clude: a fixed oscillator with frequency modulation for re-

duced EMI, Under Voltage Lock Out (UVLO) protection,

Leading Ed ge Blanking (L EB), optimized gate turn-on/turn-

off driver, thermal shut down protection (TSD), temperature

compensated precision current sources for loop compensa-

tion and fault protection circuitry. When compared to a dis-

crete MOSFET and controller or RCC switching converter

solution, the FSD200 and FSD210 reduce total component

count, design size, weight and at the same time increase effi-

ciency, productivity, and system reliability. The FSD200

eliminates the need for an auxiliary bias winding at a small

cost of increased supply power . Both devices are a basic plat-

form well suited for cost effective designs of flyback convert-

ers.

Table 1. Notes: 1. Typical continuous power in a non-ven-

tilat ed enclo se d ada pt er me as ured at 50°C ambient. 2.

Maximum practical continuous power in an op en frame

design at 50°C ambient. 3. 230 VAC or 100/115 VAC with

doubler.

Typical Circuit

Figure 1. Typical Flyback Application using FSD210

Figure 2. Typical Flyback Application using FSD200

OUTPUT POWER TABLE

PRODUCT 230VAC ±15%(3) 85-265VAC

Adapter(1) Open

Frame(2) Adapter(1) Open

Frame(2)

FSD210 5W 7W 4W 5W

FSD200 5W 7W 4W 5W

FSD210M5W7W4W5W

FSD200M5W7W4W5W

Drain

Source

Vstr

Vfb Vcc

PWM

IN DC

OUT

Drain

Source

Vstr

Vfb Vcc

PWM

IN DC

OUT

FSD210, FSD200

Green Mode Fairchild Power Switch (FPSTM)

FSD210 , FSD2 00

Internal Block Diagram

Figur e 3. Functional Block Diagra m of FSD210

Figure 4. Functi on al Blo ck Diag ram of FSD200 showing i nte rn al hig h vo ltag e reg ulator

UVLO Voltage

Ref H

Vstr

Vcc

Internal

Bias

Rsense

Iover

S/S

3mS

1, 2, 3

OSC

TSD

LEB

OLP

Reset

A/R

DRIVER

Frequency

Modulation

5uA 250uA

Vck

Vth

SFET

Drain

GND

Vfb

BURST

8.7/6.7V

Rsense

Iover

S/S

3mS

1, 2, 3

OSC

TSD

LEB

OLP

Reset

A/R

DRIVER

Frequency

Modulation

5uA 250uA

Vck

Vth

SFET

Drain

GND

Vfb

BURST

UVLO Voltage

Ref.

HV/REG

INTERNAL

BIAS

ON/OFF

Vstr

Vcc

FSD210, FS D2 00

Pin Definitions

Pin Configuration

Figure 5. Pin Configuration (Top View)

Pin Number Pin Name Pin Function Description

1, 2, 3 GND Sense FET source terminal on primary side and internal control ground.

4Vfb

The feedback voltage pin is the inverting input to the PWM comparator with

nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source

connected internally while a capacitor and opto coupler are typically

connected externally. A feedback voltage of 4V triggers overload protection

(OLP). There is a time delay while charging between 3V and 4V using an

internal 5uA current source, which prevents false triggering under transient

conditions but still allows the protection mechanism to operate under true

overload conditions.

5Vcc

FSD210

Positive supply voltage input. Although connected to an auxiliary

transformer winding, current is supplied from pin 8 (Vstr) via an internal

switch during startup (see Internal Block Diagram section). It is not until Vcc

reaches the UVLO upper threshold (8.7V) that the internal start-up switch

opens and device power is supplied via the auxiliary transformer winding.

FSD200

This pin is connected to a storage capacitor. A high voltage regulator

connected between pin 8 (Vstr) and this pin, provides the supply voltage to

the FSD200 at startup and when switching during normal operation. The

FSD200 eliminates the need for auxiliary bias winding and associated

external components.

7Drain

The Drain pin is designed to connect directly to the primary lead of the

transformer and is capable of switching a maximum of 700V. Minimizing the

length of the trace connecting this pin to the transformer will decrease

leakage inductance.

8Vstr

The startup pin connects directly to the rectified AC line voltage source for

both the FSD200 and FSD210. For the FSD210, at start up the internal

switch supplies internal bias and charges an external storage capacitor

placed between the Vcc pin and ground. Once this reaches 8.7V, the

internal current source is disabled. For the FSD200, an internal high voltage

regulator provides a constant supply voltage.

GND

Vfb

Vstr

Drain

Vcc

7-DIP

7-LSOP

FSD210 , FSD2 00

Absolute Maximum Ratings

(Ta=25°C unless otherwise specified)

Thermal Impedance

Note:

1. Free standing without heat sink.

2. Measured on the GND pin close to plastic interface.

3. Soldered to 100mm2 copper clad.

4. Soldered to 300mm2 copper clad.

Parameter Symbol Value Unit

Maximum Supply Voltage (FSD200) V

CC,MAX

10 V

Maximum Supply Voltage (FSD210) V

CC,MAX

20 V

Input Voltage Range V

−0.3 to V

STOP

Operating Junction Temperature. T

+150 °C

Operating Ambient Temperature T

−25 to +85 °C

Storage Temperature Range T

STG

−55 to +150 °C

Parameter Symbol Value Unit

7DIP

Junction-to-Ambient Thermal

(1)

74.07

(3)

°C/W

(1)

60.44

(4)

°C/W

Junction-to-Case Thermal

(2)

22.00 °C/W

7LSOP

Junction-to-Ambient Thermal

(1)

-°C/W

(1)

-°C/W

Junction-to-Case Thermal

(2)

-°C/W

FSD210, FS D2 00

Electrical Characteristics

(Ta=25°C unless otherwise specified)

Note:

1. These parameters, although guaranteed, are not 100% tested in production

2. This parameter is derive d from characteriz ation

Parameter Symbol Condition Min. Typ. Max. Unit

Sense FET SECTION

Drain-Source Breakdown Voltage BV

DSS

= 0V, I

= 100µA 700 - - V

Startup Voltage (Vstr) Breakdown BV

STR

700 - - V

Off-State Current I

DSS

= 560V - - 100 µA

On-State Resistance R

DS(ON)

Tj = 25°C, I

= 25mA - 28 32 Ω

Tj = 100°C, I

= 25mA - 42 48 Ω

Rise Time T

= 325V, I

= 50mA - 100 - ns

Fall Time T

= 325V, l

= 25mA - 50 - ns

CONTROL SECTION

Output Frequency F

OSC

Tj = 25°C 126 134 142 kHz

Output Frequency Modulation F

MOD

Tj = 25°C-±4-kHz

Feedback Source Current I

Vfb = 0V 0.22 0.25 0.28 mA

Maximum Duty Cycle D

MAX

Vfb = 3.5V 60 65 70 %

Minimum Duty Cycle D

MIN

Vfb = 0V 0 0 0 %

UVLO Threshold Voltage (FSD200) V

START

6.377.7V

STOP

After turn on 5.3 6 6.7 V

UVLO Threshold Voltage (FSD210) V

START

8.0 8.7 9.4 V

STOP

After turn on 6.0 6.7 7.4 V

Supply Shunt Regulator (FSD200) V

CCREG

--7-V

Internal Soft Start Time T

S/S

-3-ms

BURST MODE SECTION

Burst Mode Voltage V

BURH

Tj = 25°C0.58 0.64 0.7 V

BURL

0.5 0.58 0.64 V

Hysteresis - 60 - mV

PROTECTION SECTION

Drain to Source Peak Current Limit I

OVER

0.275 0.320 0.365 A

Current Limit Delay

(1)

CLD

Tj = 25°C - 220 - ns

Thermal Shutdown Temperature (Tj)

(1)

125 145 160 °C

Shutdown Feedback Voltage V

- 3.5 4.0 4.5 V

Feedback Shutdown Delay Current I

DELAY

Vfb = 4.0V 3 5 7 µA

Leading Edge Blanking Time

(2)

LEB

200 - - ns

TOTAL DEVICE SECTION

Operating Supply Current (FSD200) I

Vcc = 7V - 600 - µA

Operating Supply Current (FSD210) I

Vcc = 11V - 700 - µA

Start Up Current (FSD200) I

START

Vcc = 0V - 1 1.2 mA

Start Up Current (FSD210) I

START

Vcc = 0V - 700 900 µA

Vstr Supply Voltage Vcc = 0V 20 - - V

FSD210 , FSD2 00

Comparison Between FSDH565 and FSD210

Function FSDH0565 FSD210 FSD210 Advantages

Soft-Start not applicable 3mS • Gradually increasing current limit

during soft-start further reduces peak

current and voltage component

stresses

• Eliminates external components used

for soft-start in most applications

• Reduces or eliminates output

overshoot

Switching Frequency 100kHz 134kHz • Smaller transformer

Frequency Modulation not applicable ±4kHz • Reduced conducted EMI

Burst Mode Operation not applicable Yes-built into

controller • Improve light load efficiency

• Reduces no-load consumption

• Transformer audible noise reduction

Drain Creepage at

Package 1.02mm 3.56mm DIP

3.56mm LSOP • Greater immunity to acting as a result

of build-up of dust, debris and other

contaminants

FSD210, FS D2 00

Typical Performance Characteristics

(These characteristic graphs are normalized at Ta=25℃)

Frequency vs. Temp Operating Current vs. Temp

Peak Current Limit vs. Temp Feedback Source Current vs. Temp

Vstop Voltage vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Feedback SOurce Current (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Peak Current Limit (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Operating Current (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Fosc (kHz)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-25 0 25 50 75 100 125

Junction Temperature (℃)

Vstart (V)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-25 0 25 50 75 100 125

Junction Temperature (℃)

Vstop (V)

Vstart Vol tage vs. Temp

FSD210 , FSD2 00

Typical Performance Characteristics

(Continued)

(These characteristic graphs are normalized at Ta=25℃)

On State Resistance vs. Temp Breakdown Voltage vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Vcc Regulation Voltage (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-25 0 25 50 75 100 125

Junction Temperature (℃)

On State Resistance (Ω)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

BVdss (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

VSD (V)

Vcc Regulation Voltage vs. Temp (for FSD200) Shutdown Feedback Voltage vs. Temp

Start Up Current vs. Temp (for FSD210)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-25 0 25 50 75 100 125

Junction Temperature (℃)

Istart (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Istart (A)

Start Up Current vs. Tem p (for FSD200)

FSD210, FS D2 00

Functional Description

1. Star t up : At startup, the internal high voltage current

source supplies the internal bias and charges the external

Vcc capacitor as shown in figure 7. In the case of the

FSD210, when Vcc reaches 8.7V the device starts switching

and the internal high voltage current source is disabled (see

figure 1). The device continues to switch provided that Vcc

does not drop below 6.7V. For FSD210, after startup, the

bias is supplied from the auxiliary transformer winding. In

the case of FSD200, Vcc is continuously supplied from the

external high voltage source and Vcc is regulated to 7V by

an internal high voltage regulator (HVReg), thus eliminating

the need for an auxiliary winding (see figure 2).

Figure 6. I ntern al sta rtup ci rcuit

Calculating the Vcc capacitor is an important step to design-

ing in the FSD200/210. At initial start-up in both the

FSD200/210, the stand-by maximum current is 100uA, sup-

plying current to UVLO and Vref Block. The charging cur-

rent (i) of the Vcc capacitor is equal to Istr - 100uA. After

Vcc reaches the UVLO start voltage only the bias winding

supplies Vcc current to device. When the bias winding volt-

age is not sufficient, the Vcc level decreases to the UVLO

stop voltage. At this time Vcc oscillates. In order to prevent

this ripple it is recommended that the Vcc capacitor be sized

between 10uF and 47uF.

2. Feedback Control : The FSD200/210 are both voltage

mode devices as shown in Figure 8. Usually, a H11A817

optocoupler and KA431 voltage reference (or a FOD2741

integrated optocoupler and voltage reference) are used to

implement the isolated secondary feedback network. The

feedback voltage is compared with an interna lly gener ated

sawtooth waveform, directly controllin g the dut y cycle.

When the KA431 reference pin voltage exceed s the internal

reference voltage of 2.5 V, the optocoupler LED current

increases pulling down the feedback voltage and reducing

the duty cycle. This event will occur when either th e input

voltage increases or the output load decreases.

Figur e 7. Ch ar ging t he Vcc c apacitor thro ugh Vstr

3. Leading edge blanking (LEB) : At the instant the inter-

nal Sense FET is turned on, there usually exists a high cur-

rent spike through the Sense FET , caused by the primary side

capacitance and secondary side rectifier diode reverse recov-

ery. Exceeding the pulse-by-pulse current limit could ca use

premature termination of the switching pulse (see Protection

Section). To counter this effect, the FPS employs a leading

edge blanking (LEB) circuit. This cir cuit inhibits the over

current comparator for a short time (TLEB) after the Sense

FET is turned on.

Figure 8. PWM and feedback circuit

4. Protection Circuit : The FSD200/210 h as 2 self pr otec-

tion functions: over load protection (OLP) an d thermal shut-

down (TSD). Because these protection circuits are fully

integrated into the IC with no external components, system

Vin,dc

Vstr

Vcc HV

Reg.

Vin,dc

Vstr

Vcc

Istr Istr

FSD210 FSD200

8.7V/

6.7V

Vin,dc

Vin,dcVin,dc

Vin,dc

Vstr

VstrVstr

Vstr

Istr

IstrIstr

Istr

J-FET

J-FETJ-FET

J-FET

UVLO

Vref

max

max max

max

100uA

100uA100uA

100uA

i = Istr-max

i = Istr-max i = Istr-max

i = Istr-max

100uA

100uA100uA

100uA

i = Istr-max 100uA

i = Istr-max 100uAi = Istr-max 100uA

i = Istr-max 100uA

FSD2xx

FSD2xxFSD2xx

FSD2xx

Vcc

VccVcc

Vcc

UVLO

start

UVLO

stop

Vcc

Vcc must not drop

to UVLO stop

Auxilia ry winding

voltage

OSC

Vcc Vref

5uA 0.25mA

VSD

FB Gate

driver

OLP

Vfb

KA431

Cfb

FSD210 , FSD2 00

reliability is improved without a cost increase. If either of

these thresholds are triggered, the FPS starts an auto-restart

cycle. Once the fault condition occurs, switching is termi-

nated and the Sense FET remain s off. This causes Vcc to

fall. When Vcc reaches the UVLO stop voltage

(6.7V:FSD210, 6V:FSD200), the protection is reset and the

internal high voltage curr ent source charges the Vcc capaci-

tor. When Vcc reaches the UVLO start voltage

(8.7V:FSD210,7V:FSD200), the device attempts to resume

normal operation. If the fau lt conditio n is no longer present

start up will be successful. If it is still present the cycle is

repeated (see figure 10) .

Figure 9. Protection block

4.1 Over Load Protection (OLP) : Over load protection

occurs when the load current exceed s a pre-set level due to

an abnormal situation. If this occurs, the prote ction circuit

should be triggered to protect the SMPS. It is possible that a

short term load transient can occu r un der normal operation.

In order to avoid false shutdowns, the over load protection

circuit is designed to trigger after a dela y. Therefore the

device can differentiate between transient over loads and

true fault conditions. The maximum input power is limited

using the pulse-by-pulse curren t limit feature. If the load

tries to

draw more than this, the output voltage will drop below its

set value. This reduces the optocoupler LED current which

in turn reduces the photo-transistor current (see figure 9).

Therefore, the 250uA current source will charge the feed-

back pin capacitor, Cfb, and the feedback voltage, Vfb, will

increase. The input to the feedback comparator is clamped at

3V. Once Vfb reaches 3V, the device switches at maximum

power, the 250uA current source is blocked and the 5uA

source continues to charge Cfb. Once Vfb reaches 4V,

switching stops.and overload protection is triggered. The

resultant shutdown delay time is set by the time required to

charg e Cfb from 3Vto 4Vwith 5uA a s shown in Fig. 10.

4.2 Thermal Shutdown (TSD) : The Sense FET and the

control IC are integrated, making it easier for the contro l IC

to detect the temperature of the Sense FET. Whe n the tem-

perature exceeds approximately 145°C, thermal shutdown is

activated.

Figure 10. Over load protection delay

5. Soft Start : FSD200/210 has an internal soft start circuit

that gradually increases current throu gh the Sens e FET as

shown in figure 11. The soft start time is 3msec in FSD200/

210.

Figure 11. Internal Soft Start

6. Burst operation : In order to minimize the power dissipa-

tion in standby mode, the FSD200/210 implements burst

mode functionality (see figure 12). As the load decreases, the

feedback voltage decreases. As shown in figure 13, the

device automatically enters burst mode when the feedback

voltage drops below V

BURL

(0.58V). At this point switching

stops and the output voltages start to drop at a rate dependant

on standby current load. This causes the feedback voltage to

rise. Once it passes V

BURH

(0.64V) switching starts again.

The feedback voltage falls and the process repeats. Burst

mode operation alternately enables and disables switching of

the power Sense FET thereby redu cing switc hin g loss in

OSC

Vfb

GATE

DRIVER

FSD2xx

OLP, TSD

Protection Block

5uA 250uA

RESET

Vth 4V

OLP

TSD

A/R

Cfb

3VR

Vfb

OLP

t1 t3

t1<<t2, t3

t1 = -1/RC Χ

Χ Χ

Χ ln( 1-v(t1)/R ) v(t1)=3V

t2 = Cfb Χ

Χ Χ

Χ {v(t1+t2)-v(t1)} /

/ /

/ Idelay

FPS Swi t ch ing Area

Idelay (5uA) charges Cfb IC Reset

under Vstop of UVLO

0.2A

0.25A

0.3A

3mS

Iover

FSD200/210

I(A)

FSD210, FS D2 00

standby mo de .

Figure 12. Circuit for burst operation

Figur e 13. Burst mode opera tion

7. Frequency Modulation : EMI re duction can be accom-

plished by modulating the switching frequency of a SMPS.

Fre quency mod ulat ion can redu ce EMI by spreading the

energy over a wider frequency range. The amount of EMI

reduction is directly related to the level of modulation

(Fmod) and the rate of modulation. As can be seen in Figure

14, the frequency changes from 130kHz to 138kHz in 4mS

for the FSD200/FSD210. Frequency modulation allows the

use of a cost effective inductor instead of an AC input mode

choke to satisfy the requirements of world wi de EM I limits.

Figur e 14. Frequency Modulat ion Wavefo rms

Figure 15. FSDH0165 Full Range EMI scan(100kHz, no

Frequency Modulation) with charger set

Figure 16. FSD210 Full Range EMI scan(134kHz, with Fre-

quency Modulation) with charger set

OSC

Vfb

GATE

DRIVER

5uA 250uA

0.64V

/0.58V

on/off

FSD2xx

Burst Operation Block

Vds

0.58V

0.64V

Ids

set

time

138kHz

134kHz

130kHz 8kHz

Turn-on Turn-off

point

Internal

Oscillator

Drain to

Source

voltage

Vds

Waveform

Drain to

Source

current

Frequency(MHz)

Amplitude(dBµV)

CISPR22Q(PK) CISPR22A(AV)

Amplitude(dBµV)

Frequency(MHz)

CISPR22Q(PK) CISPR22A(AV)

FSD210 , FSD2 00

Typical application circuit

Features

• High efficiency (>67% at Universal Input)

• Low zero load power consumption (<100mW at 240Vac) with FSD210

• Low component count

• Enhanced system reliability through various protection functions

• Internal s oft-start (3ms)

• Frequency Mo du lation for low EMI

Key Design Notes

• The constant voltage (CV) mode control is implemented with resistors, R8, R9, R10 and R11, shunt regulator, U2, feedback

capacitor, C9 and opto-coupler, U3.

• The con sta nt curren t (CC ) mode c ontro l is de signe d with res ist ors, R8 , R9, R15, R16, R17 a nd R19 , NPN tr ansisto r, Q1 and

NTC, TH1 . When the vo ltage across current sensing resi stors, R15 ,R16 and R1 7 is 0.7V, the NPN transi stor turns on and the

current through the opto coup ler LED increases. This reduces the feedback voltag e and du ty ratio. Therefore, the output

voltage decreases and the output current is regulated.

• The NTC(negative thermal coe fficient) is used to compensate the temperatu re ch aracteristics of the transistor Q1.

1. Schematic

Application Output power Input voltage Output voltage (Max current)

Cellular Phone Charger 3.38W Universal input (85-265Vac) 5.2V (650mA)

For FSD21x

For FSD21xFor FSD21x

For FSD21x

4uH

330uF 16V

L1 330uH

R19

510R

1N4148

47k

TH1 10k

R15 3R0

39R

KSP2222A

TL431

1N4007

R16 3R0

C9 470nF

TX1

R10

2.2k

4.7uF 400V

100nF

H11A817B

R1 4.7k

4.7UF 400V

33uF 50V

Fuse

1W, 10R

C6 152M-Y, 250Vac

1N4007

H11A817B

4.7M, 1/4W

R17 3R0

1N4007

56R

UF4007

R12

330uF 16V

(5.2V/0.65A)

47k

C10

4.7uF 50V

FSD210

Vstr

Vcc

Drain

GND

Vfb

GND

SB260

4.7M 1/4W

102k 1kV

FSD210, FS D2 00

2. Demo Circuit Part List

3. Transformer Schematic Diagram

4. Winding Specification

5. Electrical Characteristics

TO-92 Type, LM431Vref=2.495V(Typ.)1KA431AZU2

Iover=0.3A, Fairchildsemi0.5A/700V1FSD210

(FSD200)

-CTR 80~ 16 0%1H11A817AU3

DO41 Type1A/1000 V Ultra Fast Dio de1UF4007D5

D0-2 13 Typ e10m A /100V Junction Diode11N4148D6

D0-41 Type2A/60V Scho ttky Diode1SB260D7

Quantity

Ic=600m A, Vce= 30V

1A/1000 V Junctio n R ectifier

Description

TO-92 Typ eKSP2222AQ1

DO41 Type1N4007D1,D2,D3,D4

Requirement/CommentPart #Reference

TO-92 Type, LM431Vref=2.495V(Typ.)1KA431AZU2

Iover=0.3A, Fairchildsemi0.5A/700V1FSD210

(FSD200)

-CTR 80~ 16 0%1H11A817AU3

DO41 Type1A/1000 V Ultra Fast Dio de1UF4007D5

D0-2 13 Typ e10m A /100V Junction Diode11N4148D6

D0-41 Type2A/60V Scho ttky Diode1SB260D7

Quantity

Ic=600m A, Vce= 30V

1A/1000 V Junctio n R ectifier

Description

TO-92 Typ eKSP2222AQ1

DO41 Type1N4007D1,D2,D3,D4

Requirement/CommentPart #Reference

CORE : EE1616

BOBBIN : EE1616(H)

2mm 2mm

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING9 Ts0.40ΦΧ18 →7W4 INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING50 Ts0.16ΦΧ11 →openW3 INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

CENTER SOLENOID

WINDING

18 Ts0.16ΦΧ14 →3W2 INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

SOLENOID WINDING99 Ts0.16ΦΧ11 →2W1 W i ndi n g Meth o dWinding MethodTurnsTurnsWireWirePin (S Pin (S →

→→

→F)F)No.No.

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING9 Ts0.40ΦΧ18 →7W4 INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING50 Ts0.16ΦΧ11 →openW3 INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

CENTER SOLENOID

WINDING

18 Ts0.16ΦΧ14 →3W2 INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

SOLENOID WINDING99 Ts0.16ΦΧ11 →2W1 W i ndi n g Meth o dWinding MethodTurnsTurnsWireWirePin (S Pin (S →

→→

→F)F)No.No.

3,4,7,8 short

100kHz, 1V

50uH1 –2LEAKAGE L 1kHz, 1V1.6mH1 –2INDUCTANCE REMARKSREMARKSSPECIFICATIONSPECIFICATIONTERMINALTERMINALITEMITEM

3,4,7,8 short

100kHz, 1V

50uH1 –2LEAKAGE L 1kHz, 1V1.6mH1 –2INDUCTANCE REMARKSREMARKSSPECIFICATIONSPECIFICATIONTERMINALTERMINALITEMITEM

3,4,7,8 short

100kHz, 1V

50uH1 –2LEAKAGE L 1kHz, 1V1.6mH1 –2INDUCTANCE REMARKSREMARKSSPECIFICATIONSPECIFICATIONTERMINALTERMINALITEMITEM

3,4,7,8 short

100kHz, 1V

50uH1 –2LEAKAGE L 1kHz, 1V1.6mH1 –2INDUCTANCE REMARKSREMARKSSPECIFICATIONSPECIFICATIONTERMINALTERMINALITEMITEM

FSD210, FS D2 00

Typical application circuit

Features

• Non isolation buck converter

• Low component count

• Enhanced system reliability through various protection functions

Key Design Notes

• The output voltage(12V) is regulated with resistors, R1, R2 and R3, zener diode, D3, the transistor, Q1 and the capacitor,

C2. While the FSD210 is off diodes, D1 and D2, are on. At this time the output voltage, 12V, can be sensed by the feedback

components above. This output is also used with bias voltage for the FSD210.

• R, 680K, is to prevent the OLP(over load protection) at startup.

• R, 8.2K, is a dummy resistor to regulate output voltage in light load.

1. Schematic

2. Demo Circuit Part List

Application Output power Input voltage Output voltag e (Max current)

Non Isolation Buck 1.2W Universal dc input

(100 ~ 375Vac) 12V (100mA)

680K

110

4.7uF/400V

R8.2K

750

D3(ZD)

1N759A

GND

KSP2222A

1000uF 16V

47nF/50V

GND

R1 110

FSD21x

Vstr

Vcc

Drain

GND

Vfb

GND

47uF 50V

UF4004

VINDC D2

UF4004

VOUT(12V/100mA)

1mH

TO -92 Type1Q1

DO-35 Type

12VZD/0.5W11N759AZD1

0.5A/700V1FSD210U1

Quantity

1A/1 000V Ultr a F ast Di ode

Description

DO41 TypeUF4007D1,D2,

Requirement/CommentPart #Reference

Ic=200mA, Vcc =40V

1KSP2222A

Iover=0.3A

Quantity

Description

DO41 TypeD1,D2

Requirement/CommentPart #Reference

FSD210, FS D2 00

Layout Considerations (for Flyback Convertor)

Figur e 17. Layout Consid eratio ns for F SD2x0 us i ng 7DIP

#1 : GND

#2 : GND

#3 : GND

#4 : Vfb

#5 : Vcc

#6 : N.C.

#7 : Drain

#8 : Vstr

Copper area for heatsin

FSD210 , FSD2 00

Package Dimensions

7-DIP

FSD210, FS D2 00

Package Dimensions

(Continued)

7-LSOP

FSD210 , FSD2 00

6/21/04 0.0m 001

 2004 Fairchild Semiconductor Corporation

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OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORA TION. As used he rein :

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or syst em who se fai lure to pe rform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effec tiv ene ss.

www.fairchildsemi.com

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MA KE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRO DUCTS HEREIN TO IMPROVE RELIABILITY, FUN CTION OR DESIG N. FAIRCHILD DO ES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIG HTS, NOR THE RIGHTS OF OT HERS.

Ordering Information

Product Number Package Rating Topr (°C)

FSD210 7DIP 700V, 0.5A −25°C to +85°C

FSD200 7DIP 700V, 0.5A −25°C to +85°C

FSD210M 7LSOP 700V, 0.5A −25°C to +85°C

FSD200M 7LSOP 700V, 0.5A −25°C to +85°C