CY62148EV30 MoBL®
4-Mbit (512K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05576 Rev. *U Revised October 18, 2016
4-Mbit (512K × 8) Static RAM
Features
■Very high speed: 45 ns
❐Wide voltage range: 2.20 V to 3.60 V
■Temperature range:
❐Industrial: –40 °C to +85 °C
❐Automotive-A: –40 °C to +85 °C
■Pin compatible with CY62148DV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 7 A (Industrial)
■Ultra low active power
❐Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 36-ball very fine-pitch ball grid array
(VFBGA), 32-pin thin small outline package (TSOP) II, and
32-pin small outline integrated circuit (SOIC) [1] packages
Functional Description
The CY62148EV30 is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
For a complete list of related 1documentation, click here.
A0IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A13
A14
A15
A16
A17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A10
A11
A12
A18
Logic Block Diagram
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Note
1. SOIC package is available only in 55 ns speed bin.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 2 of 19
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 3 of 19
Pin Configuration
VFBGA, SOIC and TSOP II pinouts are as follows. [2, 3]
A
15
V
CC
A
13
A
12
A
5
NC
WE A
7
I/O
4
I/O
5
A
4
I/O
6
I/O
7
V
ss
A
11
A
10
A
1
V
SS
I/O
0
A
2
A
8
A
6
A
3
A
0
V
cc
I/O
1
I/O
2
I/O
3
A
17
A
18
A
16
CE
OE
A
9
A
14
D
E
B
A
C
F
G
H
NC
36-ball VFBGA pinout
Top View
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-pin SOIC/TSOP II pinout
Top View
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
SS
V
CC
A
18
WE
OE
CE
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2
(µA)
f = 1 MHz f = fmax
Min Typ [4] Max Typ [4] Max Typ [4] Max Typ [4] Max
CY62148EV30LL VFBGA Industrial 2.2 3.0 3.6 45 2 2.5 15 20 1 7
TSOP II Industrial /
Automotive-A
SOIC Industrial 2.2 3.0 3.6 55 2 2.5 15 20 1 7
Notes
2. SOIC package is available only in 55 ns speed bin.
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 4 of 19
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ..................................... 55 °C to +125 °C
Supply voltage
to ground potential .......................–0.3 V to VCC(max) + 0.3 V
DC voltage applied to outputs
in High Z State [5, 6] ......................–0.3 V to VCC(max) + 0.3 V
DC input voltage [5, 6] ...................–0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Product Range Ambient
Temperature VCC[7]
CY62148EV30 Industrial /
Automotive-A
–40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-45 (Industrial /
Automotive-A) -55 [8]
Unit
Min Typ [9] Max Min Typ [9] Max
VOH Output high voltage IOH = –0.1 mA 2.0 – – 2.0 – – V
IOH = –1.0 mA, VCC > 2.70 V 2.4 – – 2.4 – – V
VOL Output low voltage IOL = 0.1 mA – – 0.4 – – 0.2 V
IOL = 2.1 mA, VCC > 2.70 V – – 0.4 – – 0.4 V
VIH Input high voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 1.8 – VCC + 0.3 V
VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 2.2 – VCC + 0.3 V
VIL Input low voltage
V
CC
= 2.2 V to 2.7 V
For VFBGA and
TSOP II packages
–0.3 – 0.6 – – – V
For SOIC package – – – –0.3 – 0.4 [10] V
V
CC
= 2.7 V to 3.6 V
For VFBGA and
TSOP II packages
–0.3 – 0.8 – – – V
For SOIC package – – – –0.3 – 0.6 [10]
IIX Input leakage
current
GND < VI < VC–1 – +1 –1 – +1 A
IOZ Output leakage
current
GND < VO < VCC, Output disabled –1 – +1 –1 – +1 A
ICC VCC operating
supply current
f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA, CMOS
levels
– 15 20 – 15 20 mA
f = 1 MHz – 2 2.5 – 2 2.5
ISB1 [11] Automatic CE power
down current –
CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
–1 7 –1 7 A
ISB2 [11] Automatic CE power
down current –
CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–1 7 –1 7 A
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 5 of 19
Capacitance
Parameter [12] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [12] Description Test Conditions 36-ball VFBGA
Package
32-pin TSOP II
Package
32-pin SOIC
Package Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
44.79 59.10 51.57 C/W
JC Thermal resistance
(junction to case)
23.17 12.19 25.01 C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to:
THEVENIN
EQUIVALENT
ALL INPUT PULSES
R
TH
R1
VCC
Parameters 2.50 V 3.0 V Unit
R116667 1103
R215385 1554
RTH 8000 645
VTH 1.20 1.75 V
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 6 of 19
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [13] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR [14] Data retention current VCC = 1.5 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
Industrial /
Automotive-A
–0.87A
tCDR[15] Chip deselect to data
retention time
0––ns
tR[16] Operation recovery time CY62148EV30LL-45 45 – – ns
CY62148EV30LL-55 55 – – ns
Data Retention Waveform
Figure 2. Data Retention Waveform
Notes
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
14. Chip Enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 7 of 19
Switching Characteristics
Over the Operating Range
Parameter [17, 18] Description
-45 (Industrial /
Automotive-A) -55 [19]
Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 –55 –ns
tAA Address to data valid –45 –55 ns
tOHA Data hold from address change 10 –10 –ns
tACE CE LOW to data valid –45 –55 ns
tDOE OE LOW to data valid –22 –25 ns
tLZOE OE LOW to Low Z [20] 5 – 5 – ns
tHZOE OE HIGH to High Z [20, 21] –18 –20 ns
tLZCE CE LOW to Low Z [20] 10 –10 –ns
tHZCE CE HIGH to High Z [20, 21] –18 –20 ns
tPU CE LOW to power up 0 – 0 – ns
tPD CE HIGH to power down –45 –55 ns
Write Cycle [22, 23]
tWC Write cycle time 45 –55 –ns
tSCE CE LOW to write end 35 –40 –ns
tAW Address setup to write end 35 –40 –ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 –40 –ns
tSD Data setup to write end 25 –25 –ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to High Z [20, 21] –18 –20 ns
tLZWE WE HIGH to Low Z [20] 10 –10 –ns
Notes
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
18. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 1 on page 5.
19. SOIC package is available only in 55 ns speed bin.
20. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
21. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
22. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
23. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 8 of 19
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [24, 25]
Figure 4. Read Cycle No. 2 (OE Controlled) [25, 26]
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [27, 28]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA I/O
OE
NOTE
29
Notes
24. Device is continuously selected. OE, CE = VIL.
25. WE is HIGH for read cycles.
26. Address valid before or similar to CE transition LOW.
27. Data I/O is high impedance if OE = VIH.
28. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
29. During this period, the I/Os are in output state. Do not apply input signals.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 9 of 19
Figure 6. Write Cycle No. 2 (CE Controlled) [30, 31]
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [31, 32]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA I/O
NOTE
33
Notes
30. Data I/O is high impedance if OE = VIH.
31. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
32. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
33. During this period, the I/Os are in output state. Do not apply input signals.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 10 of 19
Truth Table
CE [34] WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power down Standby (ISB)
L H L Data out Read Active (ICC)
L H H High Z Output disabled Active (ICC)
L L X Data in Write Active (ICC)
Note
34. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 11 of 19
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62148EV30LL-45BVI 51-85149 36-ball VFBGA Industrial
CY62148EV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free)
CY62148EV30LL-45BVXIT 51-85149 36-ball VFBGA (Pb-free)
CY62148EV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free)
CY62148EV30LL-45ZSXA 51-85095 32-pin TSOP II (Pb-free) Automotive-A
55 CY62148EV30LL-55SXI 51-85081 32-pin SOIC (Pb-free) Industrial
Contact your local Cypress sales representative for availability of these parts.
Option: T = Tape and Reel; Blank = Standard
Temperature Grade: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = BV or ZS or S
BV = 36-ball VFBGA
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 48EX
LL X
-
V30 X
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 12 of 19
Package Diagrams
Figure 8. 36-ball VFBGA (6 × 8 × 1.0 mm) VCF036/BV36/BZ36/BZ36A Package Outline, 51-85149
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER RO
W
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
8.
7.
6.
NOTES:
5.
4.
3.
2.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
SD
b
eE
eD
ME
N
0.25
0.375 BSC
0.75 BSC
0.75 BSC
0.30
36
6
0.35
DIMENSIONS
D1
MD
E1
E
D
A
A1
SYMBOL
0.16
MIN.
-
5.25 BSC
3.75 BSC
8
6.00 BSC
8.00 BSC
NOM.
-1.00
-
MAX.
SE 0.375 BSC
D1
E1
36XØb
A
SD
SE eE
5
6
6
Ø0.25 C
M
CØ0.05 M
AB
E
D
TOP VIEW
BOTTOM VIEW
SIDE VIEW
A1 CORNER
7
0.10
2X C
eD
B
0.10 2X
C
C
A1
0.10 C
0.25 C
DETAIL A
(datum A)
(datum B)
DETAIL A
-
A
METALIZED MARK, INDENTATION OR OTHER MEANS.
"SD" = eD/2 AND "SE" = eE/2.
PLANE PARALLEL TO DATUM C.
"SD" OR "SE" = 0.
SIZE MD X ME.
A1 CORNER
BALLS.
A
1234
B
C
D
E
F
G
H
65
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 13 of 19
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
Package Diagrams (continued)
51-85095 *D
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 14 of 19
Figure 10. 32-pin SOIC (450 Mils) S32.45/SZ32.45 Package Outline, 51-85081
Package Diagrams (continued)
51-85081 *E
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 15 of 19
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CMOS Complementary Metal Oxide Semiconductor
CE Chip Enable
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
µA microampere
mA milliampere
ns nanosecond
pF picofarad
Vvolt
Wwatt
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 16 of 19
Document History Page
Document Title: CY62148EV30 MoBL®, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Region ECN Submission
Date
Orig. of
Change Description of Change
** 223225 See ECN AJU New data sheet.
*A 247373 See ECN SYT Changed status from Advance Information to Preliminary.
Updated Operating Range (Updated Note 7 (Changed VCC stabilization time
from 100 s to 200 s)).
Updated Data Retention Characteristics (Changed maximum value of ICCDR
parameter from 2.0 A to 2.5 A, changed minimum value of tR parameter from
100 s to tRC ns).
Updated Switching Characteristics (Changed minimum value of tOHA
parameter from 6 ns to 10 ns for both 35 ns and 45 ns speed bin, changed
maximum value of tDOE parameter from 15 ns to 18 ns for 35 ns speed bin,
changed maximum value of tHZOE, tHZWE parameters from 12 ns to 15 ns for
35 ns speed bin and 15 ns to 18 ns for 45 ns speed bin, changed minimum
value of tSCE from 25 ns to 30 ns for 35 ns speed bin and 40 ns to 35 ns for
45 ns speed bin, changed maximum value of tHZCE parameter from 12 ns to
18 ns for 35 ns speed bin and 15 ns to 22 ns for 45 ns speed bin, changed
minimum value of tSD parameter from 15 ns to 18 ns for 35 ns speed bin and
20 ns to 22 ns for 45 ns speed bin).
Updated Ordering Information (Changed to include Pb-free Packages).
*B 414807 See ECN ZSD Changed status from Preliminary to Final.
Changed the address of Cypress Semiconductor Corporation on page #1 from
“3901 North First Street” to “198 Champion Court”.
Updated Features (Removed 35 ns speed bin).
Updated Pin Configuration (Changed ball C3 from DNU to NC, removed the
Note “DNU pins have to be left floating or tied to VSS to ensure proper
application.” and its reference, added 32-pin SOIC pinout).
Updated Electrical Characteristics (Removed “L” version of CY62148EV30,
changed maximum value of ICC parameter from 2 mA to 2.5 mA and typical
value of ICC parameter from 1.5 mA to 2 mA at f = 1 MHz, changed typical value
of ICC parameter from 12 mA to 15 mA at f = fmax, changed typical value of ISB1
and ISB2 parameters from 0.7 A to 1 A and maximum value of ISB1 and ISB2
parameters from 2.5 A to 7 A).
Updated AC Test Loads and Waveforms (Changed the AC test load
capacitance value from 50 pF to 30 pF).
Updated Data Retention Characteristics (Changed maximum value of ICCDR
parameter from 2.5 A to 7 A, added typical value of ICCDR parameter).
Updated Switching Characteristics (Changed minimum value of tLZOE
parameter from 3 ns to 5 ns, changed minimum value of tLZCE and tLZWE
parameters from 6 ns to 10 ns, changed maximum value of tHZCE parameter
from 22 ns to 18 ns, changed minimum value of tPWE parameter from 30 ns to
35 ns, changed minimum value of tSD from 22 ns to 25 ns).
Updated Ordering Information (Updated part numbers and replaced the
Package Name column with Package Diagram).
Updated Package Diagrams (Updated 36-pin VFBGA from *B to *C, added
32-pin SOIC package diagram (Figure 10)).
*C 464503 See ECN NXR Updated Product Portfolio (Included Automotive Range).
Updated Operating Range (Included Automotive Range).
Updated Electrical Characteristics (Included Automotive Range).
Updated Data Retention Characteristics (Included Automotive Range).
Updated Switching Characteristics (Included Automotive Range).
Updated Ordering Information (Updated part numbers (Included Automotive
parts and their related information)).
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 17 of 19
*D 833080 See ECN VKN Updated Electrical Characteristics (Added VIL parameter for SOIC package,
added Note 10 and referred the same note in the maximum value of VIL
parameter for SOIC package).
*E 890962 See ECN VKN Updated Features (Added Note 1 and referred the same note in 32-pin SOIC
package).
Updated Product Portfolio (Removed Automotive Range).
Updated Operating Range (Removed Automotive Range).
Updated Electrical Characteristics (Removed Automotive Range, added Note
11 and referred the same note in ISB2 parameter).
Updated Data Retention Characteristics (Removed Automotive Range).
Updated Switching Characteristics (Removed Automotive Range).
Updated Switching Characteristics (Added values for all parameters for 55 ns
Industrial range).
Updated Ordering Information (Updated part numbers).
*F 987940 See ECN VKN Updated Electrical Characteristics (Changed maximum value of VOL
parameter from 0.4 V to 0.2 V for Industrial Range at IOL = 0.1 mA, changed
maximum value of VIL parameter from 0.6 V to 0.4 V for Industrial Range, SOIC
package at VCC = 2.2 V to 2.7 V, updated Note 10, updated Note 11 (made the
note applicable for both ISB2 and ICCDR parameters).
*G 2548575 08/05/08 NXR Updated Features (Included Automotive-A Range).
Updated Product Portfolio (Included Automotive-A Range).
Updated Operating Range (Included Automotive-A Range).
Updated Electrical Characteristics (Included Automotive-A Range).
Updated Data Retention Characteristics (Included Automotive-A Range).
Updated Switching Characteristics (Included Automotive-A Range).
Updated Ordering Information (Updated part numbers (Included Automotive-A
parts and their related information)).
*H 2769239 09/25/09 VKN /
AESA
Updated Ordering Information (Updated part numbers).
*I 2944332 06/04/2010 VKN Updated Truth Table (Added Note 34 and referred the same note in CE
column).
Updated Package Diagrams.
*J 3007403 08/13/2010 AJU Added Ordering Code Definitions.
Updated in new template.
*K 3110202 12/14/2010 PRAS Updated Logic Block Diagram.
Updated Ordering Code Definitions.
*L 3302901 07/06/2011 RAME Updated Functional Description (Removed the reference of AN1064).
Updated Ordering Code Definitions.
Updated Package Diagrams (51-85095).
Updated all the notes.
Updated in new template.
*M 3363097 09/07/2011 AJU Updated Data Retention Characteristics (Corrected Note cross-reference for
ICCDR parameter (Added Note 14 and referred the same note in ICCDR
parameter)).
Updated Package Diagrams (Updated 36-ball VFBGA and 32-pin SOIC
package specs).
*N 3546715 03/09/2012 TAVA Updated Electrical Characteristics (Updated Note 10 (Removed the line “Refer
to AN13470 for details”.)).
*O 3733339 09/04/2012 JISH Minor text edits.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY62148EV30 MoBL®, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Region ECN Submission
Date
Orig. of
Change Description of Change
CY62148EV30 MoBL®
Document Number: 38-05576 Rev. *U Page 18 of 19
*P 4102967 08/23/2013 VINI Updated Switching Characteristics:
Added Note 17 and referred the same note in “Parameter” column.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*Q 4307881 04/09/2014 NILE Updated Switching Characteristics:
Updated description of tPD parameter (Replaced “CE HIGH to power up” with
“CE HIGH to power down”).
*R 4576526 11/21/2014 NILE Updated Functional Description:
Added “For a complete list of related 1documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 23 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 32 and referred the same note in Figure 7.
*S 4802206 06/18/2015 NILE Updated Package Diagrams:
spec 51-85149 – Changed revision from *E to *F.
spec 51-85095 – Changed revision from *B to *D.
Updated to new template.
*T 5234869 04/22/2016 NILE Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions (Added Tape and Reel option).
Updated Package Diagrams:
spec 51-85149 – Changed revision from *F to *G.
Updated to new template.
*U 5480386 10/18/2016 VINI Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated values of JA parameter and JC parameter corresponding to all
packages.
Updated to new template.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY62148EV30 MoBL®, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Region ECN Submission
Date
Orig. of
Change Description of Change
Document Number: 38-05576 Rev. *U Revised October 18, 2016 Page 19 of 19
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
CY62148EV30 MoBL®
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