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PRELIMINARY DATA
August 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M50FLW040A
M50FLW040B
4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)
3V Supply Firmware Hub / Low Pin Count Flash Memory
FEATURES SUMMARY
■FLASH MEMORY
– Compatible with either the LPC interface
or the FWH interface (Intel Spec rev1.1)
used in PC BIOS applications
– 5 Signal Communication Interface
supporting Read and Write Operations
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
■8 BLOCKS OF 64 KBYTES
– 5 blocks of 64 KBytes each
– 3 blocks, subdivided into 16 uniform
sectors of 4 KBytes each
Two blocks at the top and one at the
bottom (M50FLW040A)
One block at the top and two at the bottom
(M50FLW040B)
■ENHANCED SECURITY
– Hardware Write Protect Pins for Block
Protection
– Register-based Read and Write
Protection
■SUPPLY VOLTAGE
–V
CC = 3 to 3.6V for Program, Erase and
Read Operations
–V
PP = 12V for Fast Program and Erase
■TWO INTERFACES
– Auto Detection of Firmware Hub (FWH) or
Low Pin Count (LPC) Memory Cycles for
Embedded Operation with PC Chipsets
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
■PROGRAMMING TIME: 10µs typical
■PROGRAM/ERASE CONTROLLER
– Embedded Program and Erase algorithms
– Status Register Bits
Figure 1. Packages
■PROGRAM/ERASE SUSPEND
– Read other Blocks/Sectors during
Program Suspend
– Program other Blocks/Sectors during
Erase Suspend
■ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (M50FLW040A): 08h
– Device Code (M50FLW040B): 28h
TSOP32 (NB)
8 x 14mm
PLCC32 (K)
TSOP40 (N)
10 x 20mm
M50FLW040A, M50FLW040B
2/52
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram (FWH/LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Addresses (M50FLW040A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Addresses (M50FLW040B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 10
Input/Output Communications (FWH0/LAD0-FWH3/LAD3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input Communication Frame (FWH4/LFRAME).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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M50FLW040A, M50FLW040B
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. LPC Bus Write Field Definitions (1 Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Electronic Signature Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Quadruple Byte Program Command (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Double/Quadruple Byte Program Command (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program/Erase Controller Status (Bit SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Erase Suspend Status (Bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VPP Status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Suspend Status (Bit SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Block Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
M50FLW040A, M50FLW040B
4/52
Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . . 24
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . . 25
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 18. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 24. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15.FWH/LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 26. FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 28. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 29. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 36
Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 37
Figure 20.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 38
Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 38
Figure 21.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 39
5/52
M50FLW040A, M50FLW040B
Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 39
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 34. M50FLW040A Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 35. M50FLW040B Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . . 45
Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 46
Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 47
Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 48
Figure 27.Sector/Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 50
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
M50FLW040A, M50FLW040B
6/52
SUMMARY DESCRIPTION
The M50FLW040 is a 4 Mbit (512Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines, an optional 12V power supply can be used
to reduce the erasing and programming time.
The memory is divided into 8 Uniform Blocks of
64 KBytes each, three of which are divided into 16
uniform sectors of 4 KBytes each (see APPENDIX
A. for details). All blocks and sectors can be
erased independently. So, it is possible to pre-
serve valid data while old data is erased. Blocks
can be protected individually to prevent accidental
program or erase commands from modifying their
contents.
Program and erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
to control the memory is consistent with the JE-
DEC standards.
Two different bus interfaces are supported by the
memory:
■The primary interface, the FWH/LPC
Interface, uses Intel’s proprietary Firmware
Hub (FWH) and Low Pin Count (LPC)
protocol. This has been designed to remove
the need for the ISA bus in current PC
Chipsets. The M50FLW040 acts as the PC
BIOS on the Low Pin Count bus for these PC
Chipsets.
■The secondary interface, the Address/
Address Multiplexed (or A/A Mux) Interface, is
designed to be compatible with current Flash
Programmers, for production line
programming prior to fitting the device in a PC
Motherboard.
The memory is supplied with all the bits erased
(set to ’1’).
7/52
M50FLW040A, M50FLW040B
Figure 2. Logic Diagram (FWH/LPC Interface)
Note: 1. ID3 is Reserved for Future Use (RFU) in LPC mode.
Figure 3. Logic Diagram (A/A Mux Interface)
Table 1. Signal Names (FWH/LPC Interface)
Table 2. Signal Names (A/A Mux Interface)
AI08417B
4
FWH4/LFRAME
FWH0/LAD0
FWH3/LAD3
VCC
M50FLW040A
M50FLW040B
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID31
GPI0-
GPI4
VPP
AI08418B
11
RC
DQ0-DQ7
VCC
M50FLW040A
M50FLW040B
IC
VSS
8
G
W
RB
RP
A0-A10
VPP
FWH0/LAD0-
FWH3/LAD3 Input/Output Communications
FWH4/
LFRAME Input Communication Frame
ID0-ID3 Identification Inputs
GPI0-GPI4 General Purpose Inputs
IC Interface Configuration
RP Interface Reset
INIT CPU Reset
CLK Clock
TBL Top Block Lock
WP Write Protect
RFU Reserved for Future Use. Leave
disconnected
VCC Supply Voltage
VPP Optional Supply Voltage for Fast
Program and Erase Operations
VSS Ground
NC Not Connected Internally
IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
GOutput Enable
WWrite Enable
RC Row/Column Address Select
RB Ready/Busy Output
RP Interface Reset
VCC Supply Voltage
VPP Optional Supply Voltage for Fast
Program and Erase Operations
VSS Ground
NC Not Connected Internally
M50FLW040A, M50FLW040B
8/52
Figure 4. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
Figure 5. TSOP32 Connections
AI08419B
GPI4
NC
FWH4/LFRAME
RFU
17
ID1
ID0
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
RFU
GPI1
TBL
ID3/RFU
ID2
GPI0
WP
9
CLK
VSS
1
RP
VCC
NC
GPI2
RFU
32
VPP
VCC
M50FLW040A
M50FLW040B
GPI3
IC (VIL)
RFU
INIT
RFU
25
VSS
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
RC
RP
A8
VPP
VCC
A9
NC
W
VSS
VCC
NC
DQ7
IC (VIH)
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
VSS
A/A Mux A/A Mux
A/A MuxA/A Mux
AI09742B
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
DQ7
G
NC
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1/LAD1
FWH2/LAD2
GPI3
TBL
ID2
GPI0
WP
NC
NC
RFU
GPI4
NC
FWH4/LFRAME
RFU
FWH3/LAD3
VSS
RFU
RFU
CLK
RP
VPP
VCC M50FLW040A
M50FLW040B
8
1
9
16 17
24
25
32
ID3/RFU
VSS
INIT
IC
NC
GPI2 FWH0/LAD0
GPI1 ID0
NC
NC
IC (VIH)
NC
NC
RC
RP
VPP
VCC
A10
VSS
9/52
M50FLW040A, M50FLW040B
Figure 6. TSOP40 Connections
Table 3. Addresses (M50FLW040A) Table 4. Addresses (M50FLW040B)
Note: Also see APPENDIX A., Table 34. and Table 35. for a full listing of the Block Addresses.
AI08420B
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
VSS
VCC
DQ7
G
RB
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1
FWH1/LAD1
FWH2/LAD2
GPI3
TBL
ID2
GPI0
WP
NC
VCC
NC
IC (VIL)
RFU
GPI4
NC
VSS
FWH4/LFRAME
RFU
FWH3/LAD3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50FLW040A
M50FLW040B
10
1
11
20 21
30
31
40
ID3/RFU
NC INIT
NC RFU
GPI2 FWH0/LAD0
GPI1 ID0
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC
Block
Size
(KByte) Address Range Sector Size (KByte)
64 70000h-7FFFFh 16 x 4KBytes
64 60000h-6FFFFh 16 x 4KBytes
64 50000h- 5FFFFh
5 x 64KBytes
64 40000h- 4FFFFh
64 30000h-3FFFFh
64 20000h-2FFFFh
64 10000h-1FFFFh
64 00000h-0FFFFh 16 x 4KBytes
Block
Size
(KByte) Address Range Sector Size (KByte)
64 70000h-7FFFFh 16 x 4KBytes
64 60000h- 6FFFFh
5 x 64KBytes
64 50000h- 5FFFFh
64 40000h- 4FFFFh
64 30000h-3FFFFh
64 20000h-2FFFFh
64 10000h-1FFFFh 16 x 4KBytes
64 00000h-0FFFFh 16 x 4KBytes
M50FLW040A, M50FLW040B
10/52
SIGNAL DESCRIPTIONS
There are two distinct bus interfaces available on
this device. The active interface is selected before
power-up, or during Reset, using the Interface
Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub/Low Pin Count (FWH/LPC) Signal
Descriptions section and the Address/Address
Multiplexed (A/A Mux) Signal Descriptions sec-
tion, respectively, while the supply signals are dis-
cussed in the Supply Signal Descriptions section.
Firmware Hub/Low Pin Count (FWH/LPC)
Signal Descriptions
Please see Figure 2. and Table 1..
Input/Output Communications (FWH0/LAD0-
FWH3/LAD3). All Input and Output Communica-
tions with the memory take place on these pins.
Addresses and Data for Bus Read and Bus Write
operations are encoded on these pins.
Input Communication Frame (FWH4/
LFRAME). The Input Communication Frame
(FWH4/LFRAME) signal indicates the start of a
bus operation. When Input Communication Frame
is Low, VIL, on the rising edge of the Clock, a new
bus operation is initiated. If Input Communication
Frame is Low, VIL, during a bus operation then the
operation is aborted. When Input Communication
Frame is High, VIH, the current bus operation is ei-
ther proceeding or the bus is idle.
Identification Inputs (ID0-ID3). Up to 16 memo-
ries can be addressed on a bus, in the Firmware
Hub (FWH) mode. The Identification Inputs allow
each device to be given a unique 4-bit address. A
‘0’ is signified on a pin by driving it Low, VIL, or
leaving it floating (since there is an internal pull-
down resistor, with a value of RIL). A ‘1’ is signified
on a pin by driving it High, VIH (and there will be a
leakage current of ILI2 through the pin).
By convention, the boot memory must have ad-
dress ‘0000’, and all additional memories are giv-
en addresses, allocated sequentially, from ‘0001’.
In the Low Pin Count (LPC) mode, the identifica-
tion Inputs (ID0-ID2) can address up to 8 memo-
ries on a bus. In the LPC mode, the ID3 pin is
Reserved for Future Use (RFU). The value on ad-
dress A19-A21 is compared to the hardware strap-
ping on the ID0-ID2 pins to select the memory that
is being addressed. For an address bit to be ‘1’,
the corresponding ID pin can be left floating or
driven Low, VIL (again, with the internal pull-down
resistor, with a value of RIL). For an address bit to
be ‘0’, the corresponding ID pin must be driven
High, VIH (and there will be a leakage current of
ILI2 through the pin, as specified in Table 24.). For
details, see Table 5..
General Purpose Inputs (GPI0-GPI4). The
General Purpose Inputs can be used as digital in-
puts for the CPU to read, with their contents being
available in the General Purpose Inputs Register.
The pins must have stable data throughout the en-
tire cycle that reads the General Purpose Input
Register. These pins should be driven Low, VIL, or
High, VIH, and must not be left floating.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the FWH/LPC in-
terface or the Address/Address Multiplexed (A/A
Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during
operation of the memory device, except for select-
ing the desired interface in the period before pow-
er-up or during a Reset.
To select the FWH/LPC Interface, the Interface
Configuration pin should be left to float or driven
Low, VIL. To select the Address/Address Multi-
plexed (A/A Mux) Interface, the pin should be driv-
en High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
current of ILI2 through each pin when pulled to VIH.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the device. When Interface
Reset (RP) is driven Low, VIL, the memory is in
Reset mode (the outputs go to high impedance,
and the current consumption is minimized). When
RP is driven High, VIH, the device is in normal op-
eration. After exiting Reset mode, the memory en-
ters Read mode.
CPU Reset (INIT). The CPU Reset, INIT, signal
is used to Reset the device when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3.
The Clock conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 7) from
being changed. When Top Block Lock, TBL, is
driven Low, VIL, program and erase operations in
the Top Block have no effect, regardless of the
state of the Lock Register. When Top Block Lock,
TBL, is driven High, VIH, the protection of the Block
is determined by the Lock Register. The state of
Top Block Lock, TBL, does not affect the protec-
tion of the Main Blocks (Blocks 0 to 6). For details,
see APPENDIX A..
Top Block Lock, TBL, must be set prior to a pro-
gram or erase operation being initiated, and must
not be changed until the operation has completed,
otherwise unpredictable results may occur. Simi-
larly, unpredictable behavior is possible if WP is
11/52
M50FLW040A, M50FLW040B
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
driven Low, VIL, Program and Erase operations in
the Main Blocks have no effect, regardless of the
state of the Lock Register. When Write Protect,
WP, is driven High, VIH, the protection of the Block
is determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 7). For details, see APPEN-
DIX A..
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated, and must not be
changed until the operation has completed other-
wise unpredictable results may occur. Similarly,
unpredictable behavior is possible if WP is
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Reserved for Future Use (RFU). These pins do
not presently have assigned functions. They must
be left disconnected, except for ID3 (when in LPC
mode) which can be left connected. The electrical
characteristics for this signal are as described in
the “Identification Inputs (ID0-ID3).” section.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
Please see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A18). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is to be written to
or read from the memory. They output the data
stored at the selected address during a Bus Read
operation. During Bus Write operations they carry
the commands that are sent to the Command In-
terface of the internal state machine. The Data In-
puts/Outputs, DQ0-DQ7, are latched during a Bus
Write operation.
Output Enable (G). The Output Enable signal, G,
controls the output buffers during a Bus Read op-
eration.
Write Enable (W). The Write Enable signal, W,
controls the Bus Write operation of the Command
Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs are to be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on its rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the device’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the de-
vice is busy with a program or erase operation,
and it will not accept any additional program or
erase command (except for the Program/Erase
Suspend command). When Ready/Busy is High,
VOH, the memory is ready for any read, program or
erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (read, pro-
gram, erase, etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This is to prevent Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time, the operation aborts, and the memory
contents that were being altered will be invalid. Af-
ter VCC becomes valid, the Command Interface is
reset to Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program command
description in A/A Mux interface and the Double/
Quadruple Byte Program command description in
FWH mode) and Fast Erase options of the memo-
ry.
When VPP = VCC, program and erase operations
take place as normal. When VPP = VPPH, Fast Pro-
gram and Erase operations are used. Any other
voltage input to VPP will result in undefined behav-
ior, and should not be used.
VPP should not be set to VPPH for more than
80 hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt-
age measurements.
M50FLW040A, M50FLW040B
12/52
Table 5. Memory Identification Input Configuration (LPC mode)
BUS OPERATIONS
The two interfaces, A/A Mux and FWH/LPC, sup-
port similar operations, but with different bus sig-
nals and timings. The Firmware Hub/Low Pin
Count (FWH/LPC) Interface offers full functional-
ity, while the Address/Address Multiplexed (A/A
Mux) Interface is orientated for erase and program
operations.
See the sections below, The Firmware Hub/Low
Pin Count (FWH/LPC) Bus Operations and Ad-
dress/Address Multiplexed (A/A Mux) Bus Opera-
tions, for details of the bus operations on each
interface.
Firmware Hub/Low Pin Count (FWH/LPC) Bus
Operations
The M50FLW040 automatically identifies the type
of FWH/LPC protocol from the first received nibble
(START nibble) and decodes the data that it re-
ceives afterwards, according to the chosen FWH
or LPC mode. The Firmware Hub/Low Pin Count
(FWH/LPC) Interface consists of four data signals
(FWH0/LAD0-FWH3/LAD3), one control line
(FWH4/LFRAME) and a clock (CLK).
Protection against accidental or malicious data
corruption is achieved using two additional signals
(TBL and WP). And two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data, control and clock signals are designed
to be compatible with PCI electrical specifications.
The interface operates with clock speeds of up to
33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations are used to read
from the memory cells, specific registers in the
Command Interface or Firmware Hub/Low Pin
Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when
the Input Communication Frame, FWH4/
LFRAME, is Low, VIL, and the correct Start cycle
is present on FWH0/LAD0-FWH3/LAD3. On sub-
sequent clock cycles the Host will send to the
memory:
■ID Select, Address and other control bits on
FWH0-FWH3 in FWH mode.
■Type+Dir Address and other control bits on
LAD0-LAD3 in LPC mode.
The device responds by outputting Sync data until
the wait states have elapsed, followed by Data0-
Data3 and Data4-Data7.
See Table 6. and Table 8., and Figure 7. and Fig-
ure 9., for a description of the Field definitions for
each clock cycle of the transfer. See Table 26.,
and Figure 15., for details on the timings of the sig-
nals.
Bus Write. Bus Write operations are used to write
to the Command Interface or Firmware Hub/Low
Pin Count Registers. A valid Bus Write operation
starts on the rising edge of the Clock signal when
Input Communication Frame, FWH4/LFRAME, is
Low, VIL, and the correct Start cycle is present on
FWH0/LAD0-FWH3/LAD3. On subsequent Clock
cycles the Host will send to the memory:
■ID Select, Address, other control bits, Data0-
Data3 and Data4-Data7 on FWH0-FWH3 in
FWH mode.
■Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-
LAD3.
The device responds by outputting Sync data until
the wait states have elapsed.
Memory Number ID2 ID1 ID0 A21 A20 A19
1 (Boot memory) VIL or float VIL or float VIL or float 111
2VIL or float VIL or float VIH 110
3VIL or float VIH VIL or float 101
4VIL or float VIH VIH 100
5VIH VIL or float VIL or float 011
6VIH VIL or float VIH 010
7VIH VIH VIL or float 001
8VIH VIH VIH 000
13/52
M50FLW040A, M50FLW040B
See Table 7. and Table 9., and Figure 8. and Fig-
ure 10., for a description of the Field definitions for
each clock cycle of the transfer. See Table 26.,
and Figure 15., for details on the timings of the sig-
nals.
Bus Abort. The Bus Abort operation can be used
to abort the current bus operation immediately. A
Bus Abort occurs when FWH4/LFRAME is driven
Low, VIL, during the bus operation. The device
puts the Input/Output Communication pins,
FWH0/LAD0-FWH3/LAD3, to high impedance.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received. A Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command. The bus, however, will be released
immediately.
Standby. When FWH4/LFRAME is High, VIH, the
device is put into Standby mode, where FWH0/
LAD0-FWH3/LAD3 are put into a high-impedance
state and the Supply Current is reduced to the
Standby level, ICC1.
Reset. During the Reset mode, all internal circuits
are switched off, the device is deselected, and the
outputs are put to high-impedance. The device is
in the Reset mode when Interface Reset, RP, or
CPU Reset, INIT, is driven Low, VIL. RP or INIT
must be held Low, VIL, for tPLPH. The memory re-
verts to the Read mode upon return from the Re-
set mode, and the Lock Registers return to their
default states regardless of their states before Re-
set. If RP or INIT goes Low, VIL, during a Program
or Erase operation, the operation is aborted and
the affected memory cells no longer contain valid
data. The device can take up to tPLRH to abort a
Program or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional-style interface. The sig-
nals consist of a multiplexed address signals (A0-
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH)/Low Pin Count (LPC) Interface are
available; these include all the Commands but ex-
clude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected, all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to read
the contents of the Memory Array, the Electronic
Signature or the Status Register. A valid Bus Read
operation begins by latching the Row Address and
Column Address signals into the memory using
the Address Inputs, A0-A10, and the Row/Column
Address Select RC. Write Enable (W) and Inter-
face Reset (RP) must be High, VIH, and Output
Enable, G, Low, VIL. The Data Inputs/Outputs will
output the value, according to the timing con-
straints specified in Figure 17., and Table 28..
Bus Write. Bus Write operations are used to write
to the Command Interface. A valid Bus Write oper-
ation begins by latching the Row Address and Col-
umn Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH; and Write En-
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 18., and Table 29., for details
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During the Reset mode, all internal circuits
are switched off, the device is deselected, and the
outputs are put at high-impedance. The device is
in the Reset mode when RP is Low, VIL. RP must
be held Low, VIL for tPLPH. If RP goes Low, VIL,
during a Program or Erase operation, the opera-
tion is aborted, and the affected memory cells no
longer contain valid data. The memory can take up
to tPLRH to abort a Program or Erase operation.
M50FLW040A, M50FLW040B
14/52
Table 6. FWH Bus Read Field Definitions
Figure 7. FWH Bus Read Waveforms
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
3-9 7 ADDR XXXX I
A 28-bit address is transferred, with the most significant nibble
first. For the multi-byte read operation, the least significant bits
(MSIZE of them) are treated as Don’t Care, and the read operation
is started with each of these bits reset to 0. Address lines A19-21
and A23-27 are treated as Don’t Care during a normal memory
array access, with A22=1, but are taken into account for a register
access, with A22=0. (See Table 15.)
10 1 MSIZE XXXX I
This one clock cycle is driven by the host to determine the number
of Bytes that will be transferred. M50FLW040 supports: single
Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer
(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).
11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
12 1 TAR 1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not yet
available. Two wait-states are always included.
15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available during the next clock cycle.
16-17 M=2n DATA XXXX O
Data transfer is two CLK cycles, starting with the least significant
nibble. If multi-Byte read operation is enabled, repeat cycle-16 and
cycle-17 n times, where n = 2MSIZE.
previous
+1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate
a turnaround cycle.
previous
+1 1TAR
1111b
(float) N/A The FWH Flash Memory floats its outputs, the host takes control
of FWH0-FWH3.
AI08433B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE TAR SYNC DATA TAR
117123M2
15/52
M50FLW040A, M50FLW040B
Table 7. FWH Bus Write Field Definitions
Figure 8. FWH Bus Write Waveforms
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1110b I On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
3-9 7 ADDR XXXX I
A 28-bit address is transferred, with the most significant nibble
first. Address lines A19-21 and A23-27 are treated as Don’t
Care during a normal memory array access, with A22=1, but are
taken into account for a register access, with A22=0. (See Table
15.)
10 1 MSIZE XXXX I 0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b
(Quadruple Byte Transfer).
11-18 M=2/4/8 DATA XXXX I
Data transfer is two cycles, starting with the least significant
nibble. (The first pair of nibbles is that at the address with A1-
A0 set to 00, the second pair with A1-A0 set to 01, the third
pair with A1-A0 set to 10, and the fourth pair with A1-A0 set
to 11. In Double Byte Program the first pair of nibbles is that at
the address with A0 set to 0, the second pair with A0 set to 1)
previous
+1 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
previous
+1 1TAR
1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3 during
this cycle.
previous
+1 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
previous
+1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
previous
+1 1TAR
1111b
(float) N/A The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
AI08434B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
1171M212
M50FLW040A, M50FLW040B
16/52
Table 8. LPC Bus Read Field Definitions (1-Byte)
Figure 9. LPC Bus Read Waveforms (1-Byte)
Clock Cycle
Number
Clock
Cycle
Count Field LAD0-
LAD3 Memory
I/O Description
1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a
LPC cycle.
21
CYCTYPE
+ DIR 0100b I
Indicates the type of cycle and selects 1-byte reading. Bits
3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b
for read. Bit 0 is Don’t Care.
3-10 8 ADDR XXXX I
A 32-bit address is transferred, with the most significant
nibble first. A23-A31 must be set to 1. A22=1 for memory
access, and A22=0 for register access. Table 5. shows the
appropriate values for A21-A19.
11 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
12 1 TAR 1111b
(float) OThe LPC Flash Memory takes control of LAD0-LAD3
during this cycle.
13-14 2 WSYNC 0101b O
The LPC Flash Memory drives LAD0-LAD3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
15 1 RSYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least
significant nibble.
18 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
19 1 TAR 1111b
(float) N/A The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
AI04429
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START CYCTYPE
+ DIR ADDR TAR SYNC DATA TAR
1182322
17/52
M50FLW040A, M50FLW040B
Table 9. LPC Bus Write Field Definitions (1 Byte)
Figure 10. LPC Bus Write Waveforms (1 Byte)
Table 10. A/A Mux Bus Operations
Clock
Cycle
Number
Clock
Cycle
Count Field LAD0-
LAD3 Memory
I/O Description
1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
21
CYCTY
PE +
DIR
011Xb I
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 1b for write. Bit 0 is don’t
care (X).
3-10 8 ADDR XXXX I
A 32-bit address is transferred, with the most significant
nibble first. A23-A31 must be set to 1. A22=1 for memory
access, and A22=0 for register access. Table 5. shows the
appropriate values for A21-A19.
11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant
nibble.
13 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
14 1 TAR 1111b
(float) OThe LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
15 1 SYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
16 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
17 1 TAR 1111b
(float) N/A The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
Operation G WRP VPP DQ7-DQ0
Bus Read VIL VIH VIH Don't Care Data Output
Bus Write VIH VIL VIH VCC or VPPH Data Input
Output Disable VIH VIH VIH Don't Care Hi-Z
Reset VIL or VIH VIL or VIH VIL Don't Care Hi-Z
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START CYCTYPE
+ DIR ADDR DATA TAR SYNC TAR
1182212
M50FLW040A, M50FLW040B
18/52
COMMAND INTERFACE
All Bus Write operations to the device are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings, and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface reverts to the Read mode
when power is first applied, or when exiting from
Reset. Command sequences must be followed ex-
actly. Any invalid combination of commands will be
ignored. See Table 11. for the available Command
Codes.
Table 11. Command Codes
The following commands are the basic commands
used to read from, write to, and configure the de-
vice. The following text descriptions should be
read in conjunction with Table 13..
Read Memory Array Command. The Read
Memory Array command returns the device to its
Read mode, where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
device to Read mode. Once the command is is-
sued, the device remains in Read mode until an-
other command is issued. From Read mode, Bus
Read operations access the memory array.
If the Program/Erase Controller is executing a Pro-
gram or Erase operation, the device will not accept
any Read Memory Array commands until the oper-
ation has completed.
For a multibyte read, in the FWH mode, the ad-
dress, that was transmitted with the command, will
be automatically aligned, according to the MSIZE
granularity. For example, if MSIZE=7, regardless
of any values that are provided for A6-A0, the first
output will be from the location for which A6-A0 are
all ‘0’s.
Read Status Register Command. The Read
Status Register command is used to read the Sta-
tus Register. One Bus Write cycle is required to is-
sue the Read Status Register command. Once the
command is issued, subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The
Read Electronic Signature command is used to
read the Manufacturer Code and the Device Code.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the com-
mand is issued, the Manufacturer Code and De-
vice Code can be read using conventional Bus
Read operations, and the addresses shown in Ta-
ble 12..
Table 12. Electronic Signature Codes
Note: 1. A22 should be ‘1’, and the ID lines and upper address bits
should be set according to the rules illustrated in Table 5.,
Table 6. and Table 8..
The device remains in this mode until another
command is issued. That is, subsequent Bus
Read operations continue to read the Manufactur-
er Code, or the Device Code, and not the Memory
Array.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time.
The Program command works by changing appro-
priate bits from ‘1’ to ‘0’. (It cannot change a bit
from ‘0’ back to ‘1’. Attempting to do so will not
modify the value of the bit. Only the Erase com-
mand can set bits back to ‘1’. and does so for all of
the bits in the block.)
Two Bus Write operations are required to issue the
Program command. The second Bus Write cycle
latches the address and data, and starts the Pro-
gram/Erase Controller.
Hexa-
decimal Command
10h
Alternative Program Setup, Double/
Quadruple Byte Program Setup, Chip
Erase Confirm
20h Block Erase Setup
32h Sector Erase Setup
40h Program, Double/Quadruple Byte
Program Setup
50h Clear Status Register
70h Read Status Register
80h Chip Erase Setup
90h Read Electronic Signature
B0h Program/Erase Suspend
D0h Program/Erase Resume, Block Erase
Confirm, Sector Erase Confirm
FFh Read Memory Array
Code Address1Data
Manufacturer Code ...00000h 20h
Device Code M50FLW040A
M50FLW040B ...00001h 08h
28h
19/52
M50FLW040A, M50FLW040B
Once the command is issued, subsequent Bus
Read operations read the value in the Status Reg-
ister. (See the section on the Status Register for
details on the definitions of the Status Register
bits.)
If the address falls in a protected block, the Pro-
gram operation will abort, the data in the memory
array will not be changed, and the Status Register
will indicate the error.
During the Program operation, the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands are ignored.
See Figure 22., for a suggested flowchart on using
the Program command. Typical Program times are
given in Table 18..
Quadruple Byte Program Command (A/A Mux
Interface). The Quadruple Byte Program Com-
mand is used to program four adjacent Bytes in
the memory array at a time. The four Bytes must
differ only for addresses A0 and A1. Programming
should not be attempted when VPP is not at VPPH.
Five Bus Write operations are required to issue the
command. The second, third and fourth Bus Write
cycles latch the respective addresses and data of
the first, second and third Bytes in the Program/
Erase Controller. The fifth Bus Write cycle latches
the address and data of the fourth Byte and starts
the Program/Erase Controller. Once the command
is issued, subsequent Bus Read operations read
the value in the Status Register. (See the section
on the Status Register for details on the definitions
of the Status Register bits.)
During the Quadruple Byte Program operation, the
memory will only accept the Read Status Register
and Program/Erase Suspend commands. All other
commands are ignored.
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and at-
tempting to do so will not modify its value. One of
the erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 24., for a suggested flowchart on using
the Quadruple Byte Program command. Typical
Quadruple Byte Program times are given in Table
18..
Double/Quadruple Byte Program Command
(FWH Mode). The Double/Quadruple Byte Pro-
gram Command can be used to program two/four
adjacent Bytes to the memory array at a time. The
two Bytes must differ only for address A0; the four
Bytes must differ only for addresses A0 and A1.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
start address and two/four data Bytes and starts
the Program/Erase Controller. Once the command
is issued, subsequent Bus Read operations read
the contents of the Status Register. (See the sec-
tion on the Status Register for details on the defi-
nitions of the Status Register bits.)
During the Double/Quadruple Byte Program oper-
ation the memory will only accept the Read Status
register and Program/Erase Suspend commands.
All other commands are ignored.
Note that the Double/Quadruple Byte Program
command cannot change a bit set to ‘0’ back to ‘1’
and attempting to do so will not modify its value.
One of the erase commands must be used to set
all of the bits in the block to ‘1’.
See Figure 23., for a suggested flowchart on using
the Double/Quadruple Byte Program command.
Typical Double/Quadruple Byte Program times
are given in Table 18..
Chip Erase Command. The Chip Erase Com-
mand erases the entire memory array, setting all
of the bits to ‘1’. All previous data in the memory
array are lost. This command, though, is only
available under the A/A Mux interface.
Two Bus Write operations are required to issue the
command, and to start the Program/Erase Con-
troller. Once the command is issued, subsequent
Bus Read operations read the contents of the Sta-
tus Register. (See the section on the Status Reg-
ister for details on the definitions of the Status
Register bits.)
Erasing should not be attempted when VPP is not
at VPPH, otherwise the result is uncertain.
During the Chip Erase operation, the memory will
only accept the Read Status Register command.
All other commands are ignored.
See Figure 26., for a suggested flowchart on using
the Chip Erase command. Typical Chip Erase
times are given in Table 18..
Block Erase Command. The Block Erase com-
mand is used to erase a block, setting all of the bits
to ‘1’. All previous data in the block are lost.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
block address and starts the Program/Erase Con-
troller. Once the command is issued, subsequent
Bus Read operations read the contents of the Sta-
tus Register. (See the section on the Status Reg-
ister for details on the definitions of the Status
Register bits.)
If the block is protected (FWH/LPC only) then the
Block Erase operation will abort, the data in the
block will not be changed, and the Status Register
will indicate the error.
During the Block Erase operation the memory will
only accept the Read Status Register and Pro-
gram/Erase Suspend commands. All other com-
mands are ignored.
M50FLW040A, M50FLW040B
20/52
See Figure 27., for a suggested flowchart on using
the Block Erase command. Typical Block Erase
times are given in Table 18..
Sector Erase Command. The Sector Erase
command is used to erase a Uniform 4-KByte Sec-
tor, setting all of the bits to ‘1’. All previous data in
the sector are lost.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
Sector address and starts the Program/Erase
Controller. Once the command is issued, subse-
quent Bus Read operations read the contents of
the Status Register. (See the section on the Status
Register for details on the definitions of the Status
Register bits.)
If the Block to which the Sector belongs is protect-
ed (FWH/LPC only) then the Sector Erase opera-
tion will abort, the data in the Sector will not be
changed, and the Status Register will indicate the
error.
During the Sector Erase operation the memory will
only accept the Read Status Register and Pro-
gram/Erase Suspend commands. All other com-
mands are ignored.
See Figure 27., for a suggested flowchart on using
the Sector Erase Command. Typical Sector Erase
times are given in Table 18..
Clear Status Register Command. The Clear
Status Register command is used to reset Status
Register bits SR1, SR3, SR4 and SR5 to ‘0’. One
Bus Write is required to issue the command. Once
the command is issued, the device returns to its
previous mode, subsequent Bus Read operations
continue to output the data from the same area, as
before.
Once set, these Status Register bits remain set.
They do not automatically return to ‘0’, for exam-
ple, when a new program or erase command is is-
sued. If an error has occurred, it is essential that
any error bits in the Status Register are cleared, by
issuing the Clear Status Register command, be-
fore attempting a new program or erase com-
mand.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command is used to pause
the Program/Erase Controller during a program or
Sector/Block Erase operation. One Bus Write cy-
cle is required to issue the command.
Once the command has been issued, it is neces-
sary to poll the Program/Erase Controller Status
bit until the Program/Erase Controller has paused.
No other commands are accepted until the Pro-
gram/Erase Controller has paused. After the Pro-
gram/Erase Controller has paused, the device
continues to output the contents of the Status Reg-
ister until another command is issued.
During the polling period, between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing, it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit indicates that the Program/
Erase Controller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to determine if the operation has
completed or is suspended.
During Program/Erase Suspend, the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume com-
mands will be accepted by the Command Inter-
face. Additionally, if the suspended operation was
Sector Erase or Block Erase then the program
command will also be accepted. However, it
should be noted that only the Sectors/Blocks not
being erased may be read or programmed correct-
ly.
See Figure 25., and Figure 28., for suggested
flowcharts on using the Program/Erase Suspend
command. Typical times and delay durations are
given in Table 18..
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the command.
Once the command is issued, subsequent Bus
Read operations read the contents of the Status
Register.
21/52
M50FLW040A, M50FLW040B
Table 13. Commands
Note: 1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read Electronic
Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles are WRITE.
BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC mode), and
A21, A20 and A19 are set according to the rules shown in Table 5. (for LPC mode)
2. After a Read Memory Array command, read the memory as normal until another command is issued.
3. After a Read Status Register command, read the Status Register as normal until another command is issued.
4. After the erase and program commands read the Status Register until the command completes and another command is issued.
5. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.
6. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during Erase
Suspend) and Program/Erase Resume commands can be issued.
7. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status Register until
the Program/Erase Controller completes and the memory returns to Read Mode.
8. Do not use Invalid or Reserved commands.
9. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t Care. PD is
two or four Bytes depending on Msize code.
10. “1+” indicates that there is one write cycle, followed by any number of read cycles.
11. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation
is all that is needed.
12. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
Command
Cycle
Bus Operations(1)
1st 2nd 3rd 4th 5th
Addr Data Addr Data Addr Data Addr Data Addr Data
Read Memory
Array(2,10,11) 1+ X FFh Read
Addr
Read
Data
(Read
Addr2)
(Read
Data2)
(Read
Addr3)
(Read
Data3)
(Read
Addr4)
(Read
Data4)
Read Status
Register(3,10) 1+ X 70h X Status
Reg (X) (Status
Reg) (X) (Status
Reg) (X) (Status
Reg)
Read Electronic
Signature(10) 1+ X 90h or
98h
Sig
Addr
Signat
ure
(Sig
Addr)
(Signat
ure)
(Sig
Addr)
(Signat
ure)
(Sig
Addr)
(Signat
ure)
Program / Multiple
Byte program
(FWH)(4,9,11) 2X
40h or
10h
Prog
Addr
Prog
Data
Quadruple Byte
Program
(A/A Mux)(4,12) 5 X 30h A1 Prog
Data1 A2 Prog
Data2 A3 Prog
Data3 A4 Prog
Data4
Chip Erase(4) 2 X 80h X 10h
Block Erase(4) 2 X 20h BA D0h
Sector Erase(4) 2 X 32h SA D0h
Clear Status
Register(5) 1 X 50h
Program/Erase
suspend(6) 1X B0h
Program/Erase
resume(7) 1X D0h
Invalid reserved(8)
1 X 00h
1 X 01h
1 X 60h
1X 2Fh
1X C0h
M50FLW040A, M50FLW040B
22/52
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
The bits in the Status Register convey specific in-
formation about the progress of the operation.
To read the Status Register, the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any ad-
dress.
The text descriptions, below, should be read in
conjunction with Table 14., where the meanings of
the Status Register bits are summarized.
Program/Erase Controller Status (Bit SR7).
This bit indicates whether the Program/Erase Con-
troller is active or inactive. When the Program/
Erase Controller Status bit is ‘0’, the Program/
Erase Controller is active; when the bit is ‘1’, the
Program/Erase Controller is inactive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued, until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses,
the bit is ‘1’.
The end of a Program and Erase operation can be
found by polling the Program/Erase Controller
Status bit can be polled. The other bits in the Sta-
tus Register should not be tested until the Pro-
gram/Erase Controller has completed the
operation (and the Program/Erase Controller Sta-
tus bit is ‘1’).
After the Program/Erase Controller has completed
its operation, the Erase Status, Program Status,
VPP Status and Block Protection Status bits should
be tested for errors.
Erase Suspend Status (Bit SR6). This bit indi-
cates that an Erase operation has been suspend-
ed, and that it is waiting to be resumed. The Erase
Suspend Status should only be considered valid
when the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive). After a Pro-
gram/Erase Suspend command is issued, the
memory may still complete the operation rather
than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’, the Pro-
gram/Erase Controller is active or has completed
its operation. When the bit is ‘1’, a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued, the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit SR5). This bit indicates if a
problem has occurred during the erasing of a Sec-
tor or Block. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’, the memory has
successfully verified that the Sector/Block has
been erased correctly. When the Erase Status bit
is ‘1’, the Program/Erase Controller has applied
the maximum number of pulses to the Sector/
Block and still failed to verify that the Sector/Block
has been erased correctly.
Once the Erase Status bit is set to ‘1’, it can only
be reset to ‘0’ by a Clear Status Register com-
mand, or by a hardware reset. If it is set to ‘1’, it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to have failed, too.
Program Status (Bit SR4). This bit indicates if a
problem has occurred during the programming of
a byte. The Program Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Program Status bit is ‘0’, the memory
has successfully verified that the byte has been
programmed correctly. When the Program Status
bit is ‘1’, the Program/Erase Controller has applied
the maximum number of pulses to the byte and still
failed to verify that the byte has been programmed
correctly.
Once the Program Status bit is set to ‘1’, it can only
be reset to ‘0’ by a Clear Status Register com-
mand, or by a hardware reset. If it is set to ‘1’, it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to have failed, too.
VPP Status (Bit SR3). This bit indicates whether
an invalid voltage was detected on the VPP pin at
the beginning of a Program or Erase operation.
The VPP pin is only sampled at the beginning of
the operation. Indeterminate results can occur if
VPP becomes invalid during a Program or Erase
operation.
Once the VPP Status bit set to ‘1’, it can only be re-
set to ‘0’ by a Clear Status Register command, or
by a hardware reset. If it is set to ‘1’, it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
have failed, too.
Program Suspend Status (Bit SR2). This bit in-
dicates that a Program operation has been sus-
pended, and that it is waiting to be resumed. The
Program Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is ‘1’ (Program/Erase Controller inactive).
After a Program/Erase Suspend command is is-
sued, the memory may still complete the operation
instead of entering the Suspend mode.
23/52
M50FLW040A, M50FLW040B
When the Program Suspend Status bit is ‘0’, the
Program/Erase Controller is active, or has com-
pleted its operation. When the bit is ‘1’, a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued, the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit SR1). The Block
Protection Status bit can be used to identify if the
Program or Erase operation has tried to modify the
contents of a protected block. When the Block Pro-
tection Status bit is to ‘0’, no Program or Erase op-
erations have been attempted to protected blocks
since the last Clear Status Register command or
hardware reset. When the Block Protection Status
bit is ‘1’, a Program or Erase operation has been
attempted on a protected block.
Once it is set to ‘1’, the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or by a hardware reset. If it is set to ‘1’,
it should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to have failed, too.
Using the A/A Mux Interface, the Block Protection
Status bit is always ‘0’.
Reserved (Bit SR0). Bit 0 of the Status Register
is reserved. Its value should be masked.
Table 14. Status Register Bits
Note: 1. For Program operations during Erase Suspend Bit SR6 is ‘1’, otherwise Bit SR6 is ‘0’.
Operation SR7 SR6 SR5 SR4 SR3 SR2 SR1
Program active ‘0’X(1) ‘0’‘0’‘0’‘0’‘0’
Program suspended ‘1X(1) ‘0’‘0’‘0’‘1’‘0’
Program completed successfully ‘1’X(1) ‘0’‘0’‘0’‘0’‘0’
Program failure due to VPP Error ‘1’X(1) ‘0’‘1’‘1’‘0’‘0’
Program failure due to Block Protection (FWH/LPC Interface
only) ‘1’X(1) ‘0’‘1’‘0’‘0’‘1’
Program failure due to cell failure ‘1’X(1) ‘0’‘1’‘0’‘0’‘0’
Erase active ‘0’‘0’‘0’‘0’‘0’‘0’‘0’
Erase suspended ‘1’‘1’‘0’‘0’‘0’‘0’‘0’
Erase completed successfully ‘1’‘0’‘0’‘0’‘0’‘0’‘0’
Erase failure due to VPP Error ‘1’‘0’‘1’‘0’‘1’‘0’‘0’
Erase failure due to Block Protection (FWH/LPC Interface
only) ‘1’‘0’‘1’‘0’‘0’‘0’‘1’
Erase failure due to failed cell(s) in block ‘1’‘0’‘1’‘0’‘0’‘0’‘0’
M50FLW040A, M50FLW040B
24/52
FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION
REGISTERS
When the Firmware Hub Interface/Low Pin Count
is selected, several additional registers can be ac-
cessed. These registers control the protection sta-
tus of the Blocks, read the General Purpose Input
pins and identify the memory using the manufac-
turer code. See Table 15. for the memory map of
the Configuration Registers. The Configuration
registers are accessed directly without using any
specific command code. A single Bus Write or Bus
Read Operation, with the appropriate address (in-
cluding A22=0), is all that is needed.
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block: the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written. Care
should be taken, though, when writing. Once the
Lock Down Bit is set, ‘1’, further modifications to
the Lock Register cannot be made until it is
cleared again by a reset or power-up.
See Table 16. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Erase Command). When
the Write Lock Bit is set, ‘1’, the block is write pro-
tected – any operations that attempt to change the
data in the block will fail, and the Status Register
will report the error. When the Write Lock Bit is re-
set, ‘0’, the block is not write protected by the Lock
Register, and may be modified, unless it is write
protected by some other means.
If the Top Block Lock signal, TBL, is Low, VIL, then
the Top Block (Block 7) is write protected, and
cannot be modified. Similarly, if the Write Protect
signal, WP, is Low, VIL, then the Main Blocks
(Blocks 0 to 6) are write protected, and cannot be
modified.
After power-up, or reset, the Write Lock Bit is al-
ways set to ‘1’ (write-protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read (in
Read mode). When the Read Lock Bit is set, ‘1’,
the block is read protected – any operation that at-
tempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations are allowed in the Block, and re-
turn the value of the data that had been pro-
grammed in the block.
After power-up, or reset, the Read Lock Bit is al-
ways reset to ‘0’ (not read-protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset, or power-up, is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Table 15. Configuration Register Map
Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address
bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9..
Mnemonic Register Name Memory
Address Default
Value Access
Lock Registers (For details, see APPENDIX A.)
GPI_REG Firmware Hub/Low Pin Count (FWH/LPC) General
Purpose Input Register FBC0100h N/A R
MANU_REG Manufacturer Code Register FBC0000h 20h R
25/52
M50FLW040A, M50FLW040B
Table 16. Lock Register Bit Definitions
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-7] Lock Reg-
ister (T_MINUS07_LK).
Table 17. General Purpose Inputs Register Definition
Note: 1. Applies to the General Purpose Inputs Register (GPI-REG).
Firmware Hub/Low Pin Count (FWH/LPC)
General Purpose Input Register
The FWH/LPC General Purpose Input Register
holds the state of the General Purpose Input pins,
GPI0-GPI4. When this register is read, the state of
these pins is returned. This register is read-only.
Writing to it has no effect.
The signals on the FWH/LPC Interface General
Purpose Input pins should remain constant
throughout the whole Bus Read cycle.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the value 20h, which is the Manufacturer Code for
STMicroelectronics. This register is read-only.
Writing to it has no effect.
Bit Bit Name Value Function (1)
7-3 Reserved
2 Read-Lock
‘1’Bus Read operations in this Block always return 00h.
‘0’Bus read operations in this Block return the Memory Array contents. (Default
value).
1 Lock-Down
‘1’Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘0’Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
0 Write-Lock
‘1’Program and Erase operations in this Block will set an error in the Status Register.
The memory contents will not be changed. (Default value).
‘0’Program and Erase operations in this Block are executed and will modify the Block
contents.
Bit Bit Name Value Function (1)
7-5 Reserved
4GPI4 ‘1’Input Pin GPI4 is at VIH
‘0’Input Pin GPI4 is at VIL
3GPI3 ‘1’Input Pin GPI3 is at VIH
‘0’Input Pin GPI3 is at VIL
2GPI2 ‘1’Input Pin GPI2 is at VIH
‘0’Input Pin GPI2 is at VIL
1GPI1 ‘1’Input Pin GPI1 is at VIH
‘0’Input Pin GPI1 is at VIL
0GPI0 ‘1’Input Pin GPI0 is at VIH
‘0’Input Pin GPI0 is at VIL
M50FLW040A, M50FLW040B
26/52
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table
18..
Table 18. Program and Erase Times
Note: 1. TA = 25°C, VCC = 3.3V
2. Sampled only, not 100% tested.
3. Time to program two Bytes.
4. Time to program four Bytes.
5. Time obtained executing the Quadruple Byte Program command.
Parameter Interface Test Condition Min Typ(1) Max Unit
Byte Program 10 200 µs
Double Byte Program FWH VPP = 12V ± 5% 10(3) 200 µs
Quadruple Byte Program A/A Multiplexed
FWH VPP = 12V ± 5% 10(4) 200 µs
Block Program VPP = 12V ± 5% 0.1(5) 5s
VPP = VCC 0.4 5
Sector Erase (4 KBytes)(2) VPP = 12V ± 5% 0.4 4 s
VPP = VCC 0.5 5
Block Erase (64 KBytes) VPP = 12V ± 5% 0.75 8 s
VPP = VCC 110
Chip Erase A/A Multiplexed VPP = 12V ± 5% 5s
Program/Erase Suspend to Program pause(2) 5µs
Program/Erase Suspend to Block Erase/
Sector Erase pause(2) 30 µs
27/52
M50FLW040A, M50FLW040B
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 19. Absolute Maximum Ratings
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for
less than 20ns during transitions.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VIO Input or Output range 2–0.50 VCC + 0.6 V
VCC Supply Voltage –0.50 4 V
VPP Program Voltage –0.6 13 V
VESD Electrostatic Discharge Voltage (Human Body model) 3–2000 2000 V
M50FLW040A, M50FLW040B
28/52
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 20., Table 21.
and Table 22.. Designers should check that the
operating conditions in their circuit match the oper-
ating conditions when relying on the quoted pa-
rameters.
Table 20. Operating Conditions
Table 21. FWH/LPC Interface AC Measurement Conditions
Table 22. A/A Mux Interface AC Measurement Conditions
Figure 11. FWH/LPC Interface AC Measurement I/O Waveforms
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
TA
Ambient Operating Temperature (Device Grade 5) –20 85 °C
Ambient Operating Temperature (Device Grade 1) 0 70 °C
Parameter Value Unit
Load Capacitance (CL)10 pF
Input Rise and Fall Times ≤ 1.4 ns
Input Pulse Voltages 0.2 VCC and 0.6 VCC V
Input and Output Timing Ref. Voltages 0.4 VCC V
Parameter Value Unit
Load Capacitance (CL)30 pF
Input Rise and Fall Times ≤ 10 ns
Input Pulse Voltages 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 V
AI03404
0.6 VCC
0.2 VCC
0.4 VCC
IO > ILO
IO < ILO IO < ILO
Input and Output AC Testing Waveform
Output AC Tri-state Testing Waveform
29/52
M50FLW040A, M50FLW040B
Figure 12. A/A Mux Interface AC Measurement I/O Waveform
Figure 13. AC Measurement Load Circuit
Table 23. Impedance
Note: 1. Sampled only, not 100% tested.
2. See PCI Specification.
3. TA = 25°C, f = 1MHz.
Symbol Parameter Test Condition Min Max Unit
CIN(1) Input Capacitance VIN = 0V 13 pF
CCLK(1) Clock Capacitance VIN = 0V 312pF
LPIN(2) Recommended Pin
Inductance 20 nH
AI01417
3V
0V
1.5V
AI08430
VDD
CL
CL includes JIG capacitance
16.7kΩ
DEVICE
UNDER
TEST
0.1µF
VDD
0.1µF
VPP
16.7kΩ
M50FLW040A, M50FLW040B
30/52
Table 24. DC Characteristics
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
3. ID3 pin is RFU in LPC mode.
Symbol Parameter Interface Test Condition Min Max Unit
VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V
A/A Mux 0.7 VCC VCC + 0.3 V
VIL Input Low Voltage FWH/LPC –0.5 0.3 VCC V
A/A Mux -0.5 0.8 V
VIH(INIT)INIT Input High Voltage FWH/LPC 1.1 VCC + 0.5 V
VIL(INIT)INIT Input Low Voltage FWH/LPC –0.5 0.2 VCC V
ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA
ILI2 IC, IDx Input Leakage
Current IC, ID0, ID1, ID2, ID3(3) = VCC 200 µA
RIL IC, IDx Input Pull Low
Resistor 20 100 kΩ
VOH Output High Voltage FWH/LPC IOH = –500µA0.9 VCC V
A/A Mux IOH = –100µAVCC – 0.4 V
VOL Output Low Voltage FWH/LPC IOL = 1.5mA 0.1 VCC V
A/A Mux IOL = 1.8mA 0.45 V
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA
VPP1 VPP Voltage 33.6V
VPPH VPP Voltage
(Fast Erase) 11.4 12.6 V
VLKO(1) VCC Lockout Voltage 1.8 2.3 V
ICC1 Supply Current (Standby) FWH/LPC
FWH4/LFRAME = 0.9VCC
VPP = VCC
All other inputs 0.9VCC to 0.1VCC
VCC = 3.6V, f(CLK) = 33MHz
100 µA
ICC2 Supply Current (Standby) FWH/LPC
FWH4/LFRAME = 0.1 VCC, VPP =
VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
10 mA
ICC3
Supply Current
(Any internal operation
active)
FWH/LPC
VCC = VCC max, VPP = VCC
f(CLK) = 33MHz
IOUT = 0mA
60 mA
ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA
ICC5(1) Supply Current
(Program/Erase) A/A Mux Program/Erase Controller Active 20 mA
IPP VPP Supply Current
(Read/Standby) VPP > VCC 400 µA
IPP1(1) VPP Supply Current
(Program/Erase active)
VPP = VCC 40 mA
VPP = 12V ± 5% 15 mA
31/52
M50FLW040A, M50FLW040B
Figure 14. FWH/LPC Interface Clock Waveform
Table 25. FWH/LPC Interface Clock Characteristics
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.
Symbol Parameter Test Condition Value Unit
tCYC CLK Cycle Time(1) Min 30 ns
tHIGH CLK High Time Min 11 ns
tLOW CLK Low Time Min 11 ns
CLK Slew Rate peak to peak Min 1 V/ns
Max 4 V/ns
AI03403
tHIGH tLOW
0.6 VCC
tCYC
0.5 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.4 VCC, p-to-p
(minimum)
M50FLW040A, M50FLW040B
32/52
Figure 15. FWH/LPC Interface AC Signal Timing Waveforms
Table 26. FWH/LPC Interface AC Signal Timing Characteristics
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-
ification.
2. Applies to all inputs except CLK and FWH4.
Symbol PCI
Symbol Parameter Value Unit
tCHQV tval CLK to Data Out Min 2 ns
Max 11 ns
tCHQX(1) ton CLK to Active
(Float to Active Delay) Min 2 ns
tCHQZ toff CLK to Inactive
(Active to Float Delay) Max 28 ns
tAVCH
tDVCH tsu Input Set-up Time(2) Min 7 ns
tCHAX
tCHDX thInput Hold Time(2) Min 0 ns
tFLCH Input Set-up time on FWH4 Min 10 ns
tCHFH Input Hold time on FWH4 Min 5 ns
CLK
FWH0-FWH3/
LAD0-LAD3
VALID
tCHQV tCHQZ
tCHQX
tCHDX
tDVCH
VALID
OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA
AI09700
tCHFH
tFLCH
FWH4
START CYCLE
33/52
M50FLW040A, M50FLW040B
Figure 16. Reset AC Waveforms
Table 27. Reset AC Characteristics
Note: 1. See Chapter 4 of the PCI Specification.
Symbol Parameter Test Condition Value Unit
tPLPH RP or INIT Reset Pulse Width Min 100 ns
tPLRH RP or INIT Low to Reset Program/Erase Inactive Max 100 ns
Program/Erase Active Max 30 µs
RP or INIT Slew Rate(1) Rising edge only Min 50 mV/ns
tPHFL RP or INIT High to FWH4/
LFRAME Low FWH/LPC Interface only Min 30 µs
tPHWL
tPHGL
RP High to Write Enable or Output
Enable Low A/A Mux Interface only Min 50 µs
RP, INT
ai08422
W, G, FWH4/LFRAME
RB
tPLRH
tPLPH tPHWL, tPHGL, tPHFL
M50FLW040A, M50FLW040B
34/52
Figure 17. A/A Mux Interface Read AC Waveforms
Table 28. A/A Mux Interface Read AC Characteristics
Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.
Symbol Parameter Test Condition Value Unit
tAVAV Read Cycle Time Min 250 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC high Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tCHQV(1) RC High to Output Valid Max 150 ns
tGLQV(1) Output Enable Low to Output Valid Max 50 ns
tPHAV RP High to Row Address Valid Min 1 µs
tGLQX Output Enable Low to Output Transition Min 0 ns
tGHQZ Output Enable High to Output Hi-Z Max 50 ns
tGHQX Output Hold from Output Enable High Min 0 ns
AI03406
tAVAV
tCLAX tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID NEXT ADDR VALID
tAVCL tAVCH
35/52
M50FLW040A, M50FLW040B
Figure 18. A/A Mux Interface Write AC Waveforms
Table 29. A/A Mux Interface Write AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
Symbol Parameter Test Condition Value Unit
tWLWH Write Enable Low to Write Enable High Min 100 ns
tDVWH Data Valid to Write Enable High Min 50 ns
tWHDX Write Enable High to Data Transition Min 5 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC High Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tWHWL Write Enable High to Write Enable Low Min 100 ns
tCHWH RC High to Write Enable High Min 50 ns
tVPHWH(1) VPP High to Write Enable High Min 100 ns
tWHGL Write Enable High to Output Enable Low Min 30 ns
tWHRL Write Enable High to RB Low Min 0 ns
tQVVPL(1,2) Output Valid, RB High to VPP Low Min 0 ns
AI04185
tCLAX
tCHAX
tWHDXtDVWH
VALID SRD
A0-A10
G
DQ0-DQ7
RC
tCHWH
tWHRL
C1
W
R1
tAVCL
tAVCH
R2 C2
tWLWH
tWHWL
RB
VPP
tVPHWH tWHGL
tQVVPL
DIN1 DIN2
Write erase or
program setup
Write erase confirm or
valid address and data
Automated erase
or program delay
Read Status
Register Data
Ready to write
another command
M50FLW040A, M50FLW040B
36/52
PACKAGE MECHANICAL
Figure 19. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
Note: Drawing is not to scale.
PLCC-A
D
E3 E1 E
1 N
D1
D3
CP
B
E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
E2
D2 D2
37/52
M50FLW040A, M50FLW040B
Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 3.18 3.56 0.125 0.140
A1 1.53 2.41 0.060 0.095
A2 0.38 –0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
CP 0.10 0.004
D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 ––0.300 ––
E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.93 0.238 0.273
E3 10.16 ––0.400 ––
e1.27 ––0.050 ––
F 0.00 0.13 0.000 0.005
R0.89 ––0.035 ––
N32 32
M50FLW040A, M50FLW040B
38/52
Figure 20. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
Note: Drawing is not to scale.
Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α05 05
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 13.800 14.200 0.5433 0.5591
D1 12.300 12.500 0.4843 0.4921
e0.500 ––0.0197 ––
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
N32 32
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
39/52
M50FLW040A, M50FLW040B
Figure 21. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.200 0
A1 0.050 0.150 0 0
A2 0.950 1.050 0 0
B 0.170 0.270 0 0
C 0.100 0.210 0 0
CP 0.100 0
D 19.800 20.200 1 1
D1 18.300 18.500 1 1
e0.500 ––0––
E 9.900 10.100 0 0
L 0.500 0.700 0 0
α05 05
N40 40
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
M50FLW040A, M50FLW040B
40/52
PART NUMBERING
Table 33. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Example:M50FLW040 A K 5 T P
Device Type
M50 = Flash Memory for PC BIOS
Architecture
FL = Firmware Hub/Low Pin Count Interface
Operating Voltage
W = VCC = 3.0 to 3.6V
Device Function
040 = 4 Mbit (x8), Uniform Blocks and Sectors
Array Matrix
A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors
B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors
Package
K = PLCC32
NB = TSOP32: 8 x 14mm
N = TSOP40: 10 x 20 mm
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
41/52
M50FLW040A, M50FLW040B
APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE
Table 34. M50FLW040A Block and Sector
Addresses
Block
Size
(KByte)
Address
Range
Block
No and
Type
Sector
Size
(KByte)
Sector
No Register
Address
64
7F000h-
7FFFFh
7
(Top)
447
FBF0002
7E000h-
7EFFFh 446
7D000h-
7DFFFh 445
7C000h-
7CFFFh 444
7B000h-
7BFFFh 443
7A000h-
7AFFFh 442
79000h-
79FFFh 441
78000h-
78FFFh 440
77000h-
77FFFh 439
76000h-
76FFFh 438
75000h-
75FFFh 437
74000h-
74FFFh 436
73000h-
73FFFh 435
72000h-
72FFFh 434
71000h-
71FFFh 433
70000h-
70FFFh 432
64
6F000h-
6FFFFh
6
(Main)
431
FBE0002
6E000h-
6EFFFh 430
6D000h-
6DFFFh 429
6C000h-
6CFFFh 428
6B000h-
6BFFFh 427
6A000h-
6AFFFh 426
69000h-
69FFFh 425
68000h-
68FFFh 424
67000h-
67FFFh 423
66000h-
66FFFh 422
65000h-
65FFFh 421
64000h-
64FFFh 420
63000h-
63FFFh 419
62000h-
62FFFh 418
61000h-
61FFFh 417
60000h-
60FFFh 416
64 50000h-
5FFFFh
5
(Main) FBD0002
64 40000h-
4FFFFh
4
(Main) FBC0002
64 30000h-
3FFFFh
3
(Main) FBB0002
64 20000h-
2FFFFh
2
(Main) FBA0002
64 10000h-
1FFFFh
1
(Main) FB90002
Block
Size
(KByte)
Address
Range
Block
No and
Type
Sector
Size
(KByte)
Sector
No Register
Address
M50FLW040A, M50FLW040B
42/52
Note: In LPC mode, a most significant nibble, F, must be added to
the memory address. For all registers, A22=0, and the re-
maining address bits should be set according to the rules
shown in the ADDR field of Table 6. to Table 9..
Table 35. M50FLW040B Block and Sector
Addresses
64
0F000h-
0FFFFh
0
(Main)
415
FB80002
0E000h-
0EFFFh 414
0D000h-
0DFFFh 413
0C000h-
0CFFFh 412
0B000h-
0BFFFh 411
0A000h-
0AFFFh 410
09000h-
09FFFh 49
08000h-
08FFFh 48
07000h-
07FFFh 47
06000h-
06FFFh 46
05000h-
05FFFh 45
04000h-
04FFFh 44
03000h-
03FFFh 43
02000h-
02FFFh 42
01000h-
01FFFh 41
00000h-
00FFFh 40
Block
Size
(KByte)
Address
Range
Block
No and
Type
Sector
Size
(KByte)
Sector
No Register
Address Block
Size
(KByte)
Address
Range
Block
No and
Type
Sector
Size
(KByte)
Sector
No Register
Address
64
7F000h-
7FFFFh
7
(Top)
447
FBF0002
7E000h-
7EFFFh 446
7D000h-
7DFFFh 445
7C000h-
7CFFFh 444
7B000h-
7BFFFh 443
7A000h-
7AFFFh 442
79000h-
79FFFh 441
78000h-
78FFFh 440
77000h-
77FFFh 439
76000h-
76FFFh 438
75000h-
75FFFh 437
74000h-
74FFFh 436
73000h-
73FFFh 435
72000h-
72FFFh 434
71000h-
71FFFh 433
70000h-
70FFFh 432
64 60000h-
6FFFFh 6
(Main) FBE0002
64 50000h-
5FFFFh 5
(Main) FBD0002
64 40000h-
4FFFFh 4
(Main) FBC0002
64 30000h-
3FFFFh 3
(Main) FBB0002
64 20000h-
2FFFFh 2
(Main) FBA0002
43/52
M50FLW040A, M50FLW040B
Note: In LPC mode, a most significant nibble, F, must be added to
the memory address. For all registers, A22=0, and the re-
maining address bits should be set according to the rules
shown in the ADDR field of Table 6. to Table 9..
64
1F000h-
1FFFFh
1
(Main)
431
FB90002
1E000h-
1EFFFh 430
1D000h-
1DFFFh 429
1C000h-
1CFFFh 428
1B000h-
1BFFFh 427
1A000h-
1AFFFh 426
19000h-
19FFFh 425
18000h-
18FFFh 424
17000h-
17FFFh 423
16000h-
16FFFh 422
15000h-
15FFFh 421
14000h-
14FFFh 420
13000h-
13FFFh 419
12000h-
12FFFh 418
11000h-
11FFFh 417
10000h-
10FFFh 416
Block
Size
(KByte)
Address
Range
Block
No and
Type
Sector
Size
(KByte)
Sector
No Register
Address
64
0F000h-
0FFFFh
0
(Main)
415
FB80002
0E000h-
0EFFFh 414
0D000h-
0DFFFh 413
0C000h-
0CFFFh 412
0B000h-
0BFFFh 411
0A000h-
0AFFFh 410
09000h-
09FFFh 49
08000h-
08FFFh 48
07000h-
07FFFh 47
06000h-
06FFFh 46
05000h-
05FFFh 45
04000h-
04FFFh 44
03000h-
03FFFh 43
02000h-
02FFFh 42
01000h-
01FFFh 41
00000h-
00FFFh 40
Block
Size
(KByte)
Address
Range
Block
No and
Type
Sector
Size
(KByte)
Sector
No Register
Address
M50FLW040A, M50FLW040B
44/52
APPENDIX B. FLOWCHARTS AND PSEUDO CODES
Figure 22. Program Flowchart and Pseudo Code
Note: 1. A Status check of SR1 (Protected Block), SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation
by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 40h or 10h
AI08425B
Start
Write Address
and Data
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Program command:
– Write 40h or 10h
– Write Address and Data
(memory enters read status state after
the Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1,
– Enter the "VPP invalid" error handler
If SR4 = 1,
– Enter the "Program error" error handler
YES
End
YES
NO
SR1 = 0 Program to Protected
Block Error (1, 2)
If SR1 = 1,
– Enter the "Program to protected
block" error handler
Suspend
Suspend
Loop
NO
YES
FWH/LPC
Interface
Only
45/52
M50FLW040A, M50FLW040B
Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only)
Note: 1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation by following the correct
command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. A0 and/or A1 are treated as Don’t Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte Program).
For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even address, and the second at
the odd address.
For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the address that has A1-A0 at 00,
the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address that
has A1-A0 at 11.
AI08423B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Double/Quadruple Byte Program command:
– write 40h or 10h
– write Start Address and 2/4 Data Bytes
(3)
(memory enters read status state after
the Double/Quadruple Byte Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1, VPP invalid error:
– error handler
If SR4 = 1, Program error:
– error handler
Suspend
Suspend
Loop
NO
YES
Write 40h or 10h
Start
Write Start Address
and 2/4 Data Bytes
(3)
YES
End
YES
NO
SR1 = 0 Program to Protected
Block Error (1, 2)
If SR1 = 1,
Program to protected block error:
– error handler
M50FLW040A, M50FLW040B
46/52
Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct
command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.
AI08437B
Write Address 4
& Data 4
(3)
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1
(3)
– write Address 2 & Data 2
(3)
– write Address 3 & Data 3
(3)
– write Address 4 & Data 4
(3)
(memory enters read status state after
the Quadruple Byte Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1, VPP invalid error:
– error handler
If SR4 = 1, Program error:
– error handler
End
YES
Suspend
Suspend
Loop
NO
YES
Write 30h
Start
Write Address 1
& Data 1
(3)
Write Address 2
& Data 2
(3)
Write Address 3
& Data 3
(3)
47/52
M50FLW040A, M50FLW040B
Figure 25. Program Suspend and Resume Flowchart and Pseudo Code
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
Write 70h
AI08426B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR2 = 1
Program Continues
Write a read
Command
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while SR7 = 0
If SR2 = 0 Program completed
Write D0h
Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
Read Data
M50FLW040A, M50FLW040B
48/52
Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 80h
AI08428B
Start
Write 10h
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4, SR5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Chip Erase command:
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
do:
– read Status Register
while SR7 = 0
If SR3 = 1, VPP invalid error:
– error handler
If SR4, SR5 = 1, Command sequence error:
– error handler
YES
NO
SR5 = 0 Erase Error (1) If SR5 = 1, Erase error:
– error handler
End
YES
49/52
M50FLW040A, M50FLW040B
Figure 27. Sector/Block Erase Flowchart and Pseudo Code
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
Write 20h/32h
AI08424B
Start
Write Block
Address and D0h
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4, SR5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Block Erase command:
– Write 20h/32h
– Write block Address and D0h
(memory enters read Status Register after
the Block Erase command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1,
– Enter the "VPP invalid" error handler
If SR4, SR5 = 1,
– Enter the "Command sequence"error handler
YES
NO
SR5 = 0 Erase Error (1)
YES
NO
Suspend
Suspend
Loop
If SR5 = 1,
– Enter the "Erase Error" error handler
End
YES
NO
SR1 = 0 Erase to Protected
Block Error (1)
If SR1 = 1,
– Enter the "Erase to protected block"
error handler
YES
FWH/LPC
Interface
Only
M50FLW040A, M50FLW040B
50/52
Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code
Write 70h
AI08429B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR6 = 1
Erase Continues
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while SR7 = 0
If SR6 = 0, Erase completed
Write D0h
Read data from
another block/sector
or
Program
Start
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
51/52
M50FLW040A, M50FLW040B
REVISION HISTORY
Table 36. Document Revision History
Date Version Revision Details
23-Jun-2003 1.0 First Issue
04-Jul-2003 2.0 VIH(INIT) min parameter modified in Table 24., DC Characteristics.
Document status promoted from Target Specification to Product Preview
28-Jul-2003 2.1 Document renamed to M50FLW040A, M50FLW040B
08-Oct-2003 2.2 Block types removed from the Block and Sector Address tables
07-Nov-2003 2.3 Document promoted to Preliminary Data
18-Feb-2004 3.0 Wording in the textual discriptions revised throughout the document.
18-May-2004 4.0 TSOP32 package added. Updates to Tables 8, 9, 12, 13, 14, 15, 19, 26, 34 and 35;
and to Figures 15, and 22 to 28
18-Aug-2004 5.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected
M50FLW040A, M50FLW040B
52/52
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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