Low Noise Micro PMU
,
3 A Buck Regulator with 3 A LDO
Data Sheet
ADP5003
Rev. A Document Feedback
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FEATURES
Low noise, dc power supply system
High efficiency buck for first stage conversion
High PSRR, low noise LDO regulator to remove switching
ripple
Adaptive LDO regulator headroom control option for
optimal efficiency and PSRR across full load range
3 A, low noise, buck regulator
Wide input voltage range: 4.2 V to 15 V
Programmable output voltage range: 0.6 V to 5.0 V
0.3 MHz to 2.5 MHz internal oscillator
0.3 MHz to 2.5 MHz SYNC frequency range
3 A, low noise, NFET LDO regulator (active filter)
Wide input voltage range: 0.65 V to 5 V
Programmable output voltage range: 0.6 V to 3.3 V
Differential point of load remote sensing
3 µV rms output noise (independent of output voltage)
PSRR > 50 dB (to 100 kHz) with 400 mV headroom at 3 A
Ultrafast transient response
Power-good output
Precision enable inputs for both the buck regulator and LDO
−40°C to +125°C operating junction temperature range
32-lead, 5 mm × 5 mm, LFCSP
APPLICATIONS
Low noise power for high speed analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) designs
Powering RF transceivers and clocking ICs
FUNCTIONAL BLOCK DIAGRAM
RT R
RT
R
TOP1
R
BOT1
VOUT1
SW1 L1
SW1
SW1
PGND1
PGND1
PGND1
VREG
PVINSYS
VPVINSYS:
4.2V TO 15V
AGND1 AGND2
PVIN2
PVIN2
PVIN2
PVOUT2
PVOUT2
PVOUT2
C
PVOUT2
C
VREG_LDO
C
VREG
C
VBUF
C
PVINSYS
C
PVOUT1
C
PVIN2
C
PVIN1
VFB2P
EN1
VBUF
COMP1
RC
CC
REFOUT
EN2 VFB2N
VSET2
LOW NOISE
LDO ACTIVE
FILTER
3A LOAD
SYNC
VPVOUT2:
0.6V TO 3. 3V
VPVOUT1
:
0.6V TO 5. 0V
VSET1
PVIN1
PVIN1
BUCK
REGULATOR
3A
VPVIN1:
4.2V TO 15V
C
REFOUT
SYSTEM PWRGD
VREG_LDO
15021-001
Figure 1.
GENERAL DESCRIPTION
The ADP5003 integrates a high voltage buck regulator and an
ultralow noise low dropout (LDO) regulator in a small, 5 mm ×
5 mm, 32-lead LFCSP package to provide highly efficient and
quiet regulated supplies.
The buck regulator is optimized to operate at high output
currents up to 3 A. The LDO is capable of a maximum output
current of 3 A and operates efficiently with low headroom
voltage while maintaining high power supply rejection.
The ADP5003 can operate in one of two modes. Adaptive mode
allows the LDO to operate with an optimized headroom by
adjusting the buck output voltage internally in response to the
LDO load current. Alternatively, the ADP5003 can operate in
independent mode, where both regulators operate separately
from each other, and where the output voltages are
programmed using resistor dividers.
The LDO regulator output can be accurately controlled at the
point of load (POL) using remote sensing that compensates for the
printed circuit board (PCB) trace impedance while delivering
high output currents.
Each regulator is activated via a dedicated precision enable
input. The buck switching frequency can be synchronized to
an external signal, or programmed with an external resistor.
Safety features in the ADP5003 include thermal shutdown (TSD),
input undervoltage lockout (UVLO) and independent current
limits for each regulator. The ADP5003 is rated for a −40°C to
+125°C operating junction temperature range.
ADP5003 Data Sheet
Rev. A | Page 2 of 31
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Buck Regulator Specifications .................................................... 5
LDO Specifications ...................................................................... 6
Adaptive Headroom Controller Specifications ........................ 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 15
Power Management Unit ........................................................... 15
Buck Regulator ............................................................................ 15
LDO Regulator ............................................................................ 17
Power-Good ................................................................................ 18
Output Voltage of the Buck Regulator ..................................... 18
Output Voltage of the LDO Regulator ..................................... 18
Voltage Conversion Limitations ............................................... 18
Component Selection................................................................. 19
Compensation Components Design ........................................ 21
Junction Temperature ................................................................ 21
Buck Regulator Design Example .................................................. 22
Setting the Switching Frequency for the Buck Regulator ....... 22
Setting the Output Voltage for the Buck Regulator ................. 22
Selecting the Inductor for the Buck Regulator ......................... 22
Selecting the Output Capacitor for the Buck Regulator.......... 22
Designing the Compensation Network for the Buck Regulator
....................................................................................................... 23
Selecting the Input Capacitor for the Buck Regulator ............. 23
Adaptive Headroom Control Design Example .......................... 24
Setting the Switching Frequency for the Buck Regulator Using
Adaptive Headroom Control .................................................... 24
Setting the Output Voltage for the LDO Regulator Using
Adaptive Headroom Control .................................................... 24
Selecting the Inductor for the Buck Regulator Using Adaptive
Headroom Control ..................................................................... 24
Selecting the Output Capacitors for the Buck Regulator Using
Adaptive Headroom Control .................................................... 24
Designing the Compensation Network for the Buck
Regulator Using Adaptive Headroom Control ....................... 25
Selecting the Input Capacitor for the Buck Regulator Using
Adaptive Headroom Control .................................................... 25
Recommended External Components for the Buck Regulator
....................................................................................................... 26
Buck Configurations ...................................................................... 28
Independent ................................................................................ 28
Adaptive Headroom ................................................................... 29
Layout Considerations ................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Data Sheet ADP5003
Rev. A | Page 3 of 31
REVISION HISTORY
3/2019—Rev. 0 to Rev. A
Changes to Applications Section, General Description, and
Figure 1 ............................................................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Table 5 ............................................................................ 7
Changes to Table 7 ............................................................................ 8
Updated Typical Performance Characteristics Section;
Renumbered Sequentially ................................................................ 9
Changes to Adaptive Headroom Control Section, Active Pull
Down Section, and Power-Good Section .................................... 15
Changes to Oscillator Frequency Control Section ..................... 16
Add Figure 38 and Figure 39 ......................................................... 16
Changes to Current-Limit and Short-Circuit Protection
Section and Current Limit Section ............................................... 17
Changes to Output Voltage of the Buck Regulator Section,
Figure 44, Output Voltage of the LDO Regulator Section,
Figure 45, and Voltage Conversion Limitations Section ............ 18
Changes to Input Capacitor Section, Inductor Section, and
Table 9 ............................................................................................... 20
Changes to Compensation Components Design Section,
Figure 46 and Junction Temperature Section .............................. 21
Changes to Table 10, Setting the Switching Frequency for the
Buck Regulator Section, Setting the Output Voltage for the
Buck Regulator Section, Selecting the Inductor for the Buck
Regulator Section, and Selecting the Output Capacitor for the
Buck Regulator Section .................................................................. 22
Deleted Figure 44; Renumbered Sequentially ............................. 22
Changes Figure 47 ........................................................................... 23
Changes to Table 11, Setting the Output Voltage for the LDO
Regulator Using Adaptive Headroom Control Section, and
Selecting the Inductor for the Buck Regulator Using Adaptive
Headroom Control Section ........................................................... 24
Changes Figure 48 ........................................................................... 25
Changes to Recommended External Components for the Buck
Regulator Section and Table 12 Title ............................................ 26
Changes to Figure 49 Caption and Figure 50 .............................. 28
Changes to Adaptive Headroom Section and Figure 52 ............ 29
Changes to Layout Considerations Section and Figure 53 ........ 30
Updated Outline Dimensions ........................................................ 31
11/2017—Revision 0: Initial Version
ADP5003 Data Sheet
Rev. A | Page 4 of 31
SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for
typical specifications, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ
Max Unit
Test Conditions/Comments
INPUT VOLTAGE RANGE VPVIN1, VPVINSYS 4.2 15 V
VPVIN2 0.65 5 V
THERMAL SHUTDOWN
Threshold TSD 155
°C TJ rising
Hysteresis TSD-HYS 15 °C
SYNC INPUT
Input Logic
High VIH 1.1 V
Low VIL 0.4 V
Input Leakage Current VI-LEAKAGE 1 µA
ADAPTIVE MODE INPUT (VSET1)
Input Rising Threshold VADPR 2.5 V
Input Hysteresis
V
ADPH
16
mV
PRECISION ENABLING
High Level Threshold VTH_H 1.125
1.15
1.175
V
Low Level Threshold
V
TH_L
1.025
1.05
1.075
V
Shutdown Mode VTH_S 0.4 V
EN1, EN2 Pull-Down Resistance RENPD 1.5 MΩ
INPUT CURRENT
Both Channels Enabled ISTBY-NOSW 0.5 1 mA No load, not switching
Both Channels Disabled ISHUTDOWN 5 10 µA TJ = −40°C to +125°C
REFOUT CHARACTERISTICS
Output Voltage VREFOUT 2.0 V
Accuracy −0.5 +0.5 %
VREG AND VREG_LDO CHARACTERISTICS
Output Voltage VREG, VREG_LDO 5 V
Accuracy −2 +2 %
Current Limit1 10 mA
POWER-GOOD PIN (PWRGD)
Power Good Threshold PWRGDF 80 85 90 % Applies to VOUT1 and VFB2P to VFB2N
Hysteresis PWRGDFH 2.5 %
Output Voltage Level
V
OL
25
50
mV
PWRGD pin sink current = 1 mA
Deglitch Time tPWRGDD 60 µs
PVINSYS UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage
Rising UVLOPVINSYSRISE 4.2 V
Falling UVLO
PVINSYSFALL
3.9 V
1 Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground.
Data Sheet ADP5003
Rev. A | Page 5 of 31
BUCK REGULATOR SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range1 VPVOUT1 0.6 5.0 V
Buck Regulator Gain ABUCK 2.5 VPVOUT1/VVSET1
Error Amplifier Transconductance gm1 509 600 661 µS
Buck Output Voltage Accuracy2 −1 +1 % VOUT1 load current (ILOAD1) = 10 mA
Regulation
Line (ΔVPVOUT1/VPVOUT1)/ΔVPVIN1 0.004 %/V ILOAD1 = 10 mA
Load (ΔVPVOUT1/VPVOUT1)/ΔILOAD1 0.04 %/A 0 mA ≤ ILOAD1 ≤ 3 A, VPVIN1 = 12 V
Total Output Voltage Accuracy ±1.5 % 4.2 V ≤ VPVIN1 ≤ 15 V, 1 mA ≤ ILOAD1 ≤ 3 A
OPERATING SUPPLY CURRENT IIN 3.8 mA ILOAD1 = 0 mA, LDO disabled, buck
switching
SW1 CHARACTERISTICS
SW1 On Resistance RPFET 130 200 mΩ VPVIN1 = 15 V (PVIN1 to SW1)
RNFET 60 100 mΩ VPVIN1 = 15 V (SW1 to PGND1)
Current Limit Threshold ILIMIT1 3.5 A Negative channel field effect
transistor (NFET) switch valley
current limit
−1 A Negative current limit
Slew Rate SLEWSW1 1.6 V/ns VPVIN1 = 15 V, ILOAD1 = 1 A
Minimum On Time3 tMIN_ON 35 ns
Minimum Off Time tMIN_OFF 100 128 ns
BUCK REGULATOR ACTIVE PULL DOWN RPDWN-B 90 Ω Channel disabled
BUCK REGULATOR SOFT START (SS) tSSBUCK 2 ms
HICCUP TIME tHICCUP 33 ms
VSETx ADJUSTABLE INPUT BIAS CURRENT IVSET1, IVSET2 10 150 nA
OSCILLATOR
Internal Switching Frequency 1 fSW1 2.25 2.5 2.75 MHz RRT ≤ 71.2 kΩ
Internal Switching Frequency 2 fSW2 0.26 0.3 0.34 MHz RRT = 600 kΩ
SYNC
Frequency Range fSYNC 0.3 2.5 MHz
Minimum Pulse Width
Positive 20 ns
Negative 10 ns
1 The switching frequency, minimum on time, and minimum off time may limit the output voltage range.
2 The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3 The minimum on time indicates the minimum high-side turn on time to ensure fixed frequency switching.
ADP5003 Data Sheet
Rev. A | Page 6 of 31
LDO SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, LDO headroom voltage (VHR) = 300 mV, TJ = −40°C to +125°C for
minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range1 VLDO 0.6 3.3 V VVFB2P-VFB2N
LDO Gain ALDO 1.65 VLDO/VVSET2
Output Voltage Accuracy2 −1 +1 % VOUT2 load current (ILOAD2) =
150 mA
Regulation
Line (ΔVLDO/VLDO)/ΔVPVIN2 0.007 %/V (VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V,
ILOAD2 = 100 mA
Load (ΔVLDO/VLDO)/ΔILOAD2 0.08 %/A 10 mA ≤ ILOAD2 ≤ 3 A
Total Output Voltage Accuracy ±1.5 % (VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V,
10 mA ≤ ILOAD2 ≤ 3 A
OPERATING SUPPLY CURRENT IGND 1.8 2.5 mA ILOAD2 = 0 μA
2.3 mA ILOAD2 = 3 A
MINIMUM VOLTAGE REQUIREMENTS ILOAD2 = 3 A
PVINSYS to PVOUT23 VPVINSYS-PVOUT2 1.5 V
VREG_LDO to PVOUT24 VVREG_LDO-PVOUT2 1.35 V Required to drive NFET
Dropout5 VDROPOUT 100 mV
CURRENT-LIMIT THRESHOLD6 ILIMIT2 3.1 4.5 A
LDO SOFT START (SS) TIME tSSLDO 400 µs
LDO ACTIVE PULL-DOWN RPDWNLDO 300 Ω Channel disabled
OUTPUT NOISE NPVOUT2 3 µV rms 10 Hz to 100 kHz, ILOAD2 = 1 A
LDO POWER SUPPLY REJECTION RATIO PSRRLDO VPVIN2 = VPVOUT2 + 0.3 V, ILOAD2 = 1A
VPVOUT2 = 1.3 V 87 dB 1 kHz
82 dB 10 kHz
61 dB 100 kHz
38 dB 1000 kHz
VPVOUT2 = 3.3 V 89 dB 1 kHz
83 dB 10 kHz
61 dB 100 kHz
37 dB 1000 kHz
1 Limited by minimum PVINSYS to PVOUT2 and VREG_LDO to PVOUT2 voltage.
2 The LDO output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3 PVINSYS must be higher than PVOUT2 by at least VPVINSYS-PVOUT2 to keep the LDO regulating.
4 PVOUT2 must be lower than VREG_LDO by at least VVREG_LDO-PVOUT2 to keep the LDO regulating.
5 The dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage.
6 The current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output
voltage is the current that causes the output voltage to drop to 90% of 1.0 V or 0.9 V.
ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
HEADROOM VOLTAGE (PVIN2 − PVOUT2) VHR 160 mV ILOAD2 = 1 mA
280 mV ILOAD2 = 1.5 A
400 mV ILOAD2 = 3 A
Data Sheet ADP5003
Rev. A | Page 7 of 31
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
PVIN1/PVINSYS to AGND1/AGND2
−0.3 V to +16 V
PVIN2 to AGND1/AGND2 −0.3 V to +6.0 V
AGND1 to AGND2 −0.3 V to +0.3 V
PGND1 to AGND1/AGND2 −0.3 V to +0.3 V
PVOUT2 to AGND1/AGND2 −0.3 V to the lower of
(PVIN2 + 0.3 V) or +6.0 V
VFB2N to AGND1/AGND2/PGND1
−0.3 V to +0.3 V
VOUT1, VFB2P, EN1, EN2, SYNC, RT,
REFOUT, VBUF, VSET1, VSET2,
COMP1 to AGND1/AGND2
−0.3 V to the lower of (VREG
+ 0.3 V) or +6.0 V
SW1 to PGND1 −0.3 V to (PVIN1 + 0.3 V)
VREG, VREG_LDO to
AGND1/AGND2/PGND1/VFB2N
−0.3 V to the lower of
(PVINSYS + 0.3 V) or +6.0 V
VREG to VREG_LDO −0.3 V to +0.3 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature
Range
−40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Table 6. Thermal Resistance
Package Type θJA1 θJC1 Unit
CP-32-7 46.91 20.95 °C/W
1 θJA and θJC are based on a 4-layer PCB (two signal and two power planes)
with nine thermal vias connecting the exposed pad to the ground plane as
recommended in the Layout Considerations section.
ESD CAUTION
ADP5003 Data Sheet
Rev. A | Page 8 of 31
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. EX P OSE D THERM AL PAD. CO NNE CT T HE
EXPOSE D THERM AL PAD TO AGND1.
24 AGND1
23 VREG
22 RT
21 COMP1
20 PWRGD
19 VSET1
18 REFOUT
17 VSET2
1
2
3
4
5
6
7
8
PGND1
VOUT1
EN1
EN2
SYNC
PVIN2
PVIN2
PVIN2
9
10
11
12
13
14
15
16
PVOUT2
PVOUT2
PVOUT2
VFB2P
VFB2N
VBUF
AGND2
VREG_LDO
32
31
30
29
28
27
26
25
PGND1
PGND1
SW1
SW1
SW1
PVIN1
PVIN1
PVINSYS
ADP5003
TOP VIEW
(No t t o Scal e)
15021-002
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1, 31, 32 PGND1 Buck Regulator Dedicated Power Ground.
2 VOUT1 Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor.
3 EN1 Buck Regulator Precision Enable Pin. Drive the EN1 pin high to turn on the buck regulator, and drive the EN1 pin
low to turn off the buck regulator.
4 EN2 LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn
off the LDO regulator.
5 SYNC Synchronization Input. To synchronize the switching frequency of the device to an external clock, connect this
pin to an external clock with a frequency from 300 kHz to 2.5 MHz.
6 to 8 PVIN2 LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2.
9 to 11 PVOUT2 LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2.
12 VFB2P LDO Regulator Positive Sense Feedback Input. Connect a sense trace to the LDO output at the load. Route this
pin alongside the VFB2N pin on the PCB.
13 VFB2N LDO Regulator Ground Sense Feedback Input. Connect a sense trace to ground at the load. Route this pin
alongside the VFB2P pin on the PCB.
14 VBUF Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N.
15 AGND2 LDO Dedicated Analog Ground.
16 VREG_LDO Internal Regulator Output for the LDO. Connect a 1 µF ceramic decoupling capacitor between this pin and
AGND2. Do not use this pin to power external devices.
17 VSET2 LDO Regulator Output Voltage Configuration Input.
18 REFOUT Internal Reference Output Required for Driving the External Resistor Dividers for VSET1 and VSET2. Connect a
0.22 µF ceramic capacitor between this pin and AGND2.
19 VSET1 Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom
control.
20 PWRGD Power-Good Digital Output (Open-Drain NFET Pull-Down Driver).
21 COMP1 Buck Regulator External Compensation Pin.
22 RT Resistor Adjustable Frequency Programming Input.
23 VREG Internal Regulator Output. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND1. Do not
use this pin to power external devices.
24 AGND1 Analog Ground.
25 PVINSYS System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1.
26, 27 PVIN1 Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1.
28 to 30 SW1 Buck Regulator Switching Output.
EPAD Exposed Thermal Pad. Connect the exposed thermal pad to AGND1.
Data Sheet ADP5003
Rev. A | Page 9 of 31
TYPICAL PERFORMANCE CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
00.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
LO AD CURRE NT (A)
3.3V
2.5V
1.8V
1.3V
1.1V
15021-307
Figure 3. Buck Efficiency vs. Load Current, VPVIN1 = 5 V, fSW = 600 kHz at
Various Buck Output Voltages
0
10
20
30
40
50
60
70
80
90
100
00.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
LO AD CURRE NT (A)
3.3V
2.5V
1.8V
1.3V
1.1V
15021-306
Figure 4. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, fSW = 600 kHz at
Various Buck Output Voltages
0
10
20
30
40
50
60
70
80
90
100
00.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
LO AD CURRE NT (A)
300kHz
600kHz
1MHz
15021-308
Figure 5. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, VPVOUT1 = 3.3 V at
Various Buck Switching Frequencies
15021-407
0
10
20
30
40
50
60
70
80
90
100
00.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
LOAD CURRENT ( A)
3.3V
2.5V
1.8V
1.3V
1.1V
Figure 6. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 5 V,
fSW = 600 kHz at Various LDO Output Voltages
15021-408
0
10
20
30
40
50
60
70
80
90
00.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
LOAD CURRENT ( A)
3.3V
2.5V
1.8V
1.3V
1.1V
Figure 7. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V,
fSW = 600 kHz at Various LDO Output Voltages
0
10
20
30
40
50
60
70
80
90
00.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
LO AD CURRE NT (A)
300kHz
600kHz
1MHz
15021-311
Figure 8. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V,
VPVOUT2 = 3.3 V at Various Buck Switching Frequencies
ADP5003 Data Sheet
Rev. A | Page 10 of 31
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
0.1A
1A
2A
3A
15021-304
Figure 9. LDO PSRR vs. Frequency, VHR = 0.3 V, VPVOUT2 = 1.3 V at
Various LDO Load Currents
110 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
0.2V
0.3V
0.4V
0.5V
15021-305
Figure 10. LDO PSRR vs. Frequency, VPVOUT2 = 1.3 V, ILOAD2 = 1 A at Various LDO
Headroom Voltages
0.1
1
10
100
1000
110 100 1k 10k 100k 1M 10M
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY ( Hz )
0.9V
3.3V
I
PVOUT2
= 1A
15021-231
Figure 11. LDO Noise Spectral Density vs. Frequency at Various LDO Output
Voltages
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
0.1A
1A
2A
3A
15021-302
Figure 12. LDO PSRR vs. Frequency, VHR = 0.3 V, VPVOUT2 = 3.3 V at
Various LDO Load Currents
110 100 1k 10k 100k 1M 10M
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
FREQUENCY (Hz)
0.2V
0.3V
0.4V
0.5V
15021-303
Figure 13. LDO PSRR vs. Frequency, VPVOUT2 = 3.3 V, ILOAD2 = 1 A at Various LDO
Headroom Voltages
0.1
1
10
100
1000
110 100 1k 10k 100k 1M 10M
NOISE SPECTRAL DENSI TY (nV/√Hz)
FREQUENCY (Hz)
0.1A
1A
3A
V
PVOUT2
= 3.3V
15021-232
Figure 14. LDO Noise Spectral Density vs. Frequency, VPVOUT2 = 3.3 V at
Various LDO Load Currents
Data Sheet ADP5003
Rev. A | Page 11 of 31
0.1
1
10
100
1000
10000
100000
10 100 1k 10k 100k 1M 10M
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
3A
2A
1A
15021-515
Figure 15. Adaptive Mode Noise Spectral Density vs. Frequency at various
Load Currents, VPVOUT1 = VPVIN2 =3.7 V, VPVOUT2 = 3.3 V, fSW = 2 MHz, L = 1.5 μH,
RC = 23.7 kΩ, CC = 1 nF, CCP = 10 pF, CPVOUT1 = 22 μF
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
4.2 5.0 7.0 9.0 11.0 13.0 15.0
6.0 8.0 10.0 12.0 14.0
DEVI ATI ON F ROM AV E RAGE VVOUT1 ( %)
INPUT VOLTAGE (V)
15021-418
Figure 16. Buck Line Regulation, VPVOUT1 = 3.3 V, ILOAD1 = 1 A, fSW = 600 kHz
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DEVIATION FROMAVERAGE VPVOUT2 (%)
HEADROOM ( V )
15021-315
Figure 17. LDO Line Regulation, VPVOUT2 = 3.3 V, ILOAD2 = 1 A
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
00.5 1.0 1.5 2.0 2.5 3.0
DEVIATION FROM AVERAGE V
VOUT1
(%)
LO AD CURRE NT (A)
15021-312
Figure 18. Buck Load Regulation, VPVIN1 = 12 V, VPVOUT1 = 3.3 V, fSW = 600 kHz
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
00.5 1.0 1.5 2.0 2.5 3.0
DEVIATION FROMAVERAGE VPVOUT2 (%)
LO AD CURRE NT (A)
15021-314
Figure 19. LDO Load Regulation, VPVOUT2 = 3.3 V, VHR = 0.3 V
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–50 –20
10 40 70 100 130
DEVIATION FROMAVERAGE V
REFOUT
(%)
TEMPERAT URE ( °C)
15021-300
Figure 20. REFOUT Voltage (VREFOUT) vs. Temperature
ADP5003 Data Sheet
Rev. A | Page 12 of 31
–3
–2
–1
0
1
2
3
–50 –20 10 40 70 100 130
DEVIATION FROM AVERAGE
SW ITCHING FREQUENCY (%)
TEMPERATURE ( °C)
15021-301
Figure 21. Switching Frequency vs. Temperature
0
0.5
1,0
1.5
2.0
2.5
3.0
3.5
4.0
00.5 1.0 1.5 2.0 2.5 3.0
QUI E S CE NT CURRENT (mA)
LO AD CURRE NT( A)
15021-316
Figure 22. LDO Quiescent Current vs. Load Current
CH1 500mACH2 5V M200ns A CH2 8V
CH3 10mV Ω BW
2
3
1
T 94ns
VPVOUT1
IL
VSW1
15021-013
Figure 23 SW1 Waveform, VPVOUT1 = 5 V, ILOAD1 = 100 mA, fSW = 2 MHz,
L = 2.2 μH, RC = 2.7 kΩ, CC = 22 nF, CCP = 22 pF, CPVOUT1 = 22 μF
0
0.5
1.0
1.5
2.0
2.5
3.0
4 6 810 12 14
QUIESCE NT CURRENT (mA)
INPUT VOLTAGE (V)
15021-320
Figure 24. Buck Quiescent Current vs. Input Voltage
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
00.5 1.0 1.5 2.0 2.5 3.0
HEADROOM ( V )
LOAD CURRENT ( A)
15021-319
Figure 25. Adaptive Mode Headroom vs. Load Current
CH1 5.00V CH4 10.0mV ΩM400ns A CH1 5.70V
T 0.000µ s
BW
BW
CH3 500mA
1
3
4
V
SW1
I
L
V
PVOUT1
15021-526
Figure 26. SW1 Waveform, VPVOUT1 = 5 V, ILOAD1 = 3 A, fSW = 2 MHz, L = 2.2 μH,
RC = 2.7 kΩ, CC = 22 nF, CCP = 22 pF, CPVOUT1 = 22 μF
Data Sheet ADP5003
Rev. A | Page 13 of 31
CH1 5.00ACH2 500mV M20.0ms A CH2 510mV
T 40.0080ms
BWBW
CH3 10.0V BW
2
1
3
15021-317
I
L
V
SW1
V
PVOUT1
Figure 27. Entering Hiccup Mode
(VSW1 is the Voltage of the SW1 Pin, and IL is Inductor Current)
CH1 1ACH2 2V M400µs A CH2 1.56V
BW
BW
CH3 1V CH4 10V
BW
2
3
1
4
V
SW1
I
LOAD1
V
PVOUT1
V
EN1
15021-004
Figure 28. Buck Startup, VPVOUT1 = 3.3V, ILOAD1 = 3 A
(VEN1 is the EN1 voltage.)
CH2 500mV CH4 20. 0mV M80µs A CH2 12.4V
T 25.50%
Ω
BWBW
4
2
V
PVIN1
V
PVOUT1
15021-116
10V OFFSET
0.11V/µs
0.42V/µs
Figure 29. Buck Line Transient, VPVIN1 = 12 V to 13 V, VPVOUT1 = 1.2 V, ILOAD1 = 1A,
fSW = 0.6 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 2 nF, CCP = 22 pF, CPVOUT1 = 44 μF
CH1 5.00ACH2 500mV M20.0ms A CH2 510mV
T 40.0080ms
BWBW
CH3 10.0V
BW
2
1
3
15021-318
IL
VSW1
VPVOUT1
Figure 30. Exiting Hiccup Mode
VEN1/VEN2
VVOUT1
VPVOUT2
ILOAD2
CH1 1.00ACH2 1. 00V M1.00ms A CH3 2.04V
T 3.00400ms
CH3 2.00V CH4 1.00V
3
4
2
1
15021-238
Figure 31. Adaptive Mode Startup, VPVOUT2 = 3.3 V, ILOAD2 = 1 A
(VEN2 is the EN2 voltage.)
CH2 500mV CH4 1 AM200µs A CH4 1.46A
4
2
T 493.480µ s
VPVOUT1
ILOAD1
2.3A/µs 3.1A/µs
15021-118
Figure 32. Buck Load Transient, VPVIN1 = 12 V, VPVOUT1 = 1.2 V, ILOAD1 = 0.5 A to 3 A,
fSW = 0.6 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 2 nF, CCP = 22 pF, CPVOUT1 = 44 μF
ADP5003 Data Sheet
Rev. A | Page 14 of 31
CH1 500mV CH2 1.00mV M80.0µs A CH1 3.81V
BW
1
2
T 200.960µ s
V
PVOUT2
V
PVIN2
0.07V/µs
0.18V/µs
3V OFFSET
15021-126
Figure 33. LDO Line Transient, VPVIN2 = 3.6 V to 4.1 V, VPVOUT2 = 3.3 V,
ILOAD2 = 1 A
CH2 500mV CH4 1.00mV M80µs A CH2 12.5V
T 25.90%
Ω
BWBW
4
2
V
PVOUT2
V
PVIN1
0.14V/µs
0.45V/µs
15021-140
10V OFFSET
Figure 34. Adaptive Mode Line Transient, VPVIN1 = 11 V to 13 V, VPVOUT2 = 3.3 V,
ILOAD2 = 1 A, fSW = 1.5 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 22 nF, CCP = 22 pF,
CPVOUT1 = 64 μF
CH4 20.0mV Ω
CH3 1.00 A M8.00µs A CH3 920mA
T 24.7%
BW
3
4
IPVIN1
VPVOUT2
15021-535
Figure 35. Adaptive Mode Load Transient, VPVIN1 = 12 V, VPVOUT2 = 3.3 V,
ILOAD2 = 0.5 A to 3 A, fSW = 1.5 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 22 nF,
CCP = 22 pF, CPVOUT1 = 64 μF
CH2 20.0mV CH4 1.00AM8.00µs A CH4 1.34A
4
2
T 18.4800µ s
VPVOUT2
ILOAD2
2.3A/µs 3A/µs
15021-129
Figure 36. LDO Load Transient, VPVIN2 = 3.6 V, VPVOUT2 = 3.3 V,
ILOAD2 = 0.5 A to 3 A
CH3 500mACH4 10. 0mV M80µs A CH2 1.52V
T 24.70%
Ω
BW
4
3
V
PVOUT2
I
LOAD2
1.2A/µs 1.3A/µs
15021-141
Figure 37. Adaptive Mode Load Transient, VPVIN1 = 12 V, VPVOUT2 = 3.3 V,
ILOAD2 = 1 A to 1.5 A, fSW = 1.5 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 22 nF,
CCP = 22 pF, CPVOUT1 = 64 μF
Data Sheet ADP5003
Rev. A | Page 15 of 31
THEORY OF OPERATION
POWER MANAGEMENT UNIT
The ADP5003 is a micropower management unit combining a
step-down (buck) dc-to-dc converter and an ultralow noise low
dropout linear (LDO)regulator. The high switching frequency
and 5 mm × 5 mm, 32-lead LFCSP package allow a compact
power management solution.
Adaptive Headroom Control
The ADP5003 features a scheme to control the LDO headroom
voltage to ensure optimal operating efficiency while maintaining a
consistent power supply rejection ratio (PSRR) across the full
range of the LDO load current.
The scheme works by varying the headroom voltage across the
LDO NFET with respect to the LDO load current. Lower and
upper limits prevent the headroom from approaching zero volts
at light loads and from increasing more than necessary at high
loads.
Precision Enable/Shutdown
The ADP5003 has individual enable pins (EN1 and EN2) to
control the regulators.
The precision enable function allows a precise turn on point for
the regulators to allow the possibility of external sequencing. A
voltage level higher than VTH_H applied to the EN1 or EN2 pin
activates a regulator, whereas a level below VTH_L turns off a
regulator. The buck is controlled by EN1, and the LDO is
controlled by the EN2 pin. When both EN1 and EN2 fall below
VTH_S, the ADP5003 enters shutdown mode.
Undervoltage Lockout (UVLO)
To protect against the input voltage being too low, UVLO
circuitry is integrated into the system. If the input voltage on
PVINSYS drops to less than the UVLOPVINSYSFALL threshold, all
channels shut down.
The device is enabled again when the voltage on PVINSYS rises
to more than the UVLOPVINSYSRISE threshold, provided the enable
pins remain active.
Thermal Shutdown (TSD)
In the event that the junction temperature rises above TSD, the
thermal shutdown circuit turns off both regulators. Extreme
junction temperatures can be the result of high current operation,
poor circuit board design, or a high ambient temperature. A
hysteresis value of TSD-HYS is included so that when thermal
shutdown occurs, the regulators do not return to operation until
the on-chip temperature drops below TSD − TSD-HYS. When
emerging from thermal shutdown, both regulators restart with
soft start control.
Active Pull Down
Both regulators have active pull-down resistors discharging the
respective output capacitors when the regulators are disabled.
The pull-down resistors are connected between VOUT1 to
AGND1 and PVOUT2 to AGND2. Active pull-down resistors
are disabled when the regulators are turned on.
When the enable pins are asserted low, or a TSD or UVLO
event occurs, the active pull-down resistors enable to quickly
discharge the output capacitors. The pull-down resistors remain
engaged until the enable pins are asserted high, the fault event is
no longer present, or the VREG supply voltage falls to less than
the voltage required (approximately 1 V) to guarantee that the
pull-down resistor remains enabled.
Soft Start (SS)
Both regulators have an internal soft start function that ramps
the output voltage in a controlled manner on startup, thereby
limiting the inrush current. The soft start function reduces the
risk of noise spikes and voltage drops on the upstream supplies.
Power-Good
The ADP5003 has a dedicated power-good, open-drain, output
(PWRGD). PWRGD indicates whether one or more regulators
are outside the voltage limits specified by the power-good lower
limit (PWRGDF) and the power-good upper limit (PWRGDF +
PWRGDFH). When either one or both of the regulator outputs
are outside the power-good limits, the PWRGD output pulls low.
PWRGD will continue to pull low, provided the VREG supply
voltage remains above approximately 1 V.
When in adaptive mode, PWRGD only monitors the LDO
output, and when in standalone mode, PWRGD only monitors
the regulator/regulators that are enabled.
BUCK REGULATOR
Control Scheme
The buck regulator operates with a fixed frequency, emulated
peak current mode, pulse-width modulation (PWM) control
architecture, where the duty cycle of the integrated switches is
adjusted and regulates the output voltage. At the start of each
oscillator cycle, the positive channel field effect transistor (PFET)
switch is turned on, sending a positive voltage across the inductor.
Current in the inductor increases until the emulated current
sense signal crosses the peak inductor current threshold, which
turns off the PFET switch and turns on the NFET synchronous
rectifier. Turning on the NFET synchronous rectifier creates a
negative voltage across the inductor, which causes the inductor
current to decrease. The synchronous rectifier stays on for the
remainder of the cycle. By adjusting the peak inductor current
threshold, the buck regulator can regulate the output voltage.
ADP5003 Data Sheet
Rev. A | Page 16 of 31
The emulated inductor current scheme senses the current in the
inductor during the off phase of the cycle, when the NFET is
conducting, and uses this inductor current to generate the
emulated current sense signal during the on time of the cycle.
This scheme allows the low duty cycles necessary for high input
voltage, VIN, to output voltage, VOUT, conversion ratios.
Oscillator Frequency Control
The ADP5003 buck regulator oscillator frequency is controlled
by using the RT pin or the SYNC pin. To define the buck
regulator internal switching frequency, connect the RT pin via a
resistor to AGND1. Figure 38 shows the relationship of the buck
oscillator frequency and the RT resistor value.
0
0.5
1.0
1.5
2.0
2.5
3.0
10k 100k 1M
FREQUENCY (MHz)
RT RES ISTOR (Ω)
15021-538
Figure 38. Buck Oscillator Frequency vs. RT Resistor (RRT)
To determine the oscillator frequency (fSW), use the following
equation:
fSW = (1.78 × 1011)/RRT (1)
An upper limit prevents out of range frequencies when the RT
pin is shorted to ground or connected with a resistor value less
than 70 kΩ.
External Oscillator Synchronization
The SYNC pin is dedicated for oscillator synchronization and
allows the ADP5003 to lock to an external clock.
When an applied external clock signal is present at the SYNC pin,
the buck regulator operates in sync with this signal.
When alternating between external clocks and the internal
oscillator, the presence of an external frequency causes a
multiplexer to switch between the internal oscillator and the
external SYNC frequency. The output of this multiplexer acts as
the frequency reference to an internal phase-locked loop (PLL),
which ensures that changing between the two modes of operation
results in a smooth transition between the different frequencies.
Buck Startup
The buck regulator turns on with a controlled soft start ramp to
limit inrush current. The reference of the buck is ramped
during tSSBUCK, which is typically 2 ms (see Figure 39).
A CH2 1.20V
CH1 1.00ACH2 5. 0V 4.00µs
T 1.60ms
BW
CH3 5.00V CH4 1. 0V
BW
BW
BW
4
1
2
3
V
EN1
V
PVOUT1
t
SSBUCK
I
LOAD1
V
SW1
15021-441
Figure 39. Buck Startup
Data Sheet ADP5003
Rev. A | Page 17 of 31
Current-Limit and Short-Circuit Protection
The buck regulator includes current-limit protection circuitry
to limit the amount of forward current through the field effect
transistor (FET) switches. When the valley inductor current
exceeds the overcurrent limit threshold for a number of clock
cycles during an overload or short-circuit condition, the
regulator enters hiccup mode. The regulator stops switching
and then restarts with a new soft start cycle after the hiccup
time, tHICCUP, and repeats until the over-current condition is
removed. If the buck regulator output voltage falls below 50%
of the nominal output voltage, the regulator immediately enters
hiccup mode. When the valley inductor current falls below the
negative current-limit threshold, the NFET turns off and the
PFET remains off allowing the inductor current to be discharged
via the PFET body diode. The PFET turns on again with the
next clock edge after the inductor current no longer exceeds
the negative current-limit threshold.
A CH2 1.08V
CH1 10.0V CH2 2.00V 20.0ms
T 79.7600ms
CH3 2.0A
BW
V
VOUT1
I
L
V
SW1
15021-440
2
3
1
2
3
1
t
HICCUP
3.5A
3.5A
Figure 40. Short-Circuit Response (Current Limit and Hiccup Mode)
LDO REGULATOR
The ADP5003 contains a single low noise, low dropout (LDO)
linear regulator that uses an NFET pass device to provide high
PSRR with low headroom voltage and an output current up to 3 A.
The LDO regulator can operate with an input voltage of 0.65 V
to 5 V while providing excellent line and load transient response
using 10 µF ceramic input and output capacitors.
LDO Startup
The LDO regulator turns on with a controlled soft start ramp to
limit inrush current. This soft start ramp is dictated by tSSLDO,
which is typically 400 µs.
–4.5
–3.5
–2.5
–1.5
–0.5
0.5
1.5
2.5
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–0.4 –0.2 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V
EN2
(V)
V
PVOUT2
(V)
TIME (ms)
0.1A
1A
3A
V
EN2
15021-019
Figure 41. LDO Startup
Current Limit
The LDO operates in current limit when the output load exceeds
ILIMIT2. When in current limit operation, the output voltage
reduces to maintain a constant output current.
Differential Remote Sensing
The LDO can sense at the point of load by using VFB2P and
VFB2N as shown in Figure 42. Differential remote sensing
compensates for both the source drop and the return drop to
provide a more precise supply scheme at the point of load.
AGND1
PVOUT2
PVOUT2
PVOUT2
VFB2P
LOW NOISE
LDO ACTIVE
FILTER
3A
LOAD
+
–
+–
–+
VFB2N
AGND2
15021-443
Figure 42. Differential Remote Sensing
ADP5003 Data Sheet
Rev. A | Page 18 of 31
POWER-GOOD
An external pull-up resistor is necessary to drive the PWRGD
output high (see Figure 43). Through the value of the pull-up
resistor is not critical, it is recommended to use a 10 kΩ to
300 kΩ resistor. The resistor must be pulled to a voltage level
no greater than 5.5 V.
PWRGD GPIO
R
PULLUP
V
PWRGD
V
PULLUP
15021-444
Figure 43. Power-Good Setup
OUTPUT VOLTAGE OF THE BUCK REGULATOR
The output voltage on the buck regulator is adjustable through
an external resistor divider. When using adaptive mode, the
ADP5003 controls the buck output voltage.
The adjustable output voltage configuration is shown in Figure 44.
BUCK
RTOP1
RBOT1
VSET1
SW1
PVIN1
REFOUT VOUT1
PVOUT1
15021-057
Figure 44. Buck Regulator Adjustable Output Voltage
To calculate the buck output voltage, use the following equation:
11
1
1
BOTTOP
BOT
BUCK
REFOUTPVOUT RR
R
AVV (2)
where:
VREFOUT is the REFOUT output voltage.
ABUCK is the buck regulator gain.
RBOT1 is the bottom divider resistor.
RTOP1 is the top divider resistor.
OUTPUT VOLTAGE OF THE LDO REGULATOR
The output voltage on the LDO regulator is adjustable through
an external resistor divider. The LDO adjustable output voltage
configuration is shown in Figure 45.
LDO
R
TOP2
R
BOT2
VSET2
PVIN2
REFOUT VFB2P
VFB2N
PVOUT2
15021-059
Figure 45. LDO Adjustable Output Voltage Configuration
To calculate the LDO output voltage, use the following
equation:
22
2
2
BOTTOP
BOT
LDO
REFOUTPVOUT RR
R
AVV (3)
where:
ALDO is the LDO gain.
RBOT2 is the bottom divider resistor.
RTOP2 is the top divider resistor.
VOLTAGE CONVERSION LIMITATIONS
For a given input voltage and switching frequency, an upper
and lower limitation on the output voltage exists due to the
minimum on time and minimum off time. The minimum on
time limits the minimum output voltage for a given input
voltage and switching frequency.
If the minimum on time is exceeded, the ADP5003 may not
switch at a fixed frequency because the device can switch at an
effective zero on time, resulting in unpredictable switching
frequencies and unwanted noise.
To calculate the minimum output voltage for a given input
voltage and fixed switching frequency, use the following
equation:
VOUT_MIN = VPVIN1 × tMIN_ON × fSW − (RPFET – RNFET) ×
IOUT_MIN × tMIN_ON × fSW − (RNFET + RL) × IOUT_MIN (4)
where:
VOUT_MIN is the minimum output voltage.
VPVIN1 is the input voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RPFET is the high-side PFET on resistance.
RNFET is the low-side NFET on resistance.
IOUT_MIN is the minimum output current.
RL is the resistance of the output inductor.
Data Sheet ADP5003
Rev. A | Page 19 of 31
The minimum off time limits the maximum duty cycle which
in turn limits the maximum output voltage for a given input
voltage and switching frequency. Calculate the maximum output
voltage for a given input voltage and switching frequency by
using the following equation:
VOUT_MAX = VPVIN1 × (1 − tMIN_OFF × fSW) − (RPFET – RNFET) × IOUT_MAX ×
(1 − tMIN_OFF × fSW) − (RNFET + RL) × IOUT_MAX (5)
where:
VOUT_MAX is the maximum output voltage.
IOUT_MAX is the maximum output current.
tMIN_OFF is the minimum off time.
As shown in Equation 4 and Equation 5, reducing the switching
frequency eases the minimum on time and minimum off time
limitations.
COMPONENT SELECTION
Output Capacitors
Higher output capacitor values reduce the output voltage ripple
and improve the load transient response.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 25 V are recommended for best performance. Y5V
and Z5U dielectrics are not recommended for use with any dc-
to-dc converter because of their poor temperature and dc bias
characteristics.
Use the following equation to calculate the worst case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage:
CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance) (6)
where:
CEFFECTIVE is the effective capacitance at the operating voltage.
CNOMINAL is the nominal data sheet capacitance.
TEMPCO is the worst case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst case component tolerance.
To guarantee the performance of the device, it is imperative to
evaluate the dc bias effects, temperature, and tolerances on the
behavior of the capacitors for each application.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Use the following equation to calculate the minimum
capacitance needed for a specific output voltage ripple:
)(
8
—ESR
LRIPPLE
SW
L
OUT_MIN
RΔI
V
f
ΔI
C×××
≅
(7)
where:
ΔIL is the current ripple.
fSW is the switching frequency.
VRIPPLE is the allowed peak-to-peak voltage ripple.
RESR is the effective series resistance of the capacitor.
The minimum capacitance needed for stability considering
temperature and dc bias effects is 22 µF.
The minimum capacitance recommended for the LDO is 10 µF.
Table 8. Recommended Output Capacitors
Vendor Part No. Value (µF) Type Voltage Rating (V) Case
Wurth 885 012 207 026 10 X7R 10 0805
885 012 209 006 22 X7R 10 1210
885 012 109 012 47 X5R 25 1210
885 012 109 004 100 X5R 6.3 1210
Murata GRM21BR71A106KE51 10 X7R 10 0805
GRM32ER71C226KEA8 22 X7R 16 1210
GRM32ER71A476KE15 47 X7R 10 1210
ADP5003 Data Sheet
Rev. A | Page 20 of 31
Input Capacitor
The input current to the buck converter steps from zero to a
positive value that is dependent on inductor value, switching
frequency, and load current (typically between 1 A and 4 A) and
then drops quickly to zero again every switching cycle. Because
these current pulses occur at relatively high frequencies (0.3 MHz
to 2.5 MHz), the input bypass capacitor provides most of the
high frequency current while the input power source supplies
only the average current. Higher value input capacitors reduce
the input voltage ripple and improve transient response.
To minimize supply noise, it is recommended to place a low
ESR capacitor as close as possible to the relevant supply pin.
Inductor
The high switching frequency of the ADP5003 buck allows the
selection of small chip inductors. A small inductor leads to larger
inductor current ripple that provides improved transient response
but degrades efficiency. The sizing of the inductor is a trade-off
between efficiency and transient response. As a guideline, the
inductor peak-to-peak current ripple is typically set to 1/3 of
the maximum load current for optimal transient response and
efficiency.
To calculate the inductor value, L, use the following equation:
L = ((VPVIN1 − VPVOUT1) × D)/(ΔIL × fSW) (8)
where:
VPVIN1 is the input voltage.
VPVOUT1 is the output voltage.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL is the inductor ripple current.
fSW is the switching frequency.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. Use the following equation to
calculate the inductor peak current:
IPEAK = ILOAD1 + (ΔIL/2) (9)
where:
ILOAD1 is the output current.
ΔIL is the inductor ripple current.
Inductor conduction losses are minimized by using larger sized
inductors that have smaller dc resistance; this in turn improves
efficiency at the cost of solution size. Due to the high switching
frequency of the ADP5003, shielded ferrite core material is
recommended for its low core losses and low electromagnetic
interference (EMI).
Table 9. Recommended Inductors
Vendor Part No. Value (µH) Saturation Current, IS AT (A) RMS Current, IRMS (A) DC Resistance (mΩ) Size (mm)
Coilcraft XAL4020-102 1 8.7 6.7 13.25 4 × 4
XAL4020-122 1.2 7.9 6.6 17.75 4 × 4
XAL4020-152 1.5 7.1 5.2 21.45 4 × 4
XAL4020-222 2.2 5.6 4 35.2 4 × 4
XAL5030-102 1 14 8.7 8.5 5 × 5
XAL5030-122 1.2 12.5 7.9 11.4 5 × 5
XAL5030-222 2.2 9.2 7.2 13.2 5 × 5
XAL5030-332 3.3 8.7 5.9 21.2 5 × 5
XAL5050-562 5.6 6.3 5.3 23.45 5 × 5
XAL5050-682 6.8 6 4.7 26.75 5 × 5
XEL6030-102 1 18 12 6.32 6 × 6
XEL6030-152 1.5 15 10 9.57 6 × 6
XEL6030-222 2.2 13 7 12.7 6 × 6
XEL6030-332 3.3 10.5 6 19.92 6 × 6
XEL6060-472 4.7 11.4 9 13.65 6 × 6
XAL6060-562 5.6 9.9 7.5 14.46 6 × 6
XEL6060-682 6.8 7.9 7.3 20.82 6 × 6
XEL6060-822 8.2 7.6 7 22.71 6 × 6
XAL6060-103 10 7.6 5 27 6 × 6
Wurth 744 383 570 10 1 9.6 7.4 11.6 4 × 4
744 383 570 12 1.2 8.8 7 13.4 4 × 4
744 383 570 15 1.5 8.5 6.2 17.1 4 × 4
744 383 570 18 1.8 8 5.8 18 4 × 4
744 383 570 22 2.2 7 5.2 22 4 × 4
Data Sheet ADP5003
Rev. A | Page 21 of 31
COMPENSATION COMPONENTS DESIGN
For the peak current mode control architecture, the power stage
can be simplified as a voltage controlled current source that
supplies current to the output capacitor and load resistor. The
simplified loop is composed of one dominant pole and a zero
contributed by the output capacitor ESR.
The ADP5003 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 46 shows the
simplified peak current mode control, small signal circuit.
R
ESR
R
+
–
g
m
R
C
C
CP
C
PVOUT1
C
C
R
TOP1
R
BOT1
–
+
A
VI
V
PVOUT1
V
COMP1
A
BUCK
V
SET1
V
REFOUT
V
PVOUT1
15021-043
Figure 46. Simplified Peak Current Mode Control, Small Signal Circuit
The compensation components, RC and CC, contribute a zero,
and the optional CCP and RC contribute an optional pole.
The following procedure shows how to select the compensation
components (RC, CC, and CCP) for ceramic output capacitor
applications:
1. Determine the cross frequency (fC). Generally, fC is
between fSW/12 and fSW/6.
2. Use the following equation to calculate RC:
VI
m
BUCK
PVOUT
C
Ag
A
C
R×
××π×
=
1
2
(10)
where:
CPVOUT1 is the output capacitance.
AVI = 7 A /V.
3. Place the compensation zero at the domain pole (fP).
Determine CC as follows:
CC = ((R + RESR) × CPVOUT1)/RC (11)
where:
RESR is the equivalent series resistance of the output
capacitor.
4. CCP is optional. It can cancel the zero caused by the ESR of
the output capacitor. Determine CCP as follows:
CCP = (RESR × CPVOUT1)/RC (12)
JUNCTION TEMPERATURE
In cases where the ambient temperature (TA) is known, the
thermal resistance parameter (θJA) can estimate the junction
temperature rise (TJ). TJ is calculated with TA and the power
dissipation (PD) using the following formula:
TJ = TA + (PD × θJA) (13)
The typical θJA value for the 32-lead, 5 mm × 5 mm LFCSP is
46.91°C/W. An important factor to consider is that θJA is based
on a 4-layer, 4 inches × 3 inches, 2.5 ounces copper PCB, as per
the JEDEC standard, and applications may use different sizes
and layers. It is important to maximize the copper used to
remove the heat from the device. Copper exposed to air
dissipates heat better than copper used in the inner layers.
Connect the exposed pad to the ground plane with several vias.
If the case temperature can be measured, the junction
temperature is calculated by
TJ = TC + (PD × θJC) (14)
where:
TC is the case temperature.
θJC is the junction to case thermal resistance provided in Table 6.
To achieve reliable operation of the buck converter and LDO
regulator, the estimated die junction temperature of the
ADP5003 must be less than 125°C. Reliability and mean time
between failures (MTBF) is highly affected by increasing the
junction temperature. Additional information about product
reliability can be found in the Analog Devices, Inc., Reliability
Handbook at www.analog.com/reliability_handbook.
The total power dissipation in the ADP5003 simplifies to
PD = PDBUCK + PDLDO (15)
where:
PDBUCK = (VPVIN1 × IPVIN1) − (VPVOUT1 × ILOAD1).
PDLDO = ((VPVIN2 − VPVOUT2) × ILOAD2) + (VPVIN2 × IGND).
ADP5003 Data Sheet
Rev. A | Page 22 of 31
BUCK REGULATOR DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for the buck
regulator. Table 10 lists the design requirements for this
example.
Table 10. Example Design Requirements for the Buck Regulator
Parameter Specification
Input Voltage VPVIN1 = 12 V
Output Voltage VPVOUT1 = 2.5 V
Output Current
I
LOAD1
= 3 A
Output Ripple ΔVOUT1_RIPPLE = 25 mV
Load Transient ±5% at 20% to 80% load transient
SETTING THE SWITCHING FREQUENCY FOR THE
BUCK REGULATOR
The first step is to determine the switching frequency for the
ADP5003 design. In general, higher switching frequencies
produce a smaller solution size due to the lower component
values required, whereas lower switching frequencies result in
higher conversion efficiency due to lower switching losses.
The switching frequency of the ADP5003 can be set from
0.3 MHz to 2.5 MHz by connecting a resistor from the RT pin
to ground. The selected resistor allows the user to make decisions
based on the trade-off between efficiency and solution size. (For
more information, see the Oscillator Frequency Control section.)
However, the highest supported switching frequency must be
assessed by checking the voltage conversion limitations enforced
by the minimum on time and the minimum off time (see the
Voltage Conversion Limitations section).
In this design example, a switching frequency of 600 kHz is
used to achieve an ideal combination of small solution size and
high conversion efficiency. To set the switching frequency to
600 kHz, use Equation 1 to calculate the resistor value, RRT. This
gives a standard resistor value of RT = 294 kΩ.
SETTING THE OUTPUT VOLTAGE FOR THE BUCK
REGULATOR
Select a value for the top resistor (RTOP1) and then calculate the
bottom feedback (RBOT1) resistor by using the following
equation:
RBOT1 = (RTOP1 × VPVOUT1)/((VREFOUT × ABUCK) − VPVOUT1) (16)
where:
VPVOUT1 is the buck output voltage.
VREFOUT i s 2 V.
ABUCK is the buck regulator gain.
To set the output voltage to 2.5 V, RTOP1 is set to 100 kΩ, giving
an RBOT1 value of 100 kΩ.
SELECTING THE INDUCTOR FOR THE BUCK
REGULATOR
The peak-to-peak inductor ripple current, ΔIL, is set to 35% of
the maximum output current. Use Equation 8 to estimate the
value of the inductor:
L = ((VPVIN1 − VPVOUT1) × D)/(ΔIL × fSW)
where:
VPVIN1 = 12 V.
VPVOUT1 = 2.5 V.
D is the duty cycle (D = VPVOUT1/VPVIN1).
ΔIL = 35% × 3 A = 1.05 A.
fSW = 600 kHz.
The resulting value for L is 3.14 µH. The selected standard
inductor value is 3.3 µH; therefore, ΔIL is 1 A.
To calculate the peak inductor current (IPEAK), use Equation 9:
IPEAK = ILOAD1 + (ΔIL/2)
The calculated peak current for the inductor is 3.5 A.
SELECTING THE OUTPUT CAPACITOR FOR THE
BUCK REGULATOR
The output capacitor must meet the output voltage ripple, load
transient requirements and stability requirements. To meet the
output voltage ripple requirement, use Equation 7 to calculate
the capacitance:
)
(8
—ESR
LRIPPLE
SW
L
OUT_MIN
R
ΔIV
f
ΔI
C×××
≅
The calculated capacitance, COUT_MIN, is 8.7 µF.
To meet the ±5% overshoot and undershoot requirements, use
the following equations to calculate the capacitance:
( )
UVOUTPVOUT
PVIN
STEP
UV
OUT_UV
ΔV
VV
LΔI
K
C
_1
1
2
–2 ××
××
=
(17)
( )
2
1
2
_1
2
–PVOUTOVOUTPVOUT
STEP
OV
OUT_OV VΔV
V
L
ΔIK
C+
××
=
(18)
where:
KUV and KOV are factors (typically set to 2).
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
ΔVOUT_OV is the allowable overshoot on the output voltage.
For estimation purposes, use KOV = KUV = 2; therefore,
COUT_OV = 33.4 µF and COUT_UV = 9 µF.
It is recommended to use two 22 µF ceramic capacitors.
Data Sheet ADP5003
Rev. A | Page 23 of 31
DESIGNING THE COMPENSATION NETWORK FOR
THE BUCK REGULATOR
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz;
therefore, fC is set to 60 kHz.
kΩ9.87
A/V7Sμ600
2.5kHz60Fμ44π2 =
×
××××
=
C
R
( )
nF3.72
kΩ7.18
μF44Ω0.001Ω0.833 =
×+
=
C
C
pF4.46
kΩ7.18
μF44Ω0.001 =
×
=
CP
C
Choose standard components: RC = 9.76 kΩ, CC = 4.7 nF,
CCP = 4.7 pF.
Figure 47 shows the load transient waveform.
CH2 1.00ACH3 200mV M200µs A CH2 1.08A
T 432.000µ s
BW
BW
CH4 20.0mV
2
3
4
ILOAD2
VVOUT1
VPVOUT2
15021-550
0.02A/µs 0.015A/µs
Figure 47. 0.6 A to 2.4 A Load Transient for 2.5 V Output, fSW = 0.6 MHz,
L = 3.3 μH, RC = 9.76 kΩ, CC = 4.7 nF, CCP = 4.7 pF, CPVOUT1 = 44 μF
SELECTING THE INPUT CAPACITOR FOR THE BUCK
REGULATOR
For the input capacitor, select a ceramic capacitor with a
minimum capacitance of 10 µF. Place the input capacitor close
to the PVIN1 pin. In this example, one 10 µF, X5R, 25 V
ceramic capacitor is recommended.
ADP5003 Data Sheet
Rev. A | Page 24 of 31
ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for the buck
regulator using adaptive headroom control. Table 11 lists the
design requirements for this example.
Table 11. Example Design Requirements for the Buck
Regulator Using Adaptive Headroom Control
Parameter Specification
Input Voltage VPVIN1 = 12 V
Output Voltage VPVOUT2 = 1.3 V
Output Current ILOAD1 = ILOAD2 = 3 A
Buck Load Transient ±100 mV at 20% to 80% load transient
SETTING THE SWITCHING FREQUENCY FOR THE
BUCK REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Similar to the buck design example, a switching frequency of
600 kHz is used to achieve a good combination of small solution
size and high conversion efficiency. To set the switching frequency
to 600 kHz, use Equation 1 to calculate the resistor value, RRT:
RRT (kΩ) = 1.78 × 1011/fSW (kHz)
Therefore, select standard resistor RT = 294 kΩ.
SETTING THE OUTPUT VOLTAGE FOR THE LDO
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Select a value for the top feedback resistor (RTOP2) and then
calculate the bottom resistor (RBOT2) by using the following
equation:
RBOT2 = (RTOP2 × VPVOUT2)/((VREFOUT × ALDO) – VPVOUT2) (19)
where:
VPVOUT2 is the LDO output voltage.
VREFOUT is 2 V.
ALDO is the LDO regulator gain.
To set the output voltage to 1.3 V, RTOP2 is set to 100 kΩ giving
an RBOT2 value of 65 kΩ.
SELECTING THE INDUCTOR FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
The peak-to-peak inductor ripple current, ΔIL, is set to 35% of
the maximum output current. Use the Equation 8 to estimate
the value of the inductor:
L = ((VPVIN1 – VPVOUT1) × D)/(ΔIL × fSW)
where:
VPVIN1 = 12 V.
VPVOUT1 = VPVOUT2 + VHR = 1.7 V.
VPVOUT2 = 1.3 V.
VHR is the adaptive headroom voltage at steady state current. See
Table 4 and Figure 25 for the approximate values of VHR vs. load
current. For this example, use VHR equal to 0.4 V for steady state
load current of 3 A.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL = 35% × 3 A = 1.05 A.
fSW = 600 kHz.
The resulting value for L is 2.32 μH. The selected standard
inductor value is 2.2 μH; therefore, ΔIL is 1.1 A.
To calculate the peak inductor current (IPEAK), use Equation 9:
IPEAK = ILOAD1 + (ΔIL/2)
The calculated peak current for the inductor is 3.55 A.
SELECTING THE OUTPUT CAPACITORS FOR THE
BUCK REGULATOR USING ADAPTIVE HEADROOM
CONTROL
To ensure that the LDO regulator does not track the buck
output, the undershoot voltage must be set to a value less than
the minimum adaptive headroom voltage. Use Equation 17 and
Equation 18 to calculate the capacitance.
For estimation purposes, use KOV = KUV = 2; therefore,
COUT_OV = 40.7 μF and COUT_UV = 6.92 μF.
It is recommended to use a single 47 μF ceramic capacitor for the
output of the buck and a single 10 μF for the output of the LDO.
Data Sheet ADP5003
Rev. A | Page 25 of 31
DESIGNING THE COMPENSATION NETWORK FOR
THE BUCK REGULATOR USING ADAPTIVE
HEADROOM CONTROL
Due to the addition of the adaptive headroom scheme in the
feedback loop, a lower bandwidth is required. Set the crossover
frequency, fC, to fSW/60. In this example, fSW is set to 600 kHz;
therefore, fC is set to 10 kHz.
kΩ1.76
A/V7Sμ600
2.5kHz10Fμ47π2 =
×
××××
=
C
R
( )
nF15.2
kΩ1.76
μF47Ω0.001Ω0.433 =
×+
=
C
C
pF26.7
kΩ1.76
μF47Ω0.001 =
×
=
CP
C
Choose standard components: RC = 1.74 kΩ, CC = 22 nF,
CCP = 22 pF.
Figure 48 shows the load transient waveform.
CH1 1.00ACH4 100mV 200µs A CH3 1.38A
T 508µs
BWBW
15021-449
4
1
VPVOUT1
0.02A/µs 0.013A/µs
ILOAD1
Figure 48. 0.6 A to 2.4 A Load Transient for 2.5 V Output, fSW = 600 kHz,
L = 2.2 μH, RC = 1.74 kΩ, CC = 22 nF, CCP = 22 pF, CPVOUT1 = 47μF
SELECTING THE INPUT CAPACITOR FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
For the input capacitor, select a ceramic capacitor with a
minimum value of 10 µF. Place the input capacitor close to the
PVIN1 pin. In this example, one 10 µF, X5R, 25 V ceramic
capacitor is recommended.
ADP5003 Data Sheet
Rev. A | Page 26 of 31
RECOMMENDED EXTERNAL COMPONENTS FOR THE BUCK REGULATOR
Table 12 lists the recommended external components for buck applications up to 3 A operation (±5% tolerance at an ~60% step transient),
and Table 13 lists the recommended buck external components for adaptive headroom applications up to 3 A operation (VPVOUT2 ±
100 mV at an ~60% step transient).
Table 12. Recommended External Components for Buck Applications up to 3 A Operation (±5% Tolerance at an ~60% Step Transient)
fSW (kHz) VIN (V) VOUT (V) L (μH) COUT (μF) RTOP1 (kΩ) RBOT1 (kΩ) RC (kΩ) CC (nF) CCP (pF)
300 12 1 3.3 210 200 49.9 23.7 3.3 10
12 1.2 4.7 204.7 150 47.5 23.2 3.3 10
12 1.5 4.7 147 174 75 16.5 4.7 10
12 1.8 5.6 110 150 84.5 12.4 4.7 10
12 2.5 6.8 69 100 100 7.68 6.8 10
12 3.3 8.2 47 49.9 97.6 5.23 10 10
12 5 10 26.7 0 open 3.01 15 10
5 1 3.3 210 200 49.9 23.7 3.3 10
5 1.2 3.3 147 150 47.5 16.5 3.3 10
5 1.5 4.7 132 174 75 14.7 4.7 10
5 1.8 4.7 94 150 84.5 10.5 4.7 10
5 2.5 4.7 47 100 100 5.23 6.8 10
5 3.3 4.7 51.7 49.9 97.6 5.76 10 10
600 12 1.5 2.2 69 150 84.5 15.4 2.2 4.7
12 1.8 3.3 69 150 84.5 15.4 2.2 4.7
12 2.5 3.3 32 100 100 7.15 3.3 4.7
12 3.3 4.7 26.7 49.9 97.6 6.04 4.7 4.7
12 5 5.6 22 0 Open 4.99 6.8 4.7
5 1 1.5 94 200 49.9 21 1.5 4.7
5 1.2 1.8 147 150 47.5 33.2 1.5 4.7
5 1.5 1.8 49.2 174 75 11 2.2 4.7
5 1.8 2.2 47 150 84.5 10.5 2.2 4.7
5 2.5 2.2 23 100 100 5.11 3.3 4.7
5 3.3 2.2 24.2 49.9 97.6 5.49 4.7 4.7
1000 12 2.5 2.2 22 100 100 8.25 2.2 2.2
12 3.3 3.3 22 49.9 97.6 8.25 3.3 2.2
12 5 3.3 22 0 Open 8.25 4.7 2.2
5 1 1 69 200 49.9 25.5 1 2.2
5 1.2 1 47 150 47.5 17.4 1 2.2
5 1.5 1.2 32 174 75 12.1 1.5 2.2
5 1.8 1.2 23 150 84.5 8.66 1.5 2.2
5 2.5 1.5 22 100 100 8.25 2.2 2.2
5 3.3 1.2 22 49.9 97.6 8.25 3.3 2.2
Data Sheet ADP5003
Rev. A | Page 27 of 31
Table 13. Recommended Buck External Components for Adaptive Headroom Applications up to 3 A Operation (VPVOUT2 ± 100 mV
at an ~60% Step Transient)
fSW (kHz) VIN (V) VOUT2 (V) L (µH) COUT1 (µF) RC (kΩ) CC (nF) CCP (pF) RTOP2 (kΩ) RBOT2 (kΩ) COUT2 (µF)
600 12 3.3 4.7 47 1.74 33 22 Short Open 10
12 2.5 3.3 44 1.65 22 22 37.4 118 10
12 1.8 3.3 57 2.15 22 22 100 121 10
12 1.3 2.2 47 1.74 22 22 100 64.9 10
12 1.1 1.8 47 1.74 10 22 100 49.9 10
5 3.3 1.5 44 1.65 33 22 Short Open 10
5 2.5 1.8 32 1.21 22 22 37.4 118 10
5 1.8 1.8 32 1.21 22 22 100 121 10
5 1.3 1.8 44 1.65 22 22 100 64.9 10
5 1.1 1.5 44 1.65 10 22 100 49.9 10
ADP5003 Data Sheet
Rev. A | Page 28 of 31
BUCK CONFIGURATIONS
INDEPENDENT
The buck and LDO regulators can operate independently of
each other (see Figure 50) to provide two voltage rails from a
single supply. In this way, the buck regulator can provide an
intermediate supply rail for the LDO regulator with a fixed
headroom voltage between the buck output voltage and the
LDO output voltage. The LDO regulator acts to filter the voltage
ripple and switching noise generated by the buck regulator for
noise sensitive supplies. Where additional filtering is required, a
second stage LC filter can be added between the buck output
and the LDO input. Because the regulators are independently
operated to provide a single voltage rail, the PSRR and efficiency
can be configured as required by the application by either
setting a lower headroom voltage for greater efficiency or a
higher headroom voltage for greater PSRR.
0
10
20
30
40
50
60
70
80
00.5 1.0 1.5 2.0 2.5 3.0
INDEP E NDE NT EFF ICI E NCY ( %)
LOAD CURRENT ( A)
ADAPT I V E HE ADROO M CONT ROL
INDEP E NDE NT, 150mV HE ADROO M
INDEP E NDE NT, 500mV HE ADROO M
15021-450
Figure 49. Efficiency vs. Load Current for
Different Operating Modes
ANALOG DE V ICES
RF TRANSCEIVE R,
HIGH SPEED
ADC/DAC, CLO CK,
ASIC/PROCESSOR
R
RT
294kΩ
RT
R
BOT2
64.9kΩ
R
TOP2
100kΩ
VOUT1
SW1
PGND1
VREG
PVINSYS
V
PVINSYS
: 12V
AGND1 AGND2
PVIN2
PVOUT2
VFB2P
EN1
VBUF
COMP1
REFOUT
EN2 VFB2N
VSET2
LOW NOISE
LDO ACTIVE
FILTER
3A
SYNC
VSET1
PVIN1
BUCK
REGULATOR
3A
V
PVIN1
: 12V
C
PVIN1
10µF
C
VREG_LDO
1µF
C
VBUF
0.1µF
C
VREG
1µF
R
TOP1
100kΩ
C
PVINSYS
10µF
R
BOT1
100kΩ
R
C
9.76kΩ
C
C
4.7nF
C
PVOUT1
44µF
C
PVIN2
10µF
C
PVOUT2
10µF
L1
3.3µH
SYSTEM PWRGD
VREG_LDO
C
REFOUT
0.22µF
V
PVOUT2
= 1.3V
V
PVOUT1
= 2.5V
15021-062
Figure 50. Independent Configuration (Dual Output)
Data Sheet ADP5003
Rev. A | Page 29 of 31
ADAPTIVE HEADROOM
The ADP5003 features a scheme to control the buck regulator
output voltage and thus the LDO headroom voltage to provide
better efficiency with the same noise performance of a standalone
LDO regulator. When the buck regulator uses the adaptive
headroom control configuration, the ADP5003 manages the
buck regulator output voltage vs. the LDO load current (see
Figure 25). The adaptive headroom control also optimizes the
LDO headroom when the remote sense feedback corrects any
output voltage drop due to additional filtering or high trace
impedance under high load conditions. The headroom profile
of the adaptive headroom control is set to deliver a consistent
PSRR across the load range while optimizing efficiency of the
overall system (see Figure 51). To enable adaptive headroom
control, connect VSET1 to VREG (see Figure 52).
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1k 10k 100k 1M 10M
LDO P S RR ( dB)
FREQUENCY (Hz)
LDO PSRR
VPVIN1 = 12V, VPVOUT2 = 0.9V
0.2V, 1A
0.28V, 1. 5A
0.35V, 2A
0.4V, 2. 5A
0.4V, 3A
15021-145
Figure 51. LDO PSRR vs. Frequency
L1
2.2µH
CC
2.2nF RC
1.74kΩ
RBOT2
64.9kΩ
ANALO G DEVICES
RF TRANSCEIVER,
HIGH SPE ED ADC/DAC,
CLO CK, ASIC/
PROCESSOR
RT
VOUT1
SW1
SW1
SW1
PGND1
PGND1
PGND1
VREG
PVINSYS
VPVINSYS: 12V
AGND1 AGND2
PVIN2
PVIN2
PVIN2
PVOUT2
PVOUT2
PVOUT2
VFB2P
EN1
VBUF
COMP1
REFOUT
EN2 VFB2N
VSET2
LOW NOISE
LDO ACTIVE
FILTER
3A
SYNC
VSET1
PVIN1
PVIN1
BUCK
REGULATOR
3A
VPVIN1: 12V
CVREG
1µF
CVBUF
0.1µF
CVREG_LDO
1µF
SYSTEM PWRGD
VREG_LDO
VVPOUT2 = 1.3V
VPVOUT1
(ADAPTIVE)
15021-061
RRT
294kΩ
RTOP2
100kΩ
CPVIN1
10µF
CPVINSYS
10µF
CPVOUT1
47µF
CPVIN2
10µF
CPVOUT2
10µF
CREFOUT
0.22µF
Figure 52. Adaptive Headroom Configuration
ADP5003 Data Sheet
Rev. A | Page 30 of 31
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is
particularly important for regulators with high switching
frequencies. To achieve high efficiency, proper regulation,
stability, and low noise, a well designed PCB layout is required.
Follow these guidelines when designing PCBs:
• Keep high current loops as short and wide as possible.
• Keep the input bypass capacitors close to the PVIN1,
PVIN2, and PVINSYS pins.
• Keep the inductor and output capacitor close to SW1
and PGND1.
• Route the VFB2P and VFB2N LDO sense traces side by
side connecting them each as close as possible to the point
of load. Keep them as short as possible and away from
noise sources.
• Place the frequency setting resistor close to the RT pin.
Keep AGND1 and PGND1 separate on the top layer of the
board. This separation avoids pollution of AGND1 with
switching noise. Do not connect PGND1 to the EPAD on
the top layer of the layout. Connect both AGND1 and
PGND1 to the board ground plane with vias. Ideally,
connect PGND1 to the plane at a point between the input
and output capacitors.
• Connect the negative terminal of CVBUF to the VFB2N pin.
15021-063
ADP5003
CVOUT1
22µF
25V/X5R
1206
CPVIN2
10µF
50V/X5R
1206
0201
0201
0201 0201
0201
0201
0402
0402
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
31
30
29
28
27
26
25
32
PVIN
PVOUT2
PVOUT1
13.2mm
18.7mm
L1
CPVINSYS
10µF
35V/X5R
0805
CPVIN1
10µF
50V/X5R
1206 CVREG
1µF
10V/X5R
0406
CC
CCP
RRT
RC
RBOT2
RTOP2
RBOT1
RTOP1
CREFOUT
0.22µF
10V/X5R
0402
CVBUF
0.1µF
10V/X5R
0402
CVREG_LDO
1µF
10V/X5R
0402
CPVOUT2
10µF
25V/X5R
0805
Figure 53. Example Outline Layout
Data Sheet ADP5003
Rev. A | Page 31 of 31
OUTLINE DIMENSIONS
3.25
3.10 SQ
2.95
0.80
0.75
0.70
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR 32
9
16
17
24
25
8
0.05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.50
0.40
0.30
0.20 M IN
10-19-2017-B
COM P LIANT T O JEDE C S TANDARDS M O-220-WHHD
PKG-003898
SEATING
PLANE
EXPOSED
PAD
SIDE VIEW
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP5003ACPZ-R7 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7
ADP5003CP-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15021-0-3/19(A)
