ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
- 1 -
GENERAL DESCRIP TION
T he AK43 46 is an 6-ch annel 24bit DAC operating off of a single +3.3V power supply. T he out put s are
single-ended, and it samples at rates from 8kHz to 192kHz. It uses AKM’s advanced multi-bit architecture
for the modulator to ach ieve a wide dy namic range while preserving linearity for improved THD+N
performanc e. T he output circuit includes a switche d-cap filter and a se con d-o rder an alog low pass filter,
minimizing the need for ext erna l filtering.
FEATURES
Samp ling R ate: 8kHz t o 192kHz
2 4-Bi t 8 times Digita l Fil ter with Slow Roll-O ff Opti on
DR, S/N: 104 dB
THD+N: -90dB
High Tolerance to C lock Ji t t er
Single Ended Output Buffer with Second Order Anal og LPF
Digital De- emphasis for 32, 44.1 & 48kHz sampling
Zero Detect Function
Channel Independent Digital Attenuator (Linear 256 steps)
3-wire Serial or I2C Con trol
I/ F format: MS B jus ti fied, LS B ju stified (16-, 20 -, 24 -b it), I2S, TDM
Master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 25 6fs or 38 4fs (Double Spee d Mode)
128fs or 192fs (Quad Speed Mode)
Power Supply: 2.7V to 3.6V
Ta = −20 ∼ 85°C (EF), −40 ∼ 85°C (VF)
Pa ckage: 30-pi n VS OP
SCF DAC DATT
DZF
LOUT1
SCF DAC DATT
ROUT1
SCF DAC DATT
LOUT2
SCF DAC DATT
ROUT2
SCF DAC DATT
LOUT3
SCF DAC DATT
ROUT3
Audio
I/F
Control
Register
AK4346
MCLK
LRCK
BICK
3-wire
or I2C
SDTI1
SDTI2
SDTI3
PCM
LPF
LPF
LPF
LPF
LPF
LPF
3.3V 192kHz 24-Bit 6-Channel DAC
AK4346
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Ordering Guide
AK4346EF -20
∼ +85°C 30pin VSOP
AK4346VF -40
∼ +85°C 30pin VSOP
AKD4346 Evaluation Board for AK4346
Pin Layo ut
6
5
4
3
2
1 MCLK
BICK
LRCK
SDTI1
RSTB
SMUTE/CSN/CAD0
7
DIF0/CDTI/SDA 8
DZF1
TDM0/DZF2
AVDD
AVSS
VCOM
LOUT1
ROUT1
P/S
AK4346
Top
View
10
9 SDTI2
SDTI3
TST1 11
DIF1 12
LOUT2
ROUT2
LOUT3
ROUT3
25
26
27
28
29
30
24
23
21
22
20
19
ACKS/CCLK/SCL
DEM0/CAD1 13
DVDD 14
TST3
TST2
18
17
DVSS 15 DEM1/I2C 16
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input
An e xternal TTL c lock should be input on this pi n.
2 BICK I Audio Serial Data Clock
3 SDTI 1 I DAC1 Audio Serial Data Input
4 LRCK I L/R Clock
5 RSTB I Reset Mode
When at “L”, the AK4346 is in reset mode.
The AK4346 must be reset on ce upon power-up.
SMUTE I Soft Mute i n parallel control m ode
“H”: Enable, “L”: Disabl e
CSN I Chip Select in serial 3-wire mode
6
CAD0 I Chip Address in serial I2C mod e
ACKS I Auto Setting Mode in pa ra llel control mode
“L”: Manual Settin g Mode, “H”: Auto Set tin g Mod e
CCLK I Control Data Clock in serial 3-wire control mode
7
SCL Con tr ol Data Clock in serial I2C con trol mode
DIF0 I Audio Data Interface Format in parallel con trol mode
CDTI I Control Data Input in serial 3-wire control mode
8
SDA I/O Control Data in serial I2C control mode
9 SDTI 2 I DAC2 Audio Serial Data Input
10 SDTI 3 I DAC3 Audio Serial Data Input
11 TST1 I Test pin – connect to ground.
12 DIF1 I Audio Data Interface Format
CAD1 I Chip Address in seri al control mode 13 DEM0 I De- emphasis Filter Enabl e
14 DVDD Digita l Power Supply, +2.7∼+3. 6V
15 DVSS Digital Ground
I2C I
µP I/F Mode Select in serial control mod e
“L”: 3-wire Ser i a l , “H”: I2C Bus
16
DEM1 I De-emphasis Filter Enable in parallel control mode
17 TST2 - Test pin – l eave thi s pin floating.
18 TST3 - Test pin – l eave thi s pin floating.
19 ROUT3 O DAC3 Right Channel Analog Output
20 LOUT3 O DAC 3 Left Channel Anal og Ou tp ut
21 ROUT2 O DAC2 Right Channel Analog Output
22 LOUT2 O DAC 2 Left Channel Anal og Ou tp ut
23 P/S I Parallel/Serial Control Mode Select (Internal pull-up pin)
“L”: Serial cont rol mode, “H”: Parallel control mode
24 ROUT1 O DAC1 Right Channel Analog Output
25 LOUT1 O DAC 1 Left Channel Anal og Ou tp ut
26 VCOM O Common Voltage, AVDD/2
Normal ly connected to AVSS with a 0.1µF ce ramic c apacitor in parallel with a
10µF electrolytic cap.
27 AVSS - Analog Ground
28 AVDD - Analog Power Suppl y, +2.7∼+3.6V
TDM0 I TDM I/F Format Mode in parallel control mode (Internal pull-down pin)
“L”: Normal mode, “H”: TDM 256 mode
29
DZF2 O Data Zero Input Detect in serial control mode
30 DZF1 O Data Zero Input Detect
Note: All input pin s except P/S an d TDM0 pi ns sh ould not be left floating .
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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H a ndl ing of U nused P ins
Unused I/O pin s should be r esolved as shown in this table.
Classificatio
n Pin Name Setting
Analog LOUT3-1, ROUT3-1 Leave open.
DZF2-1 Leave open.
SDTI3-1
SMUTE (Parallel control mode) Con n ect to DVSS.
Digital
DEM0, DIF1 (S erial control mode) Conn ect to DVDD or DVSS.
ABSOLU T E MA XIMU M RATIN GS
(AVSS, DVSS=0V; Note 1)
Parameter Symbol Min Max Units
Power Su p p l i e s
Analog
Digital
|AVSS-DVSS| (Note 2)
AVDD
DVDD
∆GND
-0.3
-0.3
-
4.6
4.6
0.3
V
V
V
Input Curr ent (any pins except for supplies) IIN - ±10 mA
Analog Input Voltage VINA -0.3 AVDD+0.3 V
Digita l Input Volt age VIND -0.3 DVDD+0.3 V
AK4346EF Ta -20 85
°C
Ambi ent Operating Tempera ture AK4346VF Ta -40 85
°C
Storage Te mpe rature Tstg -65 150 °C
Note 1. All voltag es wi th respect to ground.
Note 2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation a t or beyond these limits may result in permanent damage to the device.
Nor mal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter Symbol Min Typ Max Units
Power Su p p l i e s
(Note 1) Analog
Digital AVDD
DVDD 2.7
2.7 3.3
3.3 3.6
3.6 V
V
Note 3 . The power u p sequence between AVDD and DVDD is not critical.
*AKM a ssumes no responsibility for the usage beyond the condition s in this data sheet .
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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ANAL O G CHARACTE RIS T ICS
(Ta=25°C; AVDD, DVDD=3.3V; fs=4 4.1kHz; BI CK=64fs; Sig nal Freq uency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)
Parameter Min Typ Max Units
Resolution 24 Bits
Dynamic Characteristics (Note 4)
Fs=44.1kHz
BW=20kHz 0dBFS
-60dBFS -90
-40 -80
- dB
dB
fs=96kHz
BW=40kHz 0dBFS
-60dBFS -86
-37 -
- dB
dB
THD+N
fs=192kHz
BW=40kHz 0dBFS
-60dBFS -86
-37 -
- dB
dB
Dynamic Range (-60dBFS with A-weighted) (Note 5) 96 104 dB
S/N (A-weighted) (Note 6) 96 104 dB
Interchannel Isolation (1kHz) 80 100 dB
Interch annel Gain Mismatc h 0.2 0.5 dB
DC Accuracy
Gain Drift 100 - ppm/°C
Output Voltage (Note 7) 2.09 2.24 2.39 Vpp
Load Resistance (Note 8) 5 kΩ
Load Capacitance 25 pF
Power Supplies
Power Supply Current (AVDD+DVDD)
Nor mal Operation (RSTB pin = “H”, fs≤96kHz)
Normal Operation (RSTB pin = “H”, fs=192kHz)
Reset Mode (RSTB pin = “L”) (Note 9)
37
44
33
60
66
133
mA
mA
µA
Note 4. Measured by Audio Precision System Two. Refer to the evaluation board manual.
Note 5. 100dB when usin g 16bit data.
Note 6. S/N does not depend on input data resolution.
Note 7. Full scale volt age (0dB). Out put volta ge scales with the voltage of AVDD pi n. AOUT (typ. @0dB) =
2.24Vpp×AVDD/3.3
Note 8. For AC-l oad.
Note 9 P/S pin i s tied to DVDD an d t he other al l digita l input pins including clock pins (MCLK, BICK, LRCK) are tied
t o DVSS.
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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SHARP RO LL-OF F FILTER CHARACTE RIS T ICS
(Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3. 6V ; fs = 44 . 1k Hz; DE M = OFF ; SL OW = “0” )
Parameter Symbol Min Typ Max Units
Digital filter
Passband ±0.05dB (Note 10)
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 10) SB 24.1 kHz
Passband Ripple PR ± 0.02 dB
Stopband Attenuation SA 54 dB
Group Delay (Note 11) GD - 19.3 - 1/fs
Di g i t a l Fi lte r + SCF
Fr equency Response
20.0kHz
40.0kHz
80.0kHz
Fs=44.1kHz
Fs=96kHz
Fs=192kHz
FR
FR
FR
-
-
-
+ 0.06/-0.10
+ 0.06/-0.13
+ 0.06/-0.51
-
-
-
dB
dB
dB
Note 10. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs
(@±0.05dB), SB=0.546×fs.
Note 11. Calculated delay time caused by the digital filter. Thi s time is measured from wh en th e serial dat a of both
channels is in the input register to the output of the analog signal.
SL OW ROLL-OFF FILTER CHA RACTERISTI CS
(Ta = 25°C; AVDD, DVDD = 2.7~3 .6V; fs = 44.1kHz; DEM = OFF; SLOW = “1” )
Parameter Symbol Min Typ Max Units
Digital Filter
Passband ±0.04dB (Note 12)
-3.0dB PB
0
-
18.2 8.1
- kHz
kHz
Stopband (Note 12) SB 39.2 kHz
Passband Ripple PR ± 0. 005 dB
Stopband Attenuation SA 72 dB
Group Delay (Note 11) GD - 19.3 - 1/fs
Di g i t a l Fi lte r + SCF
Fr equency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
+0.1/-4.3
+0.1/-3.3
+0.1/-3.7
-
-
-
dB
dB
dB
No t e 12. The pass b and a nd stopband f requ e ncie s s c a le with fs. Fo r e xamp le, PB = 0.185×f s (@±0.04 dB), SB = 0.888×f s.
DC CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3. 6V )
Parameter Symbol Min Typ Max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 70%DVDD -
- -
30%DVDD V
V
High-Level Output Voltage (Iout = -80µA)
Low-Level Output Voltage (Iout = 80µA) VOH
VOL DVDD-0.4
- - -
0.4 V
V
Input Leakage Current (Note 13) Iin - - ± 10 µA
Note 13. P/S pin ha s an interna l pull-up device and TDM0 pin has an in ternal pull-down device, nominally 100kΩ.
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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SWIT CHING CHARA CT ERIS T ICS
(Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V; CL = 20pF)
Parameter Symbol Min Typ Max Units
Master Clock Fre quency
Duty Cycle fCLK
dCLK 2.048
40 11.2896
36.864
60 MHz
%
LRCK Fr eq ue nc y
Normal Mode (TDM 0= “0”, TDM1= “0”)
Nor ma l Speed Mode
Double Speed Mode
Quad Speed Mode
Dut y Cycle
fsn
fsd
fsq
Duty
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
TDM256 mode (TDM0= “1”, TDM1= “0”)
Norma l Speed Mode
High time
Low time
fsn
tLRH
tLRL
8
1/256fs
1/256fs
48
kHz
ns
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
Normal Speed Mode
Double Spe ed Mode
High time
Low time
fsn
fsd
tLRH
tLRL
8
60
1/128fs
1/128fs
48
96
kHz
kHz
ns
ns
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 14)
LRCK Edge to BICK “↑” (Note 14)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
81
30
30
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing (I2C Bus mode):
SCL Clock Frequen cy
Bus Free Ti me Between Transmissi ons
Start Condition Hold Time (prior to fi rst clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Star t Condition
SDA Hold Time from SCL Falling (Note 15)
SDA Setup Time from SCL Rising
Rise Time of Both SD A and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capaciti ve load on bus
fSCL
tBUF
tHD:STA
tLO W
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
pF
Reset Timing
RSTB Pulse Width (Note 16)
tRST
150
ns
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 16. The AK4346 can be reset by bringing RSTB pin = “L”.
Note 17. I2C is a reg istered trademark of Philips Semiconductors.
Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Audio Serial Interface Timing
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRI TE Comma nd Input Timi ng
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tHIGH
SCL
SDA VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Sto
p
Start Start Sto
p
tSU:STO
VIL
VIH
VIL
tSP
I2C Bus mode Timing
tRST
VIL
RSTB
Reset Ti ming
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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OPER A T ION OVERVI EW
Syste m Clock
The external clocks required to operate the AK4346 are MCLK, LRCK and BICK. The master clock (MCLK) shou ld be
sy nchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma m odulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit = “0”:
Register 00H), the sampling speed is set by DF S0-1 bits (Table 1). The f requency o f MCLK at each sampling speed is set
automatically. (Table 2~Table 4) In Auto Setting Mode (ACKS bit = “1”: Defa ult), the MCLK frequency is detected
automatically (Table 5 ), and the inte rnal master c lock is se t to the appro priate f requency (Table 6) and it is not necessary
to set DFS0-1.
In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = “L”, the AK4346
operates by normal speed mode. When ACKS pin = “H”, auto setting mode is enabled. The parallel control mode does not
support 128fs and 192fs of double speed mode.
All external clocks (MCLK, BICK and LRCK) should be present whenever the AK4346 is in normal operation mode
(RSTB pin = “H”) . If th ese clocks are not pr ovided, the AK4346 may dra w excess curr ent a nd will not operat e pr operl y
bec ause it u tilizes these clocks fo r internal dy namic refresh of registers. The AK4346 should b e reset b y setting RSTB pin
= “L” aft er threse clocks are provided. If the ext ern al clocks are not present, the AK4346 should be in the power-down
mode (RSTB pin = ”L”). After exiting reset (RSTB = “↑”) at power-up, the AK4346 is in the power-down mode until
MCLK is input.
DFS1 DFS0 Sampling Rate (fs)
0 0 Normal Speed Mode 8kHz ~48kHz Default
0 1 Double Speed Mode 60kHz~96kHz
1 0 Quad Speed Mode 120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 1152fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Man ual Setting Mode )
LRCK MCLK BICK
fs 128fs 192fs 256fs 384fs 64fs
88.2kHz 106896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 3. System Clock Example (Double Speed Mode @M anual Setting Mode)
LRCK MCLK BICK
fs 128fs 192fs 64fs
176.4kHz 22.5792MHz 33.8688MHz 106896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Ta bl e 4. Syst em Cl ock Ex a m ple ( Qu a d Sp eed Mode @M a n ual Setting Mode)
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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MCLK Sampling Speed
1152fs Norma l (fs≤32kHz)
512fs 768fs Normal
256fs 384fs Double
128fs 192fs Quad
T able 5 . Sa mpling Speed (Au t o Setting Mode)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - - Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - -
Quad
Table 6. System Clock Example (Auto Setting Mode)
ASAHI KASEI [AK4346]
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Audio Serial Interface Format
In parallel con trol mode, the DIF0 -1 and TDM0 pins can select eight serial da ta modes (Tabl e 7). The regist er value of
DIF0-1 and TDM0bits are ignored. In serial control mode, the DIF0-2 and TDM0-1 bits shown in Table 8 can select 11
seria l data modes. The default format is Mode 2 (24-bit MSB justified format in normal mode). The setting of DIF1 pin
is ignored. In all modes the audio data is MSB-fir st, 2’s complement for mat and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20-bit MSB justified formats by z eroing t he unused LSB’s.
In parallel control mode, when the TDM0 pin = “H”, the audio interface for mat is TDM 256 mode (Table 7). The audio
data of all DACs (six chan nels) i s in put to the SDTI1 pin. T he input data to SDTI2-3 pin s is ignor ed. BICK sh oul d be
fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is MSB-first, 2’s complement
format. The input data to SDTI1 pin is latched on the rising edge of BICK.
In serial control mode, when the TDM0 bit = “1” and the TDM1 bit = “0”, t he audio interface format is TDM256 mode
(Table 8) , a nd th e audio data of all DACs (six ch ann els) is in put to th e SDTI1 pin . Th e input data to SDTI2-3 pin s is
ignor ed. BICK should be fixed to 256fs. “H” time an d “L” t ime of LRC K sh ould be at l east 1/256fs. Th e audio data is
MS B -first, 2’s c omple me nt format. The i nput data to SDTI1 pin is latche d on the ris ing e dge o f BI CK. In TD M128 mo de
(TDM0 bit = “1” and TDM1 bit = “1”, Table 8), the audio data of DACs (four channels; L1, R1, L2, R2) is input to the
S DTI1 pi n. The o ther two d ata (L3, R 3) is input to the SD TI2 pin. The i nput data to SD T I3 p ins is igno re d. BI CK s hou ld
be fixed to 128fs. The audio data is MSB-f irst, 2’s co mpl eme nt f o rmat. The input data to S DT I1-2 pins is latche d o n the
rising edge of BICK.
Mode TDM0 DIF1 DIF0 SDTI Format LRCK BICK Figure
0 L L L 16 -bit LSB Justified H/L ≥32fs Figur e 1
1 L L H 20-bit LSB Justified H/L ≥40fs Figur e 2
2 L H L 24-bit MSB Justified H/L
≥48fs Figur e 3
Normal
3 L H H 24-bit I2S Comp atible L/H ≥48fs Figur e 4
H L L N/A
H L H N/A
5 H H L 24-bit MSB Justified
↑ 256fs Figure 5
TDM256
6 H H H 24-bit I2S Compatible ↓ 256fs Figure 6
Table 7. Audio Data Formats (Parallel control mode)
Mode TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK BICK Figure
0 0 0 0 0 0 16-bit LSB Justified H/L ≥32fs Figure 1
1 0 0 0 0 1 20-bit LSB Justified H/L ≥40fs Figure 2
2 0 0 0 1 0 24-bit MSB Justified H/L ≥48fs Figur e 3
3 0 0 0 1 1 24-bit I2S Compa tible L/H ≥48fs Fig ure 4
Nor mal
4 0 0 1 0 0 24-bit LSB Justified H/L ≥48fs Figure 2
0 1 0 0 0 N/A
0 1 0 0 1 N/A
5 0 1 0 1 0 24-bit MSB Justified ↑ 256fs Figure 5
6 0 1 0 1 1 24-bit I2S Compat ible ↓ 256fs Figure 6
TDM256
7 0 1 1 0 0 24-bit LSB Justified ↑ 256fs Figure 7
1 1 0 0 0 N/A
1 1 0 0 1 N/A
8 1 1 0 1 0 24-bit MSB Justified ↑ 128fs Figure 8
9 1 1 0 1 1 24-bit I2S Compat ible ↓ 128fs Figure 9
TDM128
10 1 1 1 0 0 24-bit LSB Justified ↑ 128fs Figure 10
Table 8. Audio Data For m ats (Serial control mode, Default: Mode 2)
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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SDTI
BICK
LRCK
SDTI 15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3 2 1 0 15 14
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mo de 0 D o n’t care Don’t care
15:MSB, 0:LSB
M ode 0 1514 6543210
Lch Data Rch Data
Figure 1. Mode 0 T iming
SDTI
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
M ode 1 Don’t care Don’t care
19:MSB, 0:LSB
SDTI
Mode 4 23:MSB, 0:LSB
20 19 0 20 19 0Don’t care Don’t care22 21 22 21
Lch D ata Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timing
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0Don’t care
23 2223
Figure 3. Mode 2 T iming
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care23
Lch Data Rch Data
23 25 322423 25
22 1 0 Don’t care23 23
Figure 4. Mode 3 T iming
LRCK
BICK(256fs)
SDTI1(i)
256 BICK
22 0
L1
32 BI CK
22 0
R1
32 BICK
22 0
L2
32 BI CK
22 0
R2
32 BICK
22 0
L3
32 BICK
22 0
R3
32 BICK 32 BICK 32 BICK
22 23 23 23 23 23 23 23
Figure 5. Mode 5 T iming
LRCK
BICK(256fs)
SDTI1(i)
256 BICK
23 0
L1
32 BI CK
23 0
R1
32 BICK
23 0
L2
32 BICK
23 0
R2
32 BICK
23 0
L3
32 BICK
23 0
R3
32 BICK 32 BI CK 32 BICK
23
Figure 6. Mode 6 T iming
LRCK
BICK(256fs)
SDTI1(i)
256 BICK
22 0
L1
32 BI CK
22 0
R1
32 BICK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BICK
22 0
R3
32 BICK 32 BI CK 32 BICK
23 23 23 23 23 23 23
Figure 7. Mode 7 T iming
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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LRCK
BICK(128fs)
128 BICK
L1
32 BICK R1
32 BICK
L2
32 BICK R2
32 BICK
L3
32 BICK R3
32 BICK 32 BICK 32 BICK
SDTI1(i) 22 0 22 022 022 0 23 23 23 23 22 23
SDTI2(i) 22 0 22 0
23 23 22 23
Figure 8. Mode 8 T iming
LRCK
BICK(128fs)
128 BICK
L1
32 BICK R1
32 BICK
L2
32 BICK R2
32 BICK
L3
32 BICK R3
32 BICK 32 BICK 32 BICK
SDTI1(i) 22 0 22 022 022 0 23 23 23 23 23
SDTI2(i) 22 0 22 0
23 23 23
Figure 9. Mode 9 T iming
LRCK
BICK(128fs)
128 BICK
L1
32 BICK R1
32 BICK
L2
32 BICK R2
32 BICK
L3
32 BICK R3
32 BICK 32 BICK 32 BICK
SDTI1(i) 22 022 022 022 0 23 23 23 23 19
SDTI2(i) 22 022 0
23 23 19
Fi gure 10. Mode 10 Timin g
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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De-emphasis Filter
A digital de-emphasis filter i s available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs). Th e dig it a l de- emph a si s
filter is always of f w hen the AK4346 is operated in double o r quad speed modes. In serial control mode, the DEM0-1 bits
are va lid for the DAC enabl ed by the DEMA-C bits. In parallel control mode, the DEM0-1 pins are valid.
DEM1 DEM0 Mode
0 0 44.1kHz
0 1 OFF
1 0 48kHz
1 1 32kHz
Table 9. De-emphasis Filter Cont rol (Normal Speed Mode)
Output Volume
The AK4 346 include s c hannel independe nt digital vo l ume c o ntrols (ATT) w it h 256 linear step s , includi ng MU TE. The
volume c o ntro ls are in front o f the D AC and can attenuate the input data f rom 0dB to –48 dB, and mute. When changing
levels, transitions are executed via soft chan ges; thus no switching noi se occurs during th ese transitions. The tr ansition
time of 1 level an d all 256 levels is shown in Table 10. The attenuation level is calculated by ATT = 20 log10
(ATT_DATA / 255) [dB] and MUTE at ATT _DATA = “0”.
Tra n sit ion Time
Samplin g Speed 1 Level 255 to 0
Normal Speed Mode 4LRCK 1020LRCK
Double Speed Mode 8LRCK 2040LRCK
Quad Speed Mode 16LRCK 4080LRC K
Table 10. ATT Transition time
Zero Detection
Whe n the input data at all channels are c ontinuous ly ze ros f or 8192 L RCK cycles , the AK434 6 has a Ze ro De tect func tion
detail ed in Tabl e 11 . The D ZF pin immediate ly g oes to “L ” if the input data fo r each channel is not zero aft er the DZ F pin
is “H ”. If the RS TN bit is “0”, the DZF pin goes to “H”. The DZF pin goes to “L ” after 4 to 5LRCK cycles if the input data
of each channel is not zero after the RSTN b it returns to “1”. The Zero Detect function can be disabled by the DZFE bit.
In this case, bo th DZF pins are always “ L”. When one of the PW1-3 bits is set to “0”, the input data of the DAC fo r which
the PW b it is se t to “0” sho uld b e zero in o rder to e nable zero dete c tio n of the o ther channels. When all PW1-3 b its are se t
to “ 0”, both DZF p ins are f ixe d to “ L ”. The DZ FB bit can inve rt the po larity o f the DZF p in. In parallel control mode , the
zero detect function is disabled and the DZF1 pin is fixed to “L”.
DZF Pin Operations
DZF1 AND’ed output of zero detection flag of each cha nnel set to “1” in 0C H register
DZF2 AND’ed outp ut of zero detection flag of each ch annel set to “1” in 0DH register
Ta bl e 11 . DZF pi ns O peration
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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S oft Mute O pe r ation
So ft mute operatio n is perf o rmed in the digital domain. W hen the SMUTE b it goes to “1”, the ou tput signal is attenuated
by -∞ during th e ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit is
returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during the
ATT_DATA×ATT tr ansition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the
at tenuat i on is di scont i n ued an d retur n ed t o ATT l evel by th e sa m e cycl e. The soft m ut e i s effecti ve when cha ngin g t h e
sig nal source wit hout stopping the signal tra nsmission.
SMUTE
Attenuation
DZF pin
ATT Level
-∞
AOUT
8192/fs
GD GD
(1)
(2)
(3)
(4)
(1)
Notes:
(1) ATT_DATA×ATT transition time (Table 10). F o r exa mple, in No rmal S peed Mo de , this time is 1020L R CK cy c les
(1020/fs) at AT T_DATA=255.
(2) Th e ana log output cor responding to the digital input has a group delay, GD.
(3) If the so ft mu te is canc elled before attenuating to -∞ after starting the op eration, the attenuation is disco ntinued and
ret urned to ATT l evel by t h e sam e cycle.
(4) When the input data at e ach channel is c ontinuou sly zero f o r 8192 LR CK c y cle s, the DZ F pin of e ach channel go es
to “H” . Th e DZF pin immediately goes t o “L” if in put data a r e not zero after goin g DZF “H”. In pa r allel con tr ol
mode, the DZF pin is fi xed to “L” regardless of the state of SMUTE pin.
Fi gure 11. Soft M ut e and Zero Detection (DZFB bit = “0”)
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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System Reset
Th e AK4346 should be reset once by bringin g RSTB pi n = ”L” upon power-up. Th e AK4346 is powered up an d the
internal timing starts clo cking by LRC K “↑” after exiting reset and power down state by MCLK. The AK4346 is in the
power-down mode un til MCLK an d LRCK are input.
Power ON/OFF timing
All DAC s a r e p la ced in th e p ower-d own m ode by brin gi n g RST B pin “L ” an d t h e r egi ster s a r e i nitia lized. The analog
outputs go t o V COM. Since some clic k noise occurs at the edge of the RSTB signal, the analog outp ut should be muted
externally if the click noise influences system application.
Each DAC can be powered down by setting each power-down bit (PW1-3 bits) to “0”. In this case, the registers are not
initi a l iz ed a nd t h e corresp on di n g a n a l og out pu ts g o t o VCOM. S ince some cli ck noise occur s a t th e edge of the RST B
signal , the analog output should be muted exter nal ly if th e click noise influences system ap plication.
RSTB pin
Power
Reset
Normal Operation
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute Mute ON
(5)
DZF1/DZF2
Don’t care
“0”data
GD
(1)
(3)
(4)
(6)
GD
(3)
Mute ON
“0”data
Don’t care
Internal
State
(2)
(2)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD) .
(2) Analog out puts are VCOM at the power-d own mode .
(3) Click noise occurs at the edge of RSTB signal. This noise is output even if “0” data is i nput.
(4) The ext ernal clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTB pin = “L”).
(5 ) Mute the analog ou tp ut externally if the click noise (3) influences the system application.
The timing ex ample i s shown in this figure.
(6) DZF pins are “L” in th e power-down mode (RSTB pin = “L”). (DZFB bit = “0”)
Figure 12. Power-down/up Sequence Example
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Res e t Func ti on (RST N bit)
When the RSTN bit = “0”, the interna l circuit of the DAC is powered down but the registers are not initialized. The
analog o utputs go to VCOM voltage and the DZF pins go to “H” when the DZFB bit = “0”. Figure 13 show s the example
of reset by the RSTN bi t. W hen the RSTN bit = “0”, click noise is decrea sed at no clock state.
Internal
State
RSTN bit
Di gital Bloc k Powe r-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZF
(3) (1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD) .
(2) Analog out puts go to VC OM volt age .
(3) Small click noise o cc urs at the edges(“ ↑ ↓”) of the interna l timi ng of RSTN bit. This noise is output even if “0”
data is input.
(4) The external cl ocks (MCLK, BICK and L RCK) can be stopped in the reset mode (RSTN bit = “0”).
(5 ) DZF pi ns go to “H” when the RSTN bit becom es “0”, and g o to “L” at 2 /fs after RSTN bit becomes “1”.
(6) T here is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, a nd 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”. Figure 13. Reset S equence Example (DZFB bit = “0”)
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Register Control Interface
The AK4 346 c o ntrols its f unc t ions via regis te rs. Tw o t ypes o f control mode can be used to write to the internal reg iste rs.
In I2C-bus mod e, the ch ip address i s determined by the state of the CAD0-1 pins. In 3 -wire mode, the ch ip address can
be selected by the stat e of the CAD1 pin. RSTB pin = “L” initializes th e registers to t heir d efault values. Writing “0” to
the RSTN bit r esets the internal timing circuit, but the registers a re not initialized.
* The AK4346 does not support the read command.
* W hen the A K 4346 is in the po wer do w n mode (R STB b it = “L”) o r the MCL K is not prov ide d , w riting to c o ntro l
registers is pr ohibited.
* Wh en th e state of P/S pi n is ch anged, th e AK4346 should be r eset by RSTB bit = “L” .
* In seri al control mode, the setting of para llel pins is invalid.
Function Parallel control mode Serial control mode
Double sampling mode at 128/192fs - O
De-emphasis O O
SMUTE O O
Zero Detection - O
24-bit LSB just ified format - O
TDM256 mode O O
TDM128 mode - O
Table 12. Function Table (O: Supported, -: Not supported)
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Internal registe rs may b e written to via the 3-w ire µP interface pins (CSN, CCL K and CDTI). The data on this interface
consists of Chip Addr ess (2-bits, C1/0; C1=CAD1 and C0 is fixed to “1”), Read/Write (1-bit; fixed to “1”, Write only),
Register Address (MSB first, 5-bits) and Co ntrol Data (MSB first, 8-bits). The AK4346 latches the data on the rising edge
of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by the rising edge of CSN. The
clock speed of CCLK is 5MHz (max).
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7
A
1
A
2
A3
A4
R/WC0
A0
D0D1D2D3
C1-C0: Chip Address (C1=CAD1, C0=“1”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 14. Control I/F Timing
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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(2) I2C-bus C ontrol Mode (I2C pin = “H”)
The AK4346 suppor ts fa st-mode I2C-bus system (ma x: 400 kHz) .
Figure 15 shows the data tr ansfer sequence at the I2C-bus mod e. All commands are p receded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direct ion
bit (R/W) (Figure 16). The most significant five bits of the slave address are fixed as “00100”. The next two bits are
CA D 1 and CA D 0 (c hip addres s b its). The bi ts identif y the sp e c ifi c de v i c e on the b us. The hard-w ired input pins (CAD1
and CAD0 pins) set them. If the slave address match that of th e AK4346 and R/W bit is “0”, the AK4346 generates t he
ac knowledge and the write operation is e xe c u te d. If R/ W bit is “ 1”, the A K4346 generates the not acknowledge s ince the
AK4346 can be only a slave-receiver. The master must generat e the acknowledge-related clock pulse and rel ease the
SDA line (HIGH) during the acknowledge clock pulse (Figure 20).
Th e secon d byte cons ists of th e ad dr ess for cont rol r egi ster s of th e AK434 6. T he f or ma t is MSB fir st, an d t hose most
signif icant 3-bits are fixed to zeros (Figure 17). Those data after the second by te co ntain contro l data. The f ormat is MSB
first, 8bits (Figure 18). The AK4346 generates an acknowledge after each byte has been received. A data transfer is
alw ay s terminated b y a STOP conditio n generated b y the master. A LO W to HIGH transition on the SD A line while SCL
is HIGH defines a STOP condition (Figur e 19).
The AK4346 is capable of more th an one byte write operati on by one sequence. After receip t of the thir d byte, the
AK 4346 generates an ackno wle dg e, and awaits the next data again. The master can transmit more than o ne byte instead
of termina ting the write cycle after the first data byte is transferred . After the receip t of each data, the internal 5bits
address co unter is incremented by one, and the next data is taken into next address automatically . If the addresses exceed
1FH prior to genera ting the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten .
The data on the SDA line must be stable during the HIGH peri od of the clock. The HIGH or LOW state of the data line
can only change when the clock sig nal on the SCL line is LOW (Fi gure 21) except for the START and the STOP
condition.
SDA
S
T
A
R
T
A
C
K
A
C
K
SSlave
Address
A
C
K
Sub
Address(n) Data(n) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W
A
C
K
Figure 15. Data tra nsfer sequence at the I2C -bus mode
0 0 1 0 0 CAD1 CAD0 R/W
(Those CAD1 / 0 sh oul d ma tch wit h CAD1 /0 pins)
Figure 16. The first byte
0 0 0 A4 A3 A2 A1 A0
Fi gure 1 7. Th e second byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 18. Byte st ructure after the second byte
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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SCL
SDA
sto p conditionstart condition
SP
Figure 19. START and STOP conditions
SCL FROM
MASTER
acknowled
g
e
DATA
OUTPUT BY
MASTER
DATA
OUTPUT BY
SLAVE(AK4359)
1 98
START
CONDITION
not acknowledge
clock p ulse for
acknowledgement
S
2
Figure 20. Acknowledge on the I2C-bus
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figu re 21. Bit transfer on the I2C-bus
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Regi ster Ma p
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 PW1 RSTN
01H Control 2 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
02H Control 3 0 PW3 PW2 0 0 DZFB PW1 0
03H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04 H ROUT 1 ATT Con tr ol AT T 7 AT T 6 AT T5 A TT4 ATT 3 AT T2 ATT1 ATT0
05H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06 H ROUT 2 ATT Con tr ol AT T 7 AT T 6 AT T5 A TT4 ATT 3 AT T2 ATT1 ATT0
07H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08 H ROUT 3 ATT Con tr ol AT T 7 AT T 6 AT T5 A TT4 ATT 3 AT T2 ATT1 ATT0
09H Reserved 1 1 1 1 1 1 1 1
0AH Reserved 1 1 1 1 1 1 1 1
0BH Invert Output Signal INVL1 INVR1 INVL2 INVR2 INVL3 INVR3 0 0
0CH DZF1 Control L1 R1 L2 R2 L3 R3 0 0
0DH DZF2 Control L1 R1 L2 R2 L3 R3 0 0
0EH DEM Control 0 0 0 0 DEMA DEMB DEMC 0
Note: For addresses from 0FH to 1FH, data must not be written .
When RSTB pin goes to “L”, the registers are initialized to their d efault values.
When RSTN bi t goes to “0”, the only int erna l tim i ng i s reset, and th e r egi sters ar e not in itia li zed to their d efault
values. All data can be writt en to th e r egisters even if PW1-3 bits or RSTN bit is “0” .
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 PW1 RSTN
Default 1 0 0 0 1 0 1 1
RSTN: Internal timing reset
0: Reset. All DZF pins go to “H” and any regist ers are not initialized.
1: Normal operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
This bit is duplicated into D1 of 02H.
DIF2-0: Audio da ta interface modes (See T abl e 7, Table 8)
Initial: “010”, Mode 2
TDM0-1: TDM Mode Select
Mode TDM1 TDM0 BICK SDTI Sampling Speed
Normal 0 0 32fs∼ 1-3 Nor m al , Double, Qu a d Speed
TDM256 0 1 256fs fixed 1 Normal Speed
TDM128 1 1 128fs fixed 1-2 Normal , Double Speed
AC KS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: E nable, Auto Setting Mode
Master clock frequency is detected automatically w hen the ACKS bit = “1”. In this case, the setting of
DFS1-0 bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode.
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
Default 0 0
0 0 0 0 1 0
SMUTE: Soft Mute Enable
0: Normal oper ation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (See Table 9)
Initi al: “01”, OFF
DFS 1-0: Sampling speed control (See Table 1)
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
SLO W: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
Adr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Speed & Power Down
Control 0 PW3 PW2 0 0 DZFB PW1 0
Default 0 1 1 0 0 0 1 0
PW1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
This bit is duplicated into D1 of 00H.
DZFB: In verting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
PW3-2: Power-down control (0: Power-down, 1: Power-up)
PW2: Power down control of DAC2
PW3: Power down control of DAC3
All sections are powered-down by PW1=PW2=PW3=0.
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H LOUT1 ATT Control ATT7 ATT 6 ATT5 ATT4 AT T3 ATT2 ATT1 ATT0
04H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H LOUT2 ATT Control ATT7 ATT 6 ATT5 ATT4 AT T3 ATT2 ATT1 ATT0
06H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H LOUT3 ATT Control ATT7 ATT 6 ATT5 ATT4 AT T3 ATT2 ATT1 ATT0
08H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Default 1 1 1 1 1 1 1 1
ATT = 20 log10 (ATT_DAT A / 255 ) [dB]
00H: Mute
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0BH Invert Output Signal INVL1 INVR1 INVL2 INVR2 INVL3 INVR3 0 0
Default 0 0 0 0 0 0 0 0
IN VL1-3 , I NVR1-3: Inver t ing Outp ut Pol a r i ty
0: Normal Output
1: Inver ted Output
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0CH DZF1 Control L1 R1 L2 R2 L3 R3 0 0
0DH DZF2 Control L1 R1 L2 R2 L3 R3 0 0
Default 0 0 0 0 0 0 0 0
L1-3, R1-3: Zero Detect Flag Enable for DZF1/2 pins
0: Disable
1: Enable
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0EH DEM Control 0 0 0 0 DEMA DEMB DEMC 0
Default 0 0 0 0 0 0 0 0
DEMA-C : De-em ph a sis Enable of DAC1 /2 /3
0: Disable
1: Enable
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
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SYST EM D ESIG N
Figure 22 and 23 sh ows the system connection diagra m. An evaluation board (AKD4346) is availa ble which
demonstrates application circuits, the optimum layout, power supply arrangemen ts and measurement results.
BICK
2
SDTI1
3
LRCK
4
RSTB
5
SMUTE
6
ACKS 7
DIF0 8
SDTI2
9
SDTI3 10
TST1 11
DIF1
12
DEM0
13
TDM0 29
AVDD 28
AVSS 27
VCOM 26
LOUT1 25
ROUT1 24
P/S 23
LOUT2 22
ROUT2 21
LOUT3 20
ROUT3 19
TST3 18
Micro-
controller
0.1u
AK4346
Mute Signal
14
15
17
16
DVDD
DVSS
TST2
DEM1
R1ch Out
L1ch Out
Analog Ground Digital Ground
L2ch Out
R2ch Out
Master Clock
fs
24bit Audio Data
64fs
Reset
24bit Audio Data
24bit Audio Data +
10u
+
0.1u
10u
Digital 3.3V
MCLK
1 DZF1 30
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
L3ch Out
R3ch Out
0.1u +
10u
Micro-
controller
Micro-c ontroller
Analog 3.3V
TDM Mode
Figure 22. Typical Connection Diagram (Parallel Control Mode)
Notes:
- LRCK = fs, BICK = 64 fs.
- W hen LOUT/ROUT drive s some capacitive load, so me resisto r should be a dded in se ries b e tw e e n LOUT/ROU T
and capaciti ve load.
- All input pins except P/S and T DM0 pins should not be left floating.
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
- 27 -
BICK
2
SDTI1
3
LRCK
4
RSTB
5
CSN
6
CCLK 7
CDTI 8
SDTI2
9
SDTI3 10
TST1 11
DIF1
12
CAD0
13
DZF2 29
AVDD 28
AVSS 27
VCOM 26
LOUT1 25
ROUT1 24
P/S 23
LOUT2 22
ROUT2 21
LOUT3 20
ROUT3 19
TST3 18
Micro-
controller
0.1u
AK4346
Analog 3.3V
14
15
17
16
DVDD
DVSS
TST2
I2C
R1ch Out
L1ch Out
Analog Ground Digital Ground
L2ch Out
R2ch Out
Master Clock
fs
24bit Audio Data
64fs
Reset
24bit Audio Data
24bit Audio Data +
+
0.1u
10u
Digital 3.3V
MCLK
1 DZF1 30
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
L3ch Out
R3ch Out
0.1u +
10u
Micro-
controller
10u
Figur e 23. Typical Connecti on Diagram (3-wire Seri al Control Mode)
Notes:
- LRCK = fs, BICK = 64 fs.
- W hen LOUT/ROUT drive s some c a pacitive lo ad, so me resis tor should b e a dded in se ries b etween LOUT/ROU T
and capaciti ve load.
- All input pins except P/S pin sh ould n ot be left floatin g.
- DZF1 control bits must be set to “1” in order to ena ble the DZF function.
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
- 28 -
Analog Ground
Digital Ground
System
Controller
BICK
SDTI1
3
LRCK 4
PDN
5
SMUTE/CSN/CAD06
ACKS/CCLK/CSL7
DFS0/CDT/SDA8
SDTI2
9
SDTI3
10
TST1 11
DIF1
12
DEM0/CAD113
TDM0/DZF2 29
AVDD 28
AVSS 27
VCOM 26
LOUT1 25
ROUT1 24
P/S 23
LOUT2 22
ROUT2 21
LOUT3 20
ROUT3 19
TST3
AK4346
18
14
15
17
16
DVDD
DVSS
TST2
DEM1/I2
MCLK DZF1 30
2
1
Figure 24. Ground Layout
AVSS and DVSS must be connected t o t he same analog ground plane.
1. Grounding and Power Supply Decoupling
AVDD and DVDD are usually su pplied from the analog supply in the system and it should be separated fr om system
di gi ta l supp ly. Altern at i vely if AVDD a nd DVDD are su ppl i ed separately, th e power up sequ ence i s n ot critica l. AVSS
and DVSS of the AK4346 must be connected to the analog ground plane. System analog ground and digital ground
sh ould be conn ected tog eth er cl ose t o wh er e the su ppl i es ar e brou gh t on t o th e pr i n t ed cir cu it boa r d . A decoupl i n g
c a pacitor, typ icall y a 0.1µF ceramic capacitor for high frequency by pass, should be placed as near to AVDD and DVDD
as possible.
2. An a log Out puts
The a nalog outputs are single-ended and c e ntered around the VCOM voltage. T he output signal range is typically
2.24Vpp (when AVDD=3.3V). The phase of the analog outputs can be inverted cha nnel independentl y by the
INVL/INVR bi ts. The internal switched-capacitor filter and continuous-time filter att enuate the noise generated by th e
delta-sigma modulator beyond the audio passband. The input data format is 2’s complement. The output voltage is a
positive full scale for 7FFFFFH (@24-bit) and a negative full scale for 800000H (@24-bit). The ideal output is VC OM
voltage for 000000H (@24-bit).
DC offsets on the analog outputs are eliminated by AC coupling since the analog outputs hav e DC o ff sets of VCOM + a
few m V .
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
- 29 -
PACKAGE
Detai l A
NOT E : Dimension "*" does n ot include mold flash.
0.22±0.1 0.65
*9.7±0.1 1.5MAX
A
115
16
30
30pin V SO P (Unit: m m )
5.6±0.1
7.6±0.2
0.45±0.2
-0.05
+0.10
0.3
0.15
0.12 M
0.08
1.2±0.10
0.10 +0.10
-0.05
Package & Lead frame materia l
Package molding compound: Epoxy
Lead frame material: Cu
Lead fram e surf ace treatment: Solder (Pb free) plate
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
- 30 -
MARKI NG (AK4346EF )
AKM
A
K4346EF
XXXBYYYYC
XXXBYYYYC Date code identif ier
XXXB: Lot number (X: Dig it nu m ber , B: Alp ha cha r a cter )
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
ASAHI KASEI [AK4346]
MS0531-E-00 2006/07
- 31 -
MARKI NG (AK4346VF )
AKM
A
K4346VF
XXXBYYYYC
XXXBYYYYC Date code identif ier
XXXB: Lot number (X: Dig it nu m ber , B: Alp ha cha r a cter )
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
Date (YY/MM/DD) Revision Reason Page Contents
06/07/28 00 First edition
IMPO RTANT NOTICE
• Th ese pr o du cts a nd th eir sp ec i fi ca t i ons a re subj e c t t o ch an ge w i thout n otic e. Bef o r e consi d er i n g
any use or a ppl ic at ion , c onsul t the Asah i Ka sei Mi cro syst ems C o. , Lt d. (AK M) sal es of f i ce o r
authorized distributor concerning their current status.
• AKM assum es no l iab i l ity f or i nfringem en t o f a ny p at e nt , in t ellec t u al pro pe r t y, or ot h er ri gh t in th e
appl i c ation or u se of an y in f orm ati on c on tai ned h ere in .
• A ny export o f these pro ducts, or de v ices or s y stems con taining them , may req uir e a n export licen s e
or oth er o ff i ci al app rova l un der th e l aw a nd r egu lat ion s of t he co unt ry of expor t p erta in in g to
c ustom s and tari f f s, cur ren cy exchan ge, or strat egi c m ater i als.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard rel ated device or syst em, and AKM assumes no responsibil ity relating to
any such use, except with the express written consent of t he Representative Director of AKM. As
used here:
(a) A h azard r e l at e d de vi ce o r system is on e des i g ne d or inte nd ed for l i f e s upp or t o r m ainte na nc e
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to f unction or perform may reasonabl y be expect ed to resul t in loss of lif e or in
si gni f ic ant in ju ry or dam age to perso n or p rop erty .
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or i ndirectly, in the loss of the saf ety or ef fectiveness of t he devi ce or
system con ta ini ng it , and w hi ch m ust the ref or e me et very hi gh st an dards of pe rf orm anc e and
reli ability.
• It is the responsibilit y of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product wit h a thir d party to notify that party in adv ance of the abov e content
and conditions, and the buyer or dis tributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and al l clai ms arising f rom the use of said product in the
absence of such notif ication.
