SST25LF040A-33-4I-QAE - Silicon Storage Technology

S71242-00-EOL 3/09

The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Data Sheet

FEATURES:

• Single 3.0-3.6V Read and Write Operations

• Serial Interface Architecture

– SPI Compatible: Mode 0 and Mode 3

• 33 MHz Max Clock Frequency

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Read Current: 7 mA (typical)

– Standby Current: 8 µA (typical)

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 32 KByte overlay blocks

• Fast Erase and Byte-Program:

– Chip-Erase Time: 70 ms (typical)

– Sector- or Block-Erase Time: 18 ms (typical)

– Byte-Program Time: 14 µs (typical)

• Auto Address Increment (AAI) Programming

– Decrease total chip programming time over

Byte-Program operations

• End-of-Write Detection

– Software Status

• Hold Pin (HOLD#)

– Suspends a serial sequence to the memory

without deselecting the device

• Write Protection (WP#)

– Enables/Disables the Lock-Down function of the

status register

• Software Write Protection

– Write protection through Block-Protection bits in

status register

• Temperature Range

– Commercial: 0°C to +70°C

– Industrial: -40°C to +85°C

– Extended: -20°C to +85°C

• Packages Available

– 8-lead SOIC 200 mil body width

– 8-contact WSON (5mm x 6mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

SST25LF040A features a four-wire, SPI-compatible

interface that allows for a low pin-count package occupy-

ing less board space and ultimately lowering total system

costs. SST25LF040A SPI serial flash memories are

manufactured with SST’s proprietary, high performance

CMOS SuperFlash technology. The split-gate cell design

and thick-oxide tunneling injector attain better reliability

and manufacturability compared with alternate

approaches.

The SST25LF040A significantly improves performance,

while lowering power consumption. The total energy con-

sumed is a function of the applied voltage, current, and

time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and

has a shorter erase time, the total energy consumed dur-

ing any Erase or Program operation is less than alterna-

tive flash memory technologies. The SST25LF040A

devices operate with a single 3.0-3.6V power supply.

The SST25LF040A is offered in an 8-lead SOIC 200 mil

body width (S2A) package and an 8-contact WSON

package. See Figure 1 for the pin assignments.

4 Mbit SPI Serial Flash

SST25LF040A

SST25LF020A / 040A2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

1242 B1.0

I/O Buffers

and

Data Latches

SuperFlash

Memory

X - Decoder

Control Logic

Address

Buffers

and

Latches

CE#

Y - Decoder

SCK SI SO WP# HOLD#

Serial Interface

FUNCTIONAL BLOCK DIAGRAM

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

PIN DESCRIPTION

FIGURE 1: PIN ASSIGNMENTS

TABLE 1: PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock input, while output

data is shifted out on the falling edge of the clock input.

SI Serial Data

Input

To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO Serial Data

Output

To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of

any command sequence.

WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.

HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device.

VDD Power Supply To provide power supply (3.0-3.6V).

VSS Ground

T1.0 1242(01)

8-LEAD SOIC 8-CONTACT WSON

CE#

WP#

VSS

Top View

VDD

HOLD#

SCK

1242 08-wson P2.0

CE#

WP#

VSS

VDD

HOLD#

SCK

Top View

1242 08-soic P1.0

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

PRODUCT IDENTIFICATION

MEMORY ORGANIZATION

The SST25LF040A SuperFlash memory array is orga-

nized in 4 KByte sectors with 32 KByte overlay blocks.

DEVICE OPERATION

The SST25LF040A is accessed through the SPI (Serial

Peripheral Interface) bus compatible protocol. The SPI bus

consist of four control lines; Chip Enable (CE#) is used to

select the device, and data is accessed through the Serial

Data Input (SI), Serial Data Output (SO), and Serial Clock

(SCK).

The SST25LF040A supports both Mode 0 (0,0) and Mode

3 (1,1) of SPI bus operations. The difference between the

two modes, as shown in Figure 2, is the state of the SCK

signal when the bus master is in Stand-by mode and no

data is being transferred. The SCK signal is low for Mode 0

and SCK signal is high for Mode 3. For both modes, the

Serial Data In (SI) is sampled at the rising edge of the SCK

clock signal and the Serial Data Output (SO) is driven after

the falling edge of the SCK clock signal.

FIGURE 2: SPI PROTOCOL

TABLE 2: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 00000H BFH

Device ID

SST25LF040A 00001H 44H

T2.0 1242(01)

1242 F02.0

MODE 3

SCK

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Hold Operation

HOLD# pin is used to pause a serial sequence underway

with the SPI flash memory without resetting the clocking

sequence. To activate the HOLD# mode, CE# must be in

active low state. The HOLD# mode begins when the SCK

active low state coincides with the falling edge of the

HOLD# signal. The HOLD mode ends when the HOLD#

signal’s rising edge coincides with the SCK active low state.

If the falling edge of the HOLD# signal does not coincide

with the SCK active low state, then the device enters Hold

mode when the SCK next reaches the active low state.

Similarly, if the rising edge of the HOLD# signal does not

coincide with the SCK active low state, then the device

exits in Hold mode when the SCK next reaches the active

low state. See Figure 3 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high-

impedance state while SI and SCK can be VIL or VIH.

If CE# is driven active high during a Hold condition, it resets

the internal logic of the device. As long as HOLD# signal is

low, the memory remains in the Hold condition. To resume

communication with the device, HOLD# must be driven

active high, and CE# must be driven active low. See Figure

18 for Hold timing.

FIGURE 3: HOLD CONDITION WAVEFORM

Write Protection

SST25LF040A provides software Write protection. The

Write Protect pin (WP#) enables or disables the lock-down

function of the status register. The Block-Protection bits

(BP1, BP0, and BPL) in the status register provide Write

protection to the memory array and the status register. See

Table 5 for Block-Protection description.

Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down func-

tion of the BPL bit (bit 7) in the status register. When WP#

is driven low, the execution of the Write-Status-Register

(WRSR) instruction is determined by the value of the BPL

bit (see Table 3). When WP# is high, the lock-down func-

tion of the BPL bit is disabled.

Active Hold Active Hold Active

1242 F03.0

SCK

HOLD#

TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-

WP# BPL Execute WRSR Instruction

L 1 Not Allowed

L0Allowed

HXAllowed

T3.0 1242(01)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Status Register

The software status register provides status on whether the

flash memory array is available for any Read or Write oper-

ation, whether the device is Write enabled, and the state of

the memory Write protection. During an internal Erase or

Program operation, the status register may be read only to

determine the completion of an operation in progress.

Table 4 describes the function of each bit in the software

status register.

Busy

The Busy bit determines whether there is an internal Erase

or Program operation in progress. A “1” for the Busy bit indi-

cates the device is busy with an operation in progress. A “0”

indicates the device is ready for the next valid operation.

Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the inter-

nal memory Write Enable Latch. If the Write-Enable-Latch

bit is set to “1”, it indicates the device is Write enabled. If the

bit is set to “0” (reset), it indicates the device is not Write

enabled and does not accept any memory Write (Program/

Erase) commands. The Write-Enable-Latch bit is automati-

cally reset under the following conditions:

•Power-up

•Write-Disable (WRDI) instruction completion

•Byte-Program instruction completion

•Auto Address Increment (AAI) programming

reached its highest memory address

•Sector-Erase instruction completion

•Block-Erase instruction completion

•Chip-Erase instruction completion

TABLE 4: SOFTWARE STATUS REGISTER

Bit Name Function

Default at

Power-up Read/Write

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled

2 BP0 Indicate current level of block write protection (See Table 5) 1 R/W

3 BP1 Indicate current level of block write protection (See Table 5) 1 R/W

4:5 RES Reserved for future use 0 N/A

6 AAI Auto Address Increment Programming status

1 = AAI programming mode

0 = Byte-Program mode

7 BPL 1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable

0R/W

T4.0 1242(01)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Block Protection (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of the

memory area, as defined in Table 5, to be software pro-

tected against any memory Write (Program or Erase)

operations. The Write-Status-Register (WRSR) instruction

is used to program the BP1 and BP0 bits as long as WP#

is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase

can only be executed if Block-Protection bits are both 0.

After power-up, BP1 and BP0 are set to 1.

Block Protection Lock-Down (BPL)

WP# pin driven low (VIL), enables the Block-Protection-

Lock-Down (BPL) bit. When BPL is set to 1, it prevents any

further alteration of the BPL, BP1, and BP0 bits. When the

WP# pin is driven high (VIH), the BPL bit has no effect and

its value is “Don’t Care”. After power-up, the BPL bit is

reset to 0.

Auto Address Increment (AAI)

The Auto Address Increment Programming-Status bit pro-

vides status on whether the device is in AAI programming

mode or Byte-Program mode. The default at power up is

Byte-Program mode.

TABLE 5: SOFTWARE STATUS REGISTER BLOCK PROTECTION1

1. Default at power-up for BP1 and BP0 is ‘11’.

Protection Level

Status

Bit Protected Memory Area

BP1 BP0 4 Mbit

000None

1 (1/4 Memory Array) 0 1 060000H-07FFFFH

2 (1/2 Memory Array) 1 0 040000H-07FFFFH

3 (Full Memory Array) 1 1 000000H-07FFFFH

T5.0 1242(01)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Instructions

Instructions are used to Read, Write (Erase and Program),

and configure the SST25LF040A. The instruction bus

cycles are 8 bits each for commands (Op Code), data, and

addresses. Prior to executing any Byte-Program, Auto

Address Increment (AAI) programming, Sector-Erase,

Block-Erase, or Chip-Erase instructions, the Write-Enable

(WREN) instruction must be executed first. The complete

list of the instructions is provided in Table 6. All instructions

are synchronized off a high to low transition of CE#. Inputs

will be accepted on the rising edge of SCK starting with the

most significant bit. CE# must be driven low before an

instruction is entered and must be driven high after the last

bit of the instruction has been shifted in (except for Read,

Read-ID and Read-Status-Register instructions). Any low

to high transition on CE#, before receiving the last bit of an

instruction bus cycle, will terminate the instruction in

progress and return the device to the standby mode.

Instruction commands (Op Code), addresses, and data are

all input from the most significant bit (MSB) first.

TABLE 6: DEVICE OPERATION INSTRUCTIONS1

1. AMS = Most Significant Address

AMS = A18 for SST25LF040A

Address bits above the most significant bit of each density can be VIL or VIH

Cycle Type/

Operation2,3

2. Operation: SIN = Serial In, SOUT = Serial Out

3. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)

Max

Freq

MHz

Bus Cycle4

4. One bus cycle is eight clock periods.

123456

SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT

Read 20 03H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X DOUT

High-Speed-Read

0BH Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X X X DOUT

Sector-Erase5,6

5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH

6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction

must be executed.

20H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - -

Block-Erase5,7

7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH

52H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - -

Chip-Erase660HHi-Z- -------

Byte-Program602H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN Hi-Z

Auto Address Increment

(AAI) Single-Byte Program6,8

8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,

followed by the data to be programmed.

AFH Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN Hi-Z

Read-Status-Register

(RDSR)

05H Hi-Z X DOUT -Note

9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

-Note

9-Note

Enable-Write-Status-Register

(EWSR)10

10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of

each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both

instructions effective.

50HHi-Z- -------

Write-Status-Register

(WRSR)10

01H Hi-Z Data Hi-Z - - -. - - -

Write-Enable (WREN) 06HHi-Z- -------

Write-Disable (WRDI) 04HHi-Z- -------

Read-ID 90H or

ABH

Hi-Z 00H Hi-Z 00H Hi-Z ID

Addr11

11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer and Device

ID output stream is continuous until terminated by a low to high transition on CE#

Hi-Z X DOUT12

12. Device ID = 44H for SST25LF040A

T6.0 1242(01)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Read (20 MHz)

The Read instruction supports up to 20 MHz, it outputs the

data starting from the specified address location. The data

output stream is continuous through all addresses until ter-

minated by a low to high transition on CE#. The internal

address pointer will automatically increment until the high-

est memory address is reached. Once the highest memory

address is reached, the address pointer will automatically

increment to the beginning (wrap-around) of the address

space, i.e. for 4 Mbit density, once the data from address

location 7FFFFH had been read, the next output will be

from address location 00000H.

The Read instruction is initiated by executing an 8-bit com-

mand, 03H, followed by address bits [A23-A0]. CE# must

remain active low for the duration of the Read cycle. See

Figure 4 for the Read sequence.

FIGURE 4: READ SEQUENCE

1242 F04.0

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 7047 48 55 56 63 64

N+2 N+3 N+4N N+1

DOUT

MSB MSB

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

High-Speed-Read (33 MHz)

The High-Speed-Read instruction supporting up to 33 MHz

is initiated by executing an 8-bit command, 0BH, followed

by address bits [A23-A0] and a dummy byte. CE# must

remain active low for the duration of the High-Speed-Read

cycle. See Figure 5 for the High-Speed-Read sequence.

Following a dummy byte (8 clocks input dummy cycle), the

High-Speed-Read instruction outputs the data starting from

the specified address location. The data output stream is

continuous through all addresses until terminated by a low

to high transition on CE#. The internal address pointer will

automatically increment until the highest memory address

is reached. Once the highest memory address is reached,

the address pointer will automatically increment to the

beginning (wrap-around) of the address space, i.e. for

4 Mbit density, once the data from address location

07FFFFH has been read, the next output will be from

address location 000000H.

FIGURE 5: HIGH-SPEED-READ SEQUENCE

1242 F05.0

CE#

SCK

ADD.

012345678

ADD. ADD.0B

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63 64

N+2 N+3 N+4

NN+1

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

71 72

DOUT

Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Byte-Program

The Byte-Program instruction programs the bits in the

selected byte to the desired data. The selected byte must

be in the erased state (FFH) when initiating a Program

operation. A Byte-Program instruction applied to a pro-

tected memory area will be ignored.

Prior to any Write operation, the Write-Enable (WREN)

instruction must be executed. CE# must remain active low

for the duration of the Byte-Program instruction. The Byte-

Program instruction is initiated by executing an 8-bit com-

mand, 02H, followed by address bits [A23-A0]. Following the

address, the data is input in order from MSB (bit 7) to LSB

(bit 0). CE# must be driven high before the instruction is

executed. The user may poll the Busy bit in the software

status register or wait TBP for the completion of the internal

self-timed Byte-Program operation. See Figure 6 for the

Byte-Program sequence.

FIGURE 6: BYTE-PROGRAM SEQUENCE

1242 F06.0

CE#

SCK

ADD.

012345678

ADD. ADD. DIN

HIGH IMPEDANCE

15 16 23 24 31 32 39

MODE 0

MODE 3

MSBMSB

MSB LSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Auto Address Increment (AAI) Program

The AAI program instruction allows multiple bytes of data to

be programmed without re-issuing the next sequential

address location. This feature decreases total program-

ming time when the entire memory array is to be pro-

grammed. An AAI program instruction pointing to a

protected memory area will be ignored. The selected

address range must be in the erased state (FFH) when ini-

tiating an AAI program instruction.

Prior to any write operation, the Write-Enable (WREN)

instruction must be executed. The AAI program instruction

is initiated by executing an 8-bit command, AFH, followed

by address bits [A23-A0]. Following the addresses, the data

is input sequentially from MSB (bit 7) to LSB (bit 0). CE#

must be driven high before the AAI program instruction is

executed. The user must poll the BUSY bit in the software

status register or wait TBP for the completion of each inter-

nal self-timed Byte-Program cycle. Once the device com-

pletes programming byte, the next sequential address may

be program, enter the 8-bit command, AFH, followed by the

data to be programmed. When the last desired byte had

been programmed, execute the Write-Disable (WRDI)

instruction, 04H, to terminate AAI. After execution of the

WRDI command, the user must poll the Status register to

ensure the device completes programming. See Figure 7

for AAI programming sequence.

There is no wrap mode during AAI programming; once the

highest unprotected memory address is reached, the

device will exit AAI operation and reset the Write-Enable-

Latch bit (WEL = 0).

FIGURE 7: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE

CE#

SCK

A[23:16] A[15:8] A[7:0]

AF Data Byte 1 AF Data Byte 2

CE#

SCK

Write Disable (WRDI)

Instruction to terminate

AAI Operation

Read Status Register (RDSR)

Instruction to verify end of

AAI Operation

04Last Data ByteAF 05

DOUT

MODE 3

MODE 0

TBP TBP

TBP

1242 F07.0

012345678 32333435363738391516 2324 31 0123456789101112131415 01

012345670123456789101112131415 0123456789101112131415

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Sector-Erase

The Sector-Erase instruction clears all bits in the selected 4

KByte sector to FFH. A Sector-Erase instruction applied to

a protected memory area will be ignored. Prior to any Write

operation, the Write-Enable (WREN) instruction must be

executed. CE# must remain active low for the duration of

the any command sequence. The Sector-Erase instruction

is initiated by executing an 8-bit command, 20H, followed

by address bits [A23-A0]. Address bits [AMS-A12]

(AMS = Most Significant address) are used to determine the

sector address (SAX), remaining address bits can be VIL or

VIH. CE# must be driven high before the instruction is exe-

cuted. The user may poll the Busy bit in the software status

timed Sector-Erase cycle. See Figure 8 for the Sector-

Erase sequence.

FIGURE 8: SECTOR-ERASE SEQUENCE

Block-Erase

The Block-Erase instruction clears all bits in the selected 32

KByte block to FFH. A Block-Erase instruction applied to a

protected memory area will be ignored. Prior to any Write

operation, the Write-Enable (WREN) instruction must be

executed. CE# must remain active low for the duration of

any command sequence. The Block-Erase instruction is

initiated by executing an 8-bit command, 52H, followed by

address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most

significant address) are used to determine block address

(BAX), remaining address bits can be VIL or VIH. CE# must

be driven high before the instruction is executed. The user

may poll the Busy bit in the software status register or wait

TBE for the completion of the internal self-timed Block-

Erase cycle. See Figure 9 for the Block-Erase sequence.

FIGURE 9: BLOCK-ERASE SEQUENCE

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1242 F08.0

MSBMSB

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1242 F09.0

MSB MSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Chip-Erase

The Chip-Erase instruction clears all bits in the device to

FFH. A Chip-Erase instruction will be ignored if any of the

memory area is protected. Prior to any Write operation, the

Write-Enable (WREN) instruction must be executed. CE#

must remain active low for the duration of the Chip-Erase

instruction sequence. The Chip-Erase instruction is initiated

by executing an 8-bit command, 60H. CE# must be driven

high before the instruction is executed. The user may poll

the Busy bit in the software status register or wait TCE for

the completion of the internal self-timed Chip-Erase cycle.

See Figure 10 for the Chip-Erase sequence.

FIGURE 10: CHIP-ERASE SEQUENCE

Read-Status-Register (RDSR)

The Read-Status-Register (RDSR) instruction allows read-

ing of the status register. The status register may be read at

any time even during a Write (Program/Erase) operation.

When a Write operation is in progress, the Busy bit may be

checked before sending any new commands to assure that

the new commands are properly received by the device.

CE# must be driven low before the RDSR instruction is

entered and remain low until the status data is read. Read-

Status-Register is continuous with ongoing clock cycles

until it is terminated by a low to high transition of the CE#.

See Figure 11 for the RDSR instruction sequence.

FIGURE 11: READ-STATUS-REGISTER (RDSR) SEQUENCE

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1242 F10.0

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

1242 F11.0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

Status

MSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-

Enable-Latch bit to 1 allowing Write operations to occur.

The WREN instruction must be executed prior to any Write

(Program/Erase) operation. CE# must be driven high

before the WREN instruction is executed.

FIGURE 12: WRITE ENABLE (WREN) SEQUENCE

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-

Enable-Latch bit and AAI bit to 0 disabling any new Write

operations from occurring. CE# must be driven high before

the WRDI instruction is executed.

FIGURE 13: WRITE DISABLE (WRDI) SEQUENCE

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction

arms the Write-Status-Register (WRSR) instruction and

opens the status register for alteration. The Enable-Write-

Status-Register instruction does not have any effect and

will be wasted, if it is not followed immediately by the Write-

Status-Register (WRSR) instruction. CE# must be driven

low before the EWSR instruction is entered and must be

driven high before the EWSR instruction is executed.

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1242 F12.0

MSB

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1242 F13.0

MSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Write-Status-Register (WRSR)

The Write-Status-Register instruction works in conjunction

with the Enable-Write-Status-Register (EWSR) instruction

to write new values to the BP1, BP0, and BPL bits of the

status register. The Write-Status-Register instruction must

be executed immediately after the execution of the Enable-

Write-Status-Register instruction (very next instruction bus

cycle). This two-step instruction sequence of the EWSR

instruction followed by the WRSR instruction works like

SDP (software data protection) command structure which

prevents any accidental alteration of the status register val-

ues. The Write-Status-Register instruction will be ignored

when WP# is low and BPL bit is set to “1”. When the WP#

is low, the BPL bit can only be set from “0” to “1” to lock-

down the status register, but cannot be reset from “1” to “0”.

When WP# is high, the lock-down function of the BPL bit is

disabled and the BPL, BP0, and BP1 bits in the status reg-

ister can all be changed. As long as BPL bit is set to 0 or

WP# pin is driven high (VIH) prior to the low-to-high transi-

tion of the CE# pin at the end of the WRSR instruction, the

BP0, BP1, and BPL bit in the status register can all be

altered by the WRSR instruction. In this case, a single

WRSR instruction can set the BPL bit to “1” to lock down

the status register as well as altering the BP0 and BP1 bit

at the same time. See Table 3 for a summary description of

WP# and BPL functions. CE# must be driven low before

the command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is

executed. See Figure 14 for EWSR and WRSR instruction

sequences.

FIGURE 14: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE

1242 F14.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

76543210

MSBMSBMSB

MODE 3

SCK

CE#

MODE 0

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

Read-ID

The Read-ID instruction identifies the devices as

SST25LF040A and manufacturer as SST. The device infor-

mation can be read from executing an 8-bit command, 90H

or ABH, followed by address bits [A23-A0]. Following the

Read-ID instruction, the manufacturer’s ID is located in

address 00000H and the device ID is located in address

00001H. Once the device is in Read-ID mode, the manu-

facturer’s and device ID output data toggles between

address 00000H and 00001H until terminated by a low to

high transition on CE#.

FIGURE 15: READ-ID SEQUENCE

1242 F15.0

CE#

SCK

012345678

00 ADD

90 or AB

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63

BF Device ID BF Device ID

Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.

1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.

HIGH

IMPEDANCE

MODE 3

MODE 0

MSB MSB

MSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress

Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at

these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Expo-

sure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE:

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

Industrial -40°C to +85°C 3.0-3.6V

Extended -20°C to +85°C 3.0-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 20 and 21

TABLE 7: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open

IDDW Program and Erase Current 30 mA CE#=VDD

ISB Standby Current 15 µA CE#=VDD, VIN=VDD or VSS

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T7.0 1242(01)

TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

VDD Min to Read Operation 10 µs

TPU-WRITE1VDD Min to Write Operation 10 µs

T8.0 1242(01)

TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

COUT1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Output Pin Capacitance VOUT = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T9.0 1242(01)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

TABLE 10: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T10.0 1242(01)

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: AC OPERATING CHARACTERISTICS VDD = 3.0-3.6V

Limits

20 MHz 33 MHz

Symbol Parameter Min Max Min Max Units

FCLK Serial Clock Frequency 20 33 MHz

TSCKH Serial Clock High Time 20 13 ns

TSCKL Serial Clock Low Time 20 13 ns

TCES1

1. Relative to SCK.

CE# Active Setup Time 20 12 ns

TCEH1CE# Active Hold Time 20 12 ns

TCHS1CE# Not Active Setup Time 10 10 ns

TCHH1CE# Not Active Hold Time 10 10 ns

TCPH CE# High Time 100 100 ns

TCHZ CE# High to High-Z Output 20 14 ns

TCLZ SCK Low to Low-Z Output 0 0 ns

TDS Data In Setup Time 5 3 ns

TDH Data In Hold Time 5 3 ns

THLS HOLD# Low Setup Time 10 10 ns

THHS HOLD# High Setup Time 10 10 ns

THLH HOLD# Low Hold Time 15 10 ns

THHH HOLD# High Hold Time 10 10 ns

THZ HOLD# Low to High-Z Output 20 14 ns

TLZ HOLD# High to Low-Z Output 20 14 ns

TOH Output Hold from SCK Change 0 0 ns

TVOutput Valid from SCK 20 12 ns

TSE Sector-Erase 25 25 ms

TBE Block-Erase 25 25 ms

TSCE Chip-Erase 100 100 ms

TBP Byte-Program 20 20 µs

T11.0 1242(01)

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

FIGURE 16: SERIAL INPUT TIMING DIAGRAM

FIGURE 17: SERIAL OUTPUT TIMING DIAGRAM

HIGH-Z HIGH-Z

CE#

SCK

MSB LSB

TDS TDH

TCHH

TCES TCEH TCHS

TSCKR

TSCKF

TCPH

1242 F16.0

1242 F17.0

CE#

SCK

MSB

TCLZ

TSCKH

TCHZ

TOH

TSCKL

LSB

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

FIGURE 18: HOLD TIMING DIAGRAM

FIGURE 19: POWER-UP TIMING DIAGRAM

THZ TLZ

THHH THLS

THLH

THHS

1242 F18.0

HOLD#

CE#

SCK

Time

VDD Min

VDD Max

VDD

Device fully accessible

TPU-READ

TPU-WRITE

Chip selection is not allowed.

All commands are rejected by the device.

1242 F19.0

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 21: A TEST LOAD EXAMPLE

1242 F20.0

REFERENCE POINTS OUTPUTINPUT?

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VHT - VHIGH Te s t

VLT - VLOW Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1242 F21.0

TO TESTER

TO DUT

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

PRODUCT ORDERING INFORMATION

Valid combinations for SST25LF040A

SST25LF040A-33-4C-S2AE SST25LF040A-33-4C-QAE

SST25LF040A-33-4I-S2AE SST25LF040A-33-4I-QAE

SST25LF040A-33-4E-S2AE SST25LF040A-33-4E-QAE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

SST 25 LF 040 A - 33 - 4I - S2A E

XX XXXXXXX - XXX -XX- XXX X

Environmental Attribute

E1 = non-Pb

Package Modifier

A = 8 leads or contacts

Package Type

S2 = SOIC 200 mil body width

Q = WSON

Operation Temperature

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Operating Frequency

33 = 33 MHz

Device Density

040 = 4 Mbit

Voltag e

L = 3.0-3.6V

Product Series

25 = Serial Peripheral Interface flash memory

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

PACKAGING DIAGRAMS

8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 200 MIL BODY WIDTH (5.2MM X 8MM)

SST PACKAGE CODE: S2A

2.16

1.75

08-soic-EIAJ-S2A-3

Note: 1. All linear dimensions are in millimeters (max/min).

2. Coplanarity: 0.1 mm

3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.

TOP VIEW SIDE VIEW

END VIEW

5.40

5.15

8.10

7.70

5.40

5.15

Pin #1

Identifier

0.50

0.35

1.27 BSC

0.25

0.05

0.25

0.19

0.80

0.50

0˚

8˚

1mm

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EOL Data Sheet

4 Mbit SPI Serial Flash

SST25LF040A

8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)

SST PACKAGE CODE: QA

TABLE 12: REVISION HISTORY

Number Description Date

00 •Initial release of S71242(01) to EOL all valid combinations of SST25LF040A Mar 2009

Note: 1. All linear dimensions are in millimeters (max/min).

2. Untoleranced dimensions (shown with box surround)

are nominal target dimensions.

3. The external paddle is electrically connected to the

die back-side and possibly to certain VSS leads.

This paddle can be soldered to the PC board;

it is suggested to connect this paddle to the VSS of the unit.

Connection of this paddle to any other voltage potential can

result in shorts and/or electrical malfunction of the device.

8-wson-5x6-QA-9.0

4.0

1.27 BSC

Pin #1

0.48

0.35

0.076

3.4

5.00 ± 0.10

6.00 ± 0.10 0.05 Max

0.70

0.50

0.80

0.70

0.80

0.70

Pin #1

Corner

TOP VIEW BOTTOM VIEW

CROSS SECTION

SIDE VIEW

1mm

0.2

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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