CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
Description
The HCPL-2602/12 are optically coupled line receivers
that combine a GaAsP light emitting diode, an input
current regulator and an integrated high gain photo
detector. The input regulator serves as a line
termination for line receiver applications. It clamps
the line voltage and regulates the LED current so line
reflections do not interfere with circuit performance.
The regulator allows a typical LED current of 8.5 mA
before it starts to shunt excess current. The output
of the detector IC is an open collector Schottky clamped
transistor. An enable input gates the detector. The
internal detector shield provides a guaranteed
common mode transient immunity specification of
1000 V/ms for the 2602, and 3500 V/ms for the 2612.
DC specifications are defined similar to TTL logic.
The optocoupler ac and dc operational parameters
are guaranteed from 0°C to 70°C allowing trouble-
free interfacing with digital logic circuits. An input
current of 5 mA will sink an eight gate fan-out (TTL)
at the output.
HCPL-2602, HCPL-2612
High CMR Line Receiv er Opt oc ouplers
Data Sheet
Features
•1000 V/µs minimum Common Mode Rejection (CMR) at
VCM = 50 V for HCPL-2602 and 3.5 kV/µs minimum
CMR at VCM = 300 V for HCPL-2612
•Line termination included – no extra circuitry required
•Accepts a broad range of drive conditions
•LED protection minimizes LED efficiency degradation
•High speed: 10 MBd (limited by transmission line in
many applications)
•Guaranteed AC and DC performance over temperature:
0°C to 70°C
•External base lead allows “LED peaking” and LED
current adjustment
•Safety approval
UL recognized – 3750 V rms for 1 Minute
CSA approved
•MIL-PRF-38534 hermetic version available (HCPL-1930/1)
Applications
•Isolated line receiver
•Computer-peripheral interface
•Microprocessor system interface
•Digital isolation for A/D, D/A conversion
•Current sensing
•Instrument input/output isolation
•Ground loop elimination
•Pulse transformer replacement
•Power transistor isolation in motor drives
Functional Diagram
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
1
2
3
4
8
7
6
5
IN–
IN+
GND
V
V
CC
O
V
E
NC
CATHODE
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
TRUTH TABLE
(POSITIVE LOGIC)
SHIELD
2
Selection Guide
Widebody
Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8(400 Mil) Hermetic Hermetic
On- Single Dual Single Dual Single Single and
dV/dt VCM Current Output Channel Channel Channel Channel Channel Dual Channel
(V/µs) (V) (mA) Enable Package Package Package Package Package Packages
NA NA 5 YES 6N137 HCPL-0600 HCNW137
NO HCPL-2630 HCPL-0630
5,000 50 YES HCPL-2601 HCPL-0601 HCNW2601
NO HCPL-2631 HCPL-0631
10,000 1,000 YES HCPL-2611 HCPL-0611 HCNW2611
NO HCPL-4661 HCPL-0661
1,000 50 YES HCPL-2602[1]
3,500 300 YES HCPL-2612[1]
1,000 50 3 YES HCPL-261A HCPL-061A
NO HCPL-263A HCPL-063A
1,000[2] 1,000 YES HCPL-261N HCPL-061N
NO HCPL-263N HCPL-063N
1,000 50 12.5 [3] HCPL-193X
HCPL-56XX
HCPL-66XX
Notes:
1. HCPL-2602/2612 devices include input current regulator.
2. 15 kV/µs with VCM = 1 kV can be achieved using Avago application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
Input
The HCPL-2602/12 are useful as line receivers in
high noise environments that conventional line
receivers cannot tolerate. The higher LED threshold
voltage provides improved immunity to differential
noise and the internally shielded detector provides
orders of magnitude improvement in common mode
rejection with little or no sacrifice in speed.
3
Schematic
SHIELD
8
6
5
2
4
VI
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1).
IFICC VCC
VO
GND
IO
VE
IE7
3
–
II
+
90 Ω
Ordering Information
HCPL-2602/HCPL-2612 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part RoHS non RoHS Surface Gull Tape
Number Compliant Compliant Package Mount Wing & Reel Quantity
HCPL-2602 -000E no option 300 mil DIP-8 50 per tube
HCPL-2612 -300E #300 X X 50 per tube
-500E #500 X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the
option column to form an order entry.
Example 1:
HCPL-2602-500E to order product of Gull Wing Surface Mount package in Tape and Reel packaging and RoHS
compliant.
Example 2:
HCPL-2612 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for
information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15,
2001 and RoHS compliant will use ‘–XXXE.’
4
8-Pin DIP Package with Gull Wing Surface Mount Option 300
8-Pin DIP Package
Package Outline Drawings
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
5° TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
5678
4321
TYPE NUMBER
UL
RECOGNITION
UR
3.56 ± 0.13
(0.140 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
5
Regulatory Information
The HCPL-2602/2612 have been
approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition Program,
File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
Solder Reflow Thermal Profile
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
Recommended Pb-Free IR Profile
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTU AL
PEAK TEMPERA TURE
tp
ts
PREHEAT
60 to 180 SEC.
tL
TL
Tsmax
Tsmin
25
Tp
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Insulation and Safety Related Specifications
Parameter Symbol Value Units Conditions
Min. External Air Gap L(I01) 7.1 mm Measured from input terminals to output terminals,
(External Clearance) shortest distance through air.
Min. External Tracking L(I02) 7.4 mm Measured from input terminals to output terminals,
Path (External Creepage) shortest distance path along body.
Min. Internal Plastic 0.08 mm Through insulation distance, conductor to conductor,
Gap (Internal Clearance) usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity.
Tracking Resistance CTI 200 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
Note: Non-halide flux should be used.
Note: Non-halide flux should be used.
6
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Input Current, Low Level IIL 0250 µA
Input Current, High Level IIH 5* 60 mA
Supply Voltage, Output VCC 4.5 5.5 V
High Level Enable Voltage VEH 2.0 VCC V
Low Level Enable Voltage VEL 00.8 V
Fan Out (@ RL = 1 kΩ)N 5TTL Loads
Output Pull-up Resistor RL330 4 K Ω
Operating Temperature TA070 °C
*The initial switching threshold is 5 mA or less. It is recommended that an input current between
6.3 mA and 10 mA be used to obtain best performance and to provide at least 20% LED degradation
guardband.
Absolute Maximum Ratings (No Derating Required up to 85°C)
Parameter Symbol Min. Max. Units
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 85 °C
Forward Input Current II60 mA
Reverse Input Current IIR 60 mA
Input Current, Pin 4 -10 10 mA
Supply Voltage (1 Minute Maximum) VCC 7V
Enable Input Voltage (Not to Exceed VCC by VEVCC + 0.5 V
more than 500 mV)
Output Collector Current IO50 mA
Output Collector Voltage (Selection for Higher VO7V
Output Voltages up to 20 V is Available.)
Output Collector Power Dissipation PO40 mW
Lead Solder Temperature TLS 260°C for 10 sec., 1.6 mm below
seating plane
Solder Reflow Temperature Profile See Package Outline Drawings section
7
Electrical Characteristics
Over recommended temperature (TA = 0°C to +70°C) unless otherwise specified. See note 1.
Parameter Sym. Min. Typ.* Max. Units Test Conditions Fig. Note
High Level Output IOH 5.5 100 µAV
CC = 5.5 V, VO = 5.5 V, 1
Current II = 250 µA, VE = 2.0 V
Low Level Output VOL 0.35 0.6 V VCC = 5.5 V, II = 5 mA, 2, 4,
Voltage VE = 2.0 V, 5, 14
IOL (Sinking) = 13 mA
High Level Supply ICCH 7.5 10 mA VCC = 5.5 V, II = 0 mA,
Current VE = 0.5 V
Low Level Supply ICCL 10 13 mA VCC = 5.5 V, II = 60 mA,
Current VE = 0.5 V
High Level Enable IEH -0.7 -1.6 mA VCC = 5.5 V, VE = 2.0 V
Current
Low Level Enable IEL -0.9 -1.6 mA VCC = 5.5 V, VE = 0.5 V
Current
High Level Enable VEH 2.0 V 10
Voltage
Low Level Enable VEL 0.8 V
Voltage
2.0 2.4 II = 5 mA
Input Voltage VIV3
2.3 2.7 II = 60 mA
Input Reverse VR0.75 0.95 V IR = 5 mA
Voltage
Input Capacitance CIN 90 pF VI = 0 V, f = 1 MHz
*All typicals at VCC = 5 V, TA = 25°C.
8
Switching Specifications
Over recommended temperature (TA = 0°C to +70°C), VCC = 5 V, II = 7.5 mA, unless otherwise specified.
Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay 75 ns TA = 25°C
Time to High Output tPLH 20 48 6, 7, 8 3
Level 100 ns
Propagation Delay 75 ns TA = 25°C
Time to Low Output tPHL 25 50 6, 7, 8 4
Level 100 ns RL = 350 Ω
Pulse Width |tPHL-tPLH|3.5 35 ns CL = 15 pF 9 13
Distortion
Propagation Delay tPSK 40 ns 12,
Skew 13
Output Rise Time tr24 ns 12
(10-90%)
Output Fall Time tf10 ns 12
(90-10%)
Propagation Delay tELH 30 ns RL = 350 Ω, CL = 15 pF,
Time of Enable from VEL = 0 V, VEH = 3 V 10, 11 5
VEH to VEL
Propagation Delay tEHL 20 ns RL = 350 Ω, CL = 15 pF,
Time of Enable from VEL = 0 V, VEH = 3 V 10, 11 6
VEL to VEH
Common Mode HCPL-2602 1000 10,000 VCM = 50 V VO(MIN) = 2 V,
Transient |CMH|V/µsR
L = 350 Ω,137, 9,
Immunity at High HCPL-2612 3500 15,000 VCM = 300 V II = 0 mA, 10
Output Level TA = 25°C
Common Mode HCPL-2602 1000 10,000 VCM = 50 V VO(MAX) = 0.8 V,
Transient |CML|V/µsR
L = 350 Ω,138, 9
Immunity at Low HCPL-2612 3500 15,000 VCM = 300 V II = 7.5 mA, 10
Output Level TA = 25°C
*All typicals at VCC = 5 V, TA = 25°C.
Package Characteristics
All Typicals at TA = 25°C
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO 3750 V rms RH ≤ 50%, t = 1 min., 2, 11
Withstand Voltage*TA = 25°C
Input-Output Resistance RI-O 1012 ΩVI-O = 500 Vdc 2
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz 2
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level
safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
9
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 15. Total
lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
2. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
3. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
output pulse.
4. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
output pulse.
5. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge
of the output pulse.
6. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge
of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V).
9. For sinusoidal voltages,
|dvCM|
–––––– = πfCMVCM (p-p)
dt max
10. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR
performance.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage of ≥ 4500 for one second (leakage detection
current limit, Ii-o ≤ 5 µA).
12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the operating condition
range.
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
Figure 1. Typical high level output current vs.
temperature. Figure 2. Typical low level output voltage vs.
temperature. Figure 3. Typical input characteristics.
1.00203040 60
I
I
– INPUT CURRENT – mA
10 50
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
V
I
– INPUT VOLTAGE – V
25°C
70°C
0°C
Figure 5. Typical low level output current vs.
temperature.
Figure 4. Typical output voltage vs. forward
input current.
1
6
2
3
4
5
123456
I
F
– FORWARD INPUT CURRENT – mA
R
L
= 350 Ω
R
L
= 1 KΩ
R
L
= 4 KΩ
00
V
CC
= 5 V
T
A
= 25 °C
V
O
– OUTPUT VOLTAGE – V
I
OH
– HIGH LEVEL OUTPUT CURRENT – µA
-60
0
T
A
– TEMPERATURE – °C
100
10
15
-20
5
20
V
CC
= 5.5 V
V
O
= 5.5 V
V
E
= 2 V
I
I
= 250 µA
60
-40 0 40 80
VCC = 5.5 V
VE = 2 V
II = 5 mA
0.5
0.4
-60 -20 20 60 100
TA – TEMPERATURE – °C
0.3
80400-40
0.1
VOL – LOW LEVEL OUTPUT VOLTAGE – V
0.2
IO = 16 mA
IO = 12.8 mA
IO = 9.6 mA
IO = 6.4 mA
V
CC
= 5 V
V
E
= 2 V
V
OL
= 0.6 V
70
60
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
50
80400-40
20
I
OL
– LOW LEVEL OUTPUT CURRENT – mA
40
I
I
= 10-15 mA
I
I
= 5.0 mA
10
Figure 10. Test circuit for tEHL and tELH.Figure 11. Typical enable propagation delay
vs. temperature.
Figure 7. Typical propagation delay vs.
temperature.
Figure 8. Typical propagation delay vs. pulse
input current. Figure 9. Typical pulse width distortion vs.
temperature.
Figure 6. Test circuit for tPHL and tPLH.
OUTPUT V
MONITORING
NODE
O
+5 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z = 50 Ω
t = t = 5 ns
O
f
I
I
L
R
R
M
CC
V
0.1µF
BYPASS
*C
L
*C
L
IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
GND
INPUT
MONITORING
NODE
r
1.5 V
t
PHL
t
PLH
I
I
INPUT
O
V
OUTPUT
I = 7.50 mA
I
I = 3.75 mA
I
V
CC
= 5 V
I
I
= 7.5 mA
100
80
-60 -20 20 60 100
T
A
– TEMPERATURE – °C
60
80400-40
0
t
P
– PROPAGATION DELAY – ns
40
20
t
PLH
, R
L
= 4 KΩ
t
PLH
, R
L
= 1 KΩ
t
PLH
, R
L
= 350 Ω
t
PHL
, R
L
= 350 Ω
1 KΩ
4 KΩ
V
CC
= 5 V
T
A
= 25°C
105
90
5913
I
I
– PULSE INPUT CURRENT – mA
75
15117
30
t
P
– PROPAGATION DELAY – ns
60
45
t
PLH
, R
L
= 4 KΩ
t
PLH
, R
L
= 1 KΩ
t
PLH
, R
L
= 350 Ω
t
PHL
, R
L
= 350 Ω
1 KΩ
4 KΩ
V
CC
= 5 V
I
I
= 7.5 mA
40
30
-20 20 60 100
T
A
– TEMPERATURE – °C
20
80400-40
PWD – PULSE WIDTH DISTORTION – ns
10 R
L
= 350 kΩ
R
L
= 1 kΩ
R
L
= 4 kΩ
0
-60
-10
OUTPUT V
MONITORING
NODE
O
1.5 V
t
EHL
t
ELH
V
E
INPUT
O
V
OUTPUT
3.0 V
1.5 V
+5 V
7
5
6
8
2
3
4
1
PULSE GEN.
Z = 50 Ω
t = t = 5 ns
O
f
I
IL
R
CC
V
0.1 µF
BYPASS
*C
L
*C
L
IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
GND
r
7.5 mA
INPUT V
E
MONITORING NODE
t
E
– ENABLE PROPAGATION DELAY – ns
-60
0
T
A
– TEMPERATURE – °C
100
90
120
-20
30
20 60-40 0 40 80
60
V
CC
= 5 V
V
EH
= 3 V
V
EL
= 0 V
I
I
= 7.5 mA
t
ELH
, R
L
= 4 kΩ
t
ELH
, R
L
= 1 kΩ
t
EHL
, R
L
= 350 Ω, 1 kΩ, 4 kΩ
t
ELH
, R
L
= 350 Ω
11
GND BUS (BACK)
VCC BUS (FRONT)
ENABLE
(IF USED)
0.1µF
OUTPUT 1
NC
NC
ENABLE
(IF USED)
0.1µF
OUTPUT 2
NC
NC
10 mm MAX.
(SEE NOTE 1)
Figure 13. Test circuit for common mode transient immunity and typical waveforms.
Figure 12. Typical rise and fall time vs.
temperature.
t
r
, t
f
– RISE, FALL TIME – ns
-60
0
T
A
– TEMPERATURE – °C
100
300
-20
40
20 60-40 0 40 80
60
290
20
V
CC
= 5 V
I
I
= 7.5 mA
R
L
= 4 kΩ
R
L
= 1 kΩ
R
L
= 350 Ω, 1 kΩ, 4 kΩ
t
RISE
t
FALL
R
L
= 350 Ω
+5 V
7
5
6
8
2
3
4
1
CC
V
0.1 µF
BYPASS
GND
OUTPUT V
MONITORING
NODE
O
PULSE
GENERATOR
Z = 50 Ω
O
+
I
I
B
A
CM
V
–
350 Ω
V
O
0.5 V
O
V (MIN.)
5 V
0 V SWITCH AT A: I = 0 mA
I
SWITCH AT B: I = 7.5 mA
I
CM
V
H
CM
CM
L
O
V (MAX.)
CM
V (PEAK)
V
O
Figure 15. Recommended printed circuit board layout.
Figure 14. Typical input threshold current vs.
temperature.
I
TH
– INPUT THRESHOLD CURRENT – mA
-60
0
T
A
– TEMPERATURE – °C
100
4
5
-20
2
20 60-40 0 40 80
3
V
CC
= 5.0 V
V
O
= 0.6 V
1R
L
= 4 kΩ
R
L
= 1 kΩ
R
L
= 350 Ω
12
Using the HCPL-2602/12 Line
Receiver Optocouplers
The primary objectives to fulfill
when connecting an optocoupler
to a transmission line are to
provide a minimum, but not
excessive, LED current and to
properly terminate the line. The
internal regulator in the HCPL-
2602/12 simplifies this task.
Excess current from variable
drive conditions such as line
length variations, line driver
differences, and power supply
fluctuations are shunted by the
regulator. In fact, with the LED
current regulated, the line current
can be increased to improve the
immunity of the system to
differential-mode-noise and to
enhance the data rate capability.
The designer must keep in mind
the 60 mA input current
maximum rating of the HCPL-
2602/12 in such cases, and may
need to use series limiting or
shunting to prevent overstress.
Design of the termination circuit
is also simplified; in most cases
the transmission line can simply
be connected directly to the input
terminals of the HCPL-2602/12
without the need for additional
series or shunt resistors. If
reversing line drive is used it may
be desirable to use two HCPL-
2602/12 or an external Schottky
diode to optimize data rate.
Polarity Non-Reversing Drive
High data rates can be obtained
with the HCPL-2602/12 with
polarity non-reversing drive.
Figure (a) illustrates how a
74S140 line driver can be used
with the HCPL-2602/12 and
shielded, twisted pair or coax
cable without any additional
components. There are some
reflections due to the “active
termination,” but they do not
interfere with circuit perform-
ance because the regulator
clamps the line voltage. At longer
line lengths, tPLH increases faster
than tPHL since the switching
threshold is not exactly halfway
between asymptotic line
conditions. If optimum data rate
is desired, a series resistor and
peaking capacitor can be used to
equalize tPLH and tPHL. In general,
the peaking capacitance should be
as large as possible; however, if it
is too large it may keep the
regulator from achieving turn-off
during the negative (or zero)
excursions of the input signal. A
safe rule:
make C ≤16t
where:
C = peaking capacitance in
picofarads
t = data bit interval in
nanoseconds
Polarity Reversing Drive
A single HCPL-2602/12 can also
be used with polarity reversing
drive (Figure b). Current reversal
is obtained by way of the
substrate isolation diode
(substrate to collector). Some
reduction of data rate occurs,
however, because the substrate
diode stores charge, which must
be removed when the current
changes to the forward direction.
The effect of this is a longer tPHL.
This effect can be eliminated and
data rate improved considerably
by use of a Schottky diode on the
input of the HCPL-2602/12.
For optimum noise rejection as
well as balanced delays, a split-
phase termination should be used
along with a flip-flop at the output
(Figure c). The result of current
reversal in split-phase operation
is seen in Figure (c) with switches
A and B both OPEN. The coupler
inputs are then connected in
ANTI-SERIES; however, because
of the higher steady-state termina-
tion voltage, in comparison to the
single HCPL-2602/12 termination,
the forward current in the
substrate diode is lower and
consequently there is less junction
charge to deal with when
switching.
Closing switch B with A open is
done mainly to enhance common
mode rejection, but also reduces
propagation delay slightly because
line-to-line capacitance offers a
slight peaking effect. With
switches A and B both CLOSED,
the shield acts as a current return
path which prevents either input
substrate diode from becoming
reversed biased. Thus the data
rate is optimized as shown in
Figure (c).
Improved Noise Rejection
Use of additional logic at the
output of two HCPL-2602/12s,
operated in the split phase
termination, will greatly improve
system noise rejection in addition
to balancing propagation delays
as discussed earlier.
A NAND flip-flop offers infinite
common mode rejection (CMR)
for NEGATIVELY sloped common
mode transients but requires tPHL
> tPLH for proper operation. A NOR
flip-flop has infinite CMR for
POSITIVELY sloped transients
but requires tPHL < tPLH for proper
operation. An exclusive-OR flip-
flop has infinite CMR for common
mode transients of EITHER
polarity and operates with either
tPHL >t
PLH or tPHL <t
PLH.
With the line driver and
transmission line shown in Figure
(c), tPHL > tPLH, so NAND gates are
preferred in the R-S flip-flop. A
higher drive amplitude or
13
Figure b. Polarity reversing, single ended.
Figure a. Polarity non-reversing.
Figure c. Polarity reversing, split phase.
Figure d. Flip-flop configurations.
< 1
< 1
14
different circuit configuration
could make tPHL <t
PLH, in which
case NOR gates would be pre-
ferred. If it is not known whether
tPHL > tPLH or tPHL < tPLH, or if the
drive conditions may vary over the
boundary for these conditions, the
exclusive-OR flip-flop of Figure (d)
should be used.
RS-422 and RS-423
Line drivers designed for RS-422
and RS-423 generally provide
adequate voltage and current for
operating the HCPL-2602/12. Most
drivers also have characteristics
allowing the HCPL-2602/12 to be
connected directly to the driver
terminals. Worst case drive
conditions, however, would
require current shunting to
prevent overstress of the HCPL-
2602/12.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay Skew
Propagation delay is a figure of
merit which describes how quickly
a logic signal propagates through a
system. The propagation delay
from low to high (tPLH) is the
amount of time required for an
input signal to propagate to the
output, causing the output to
change from low to high. Similarly,
the propagation delay from high to
low (tPHL) is the amount of time
required for the input signal to
propagate to the output, causing
the output to change from high to
low (see Figure 6).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ in
value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being
transmitted. Typically, PWD on
the order of 20-30% of the
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-1, etc.).
Propagation delay skew, tPSK, is an
important parameter to consider
in parallel data applications
where synchronization of signals
on parallel data lines is a concern.
If the parallel data is being sent
through a group of optocouplers,
differences in propagation delays
will cause the data to arrive at the
outputs of the optocouplers at
different times. If this difference
in propagation delays is large
enough, it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is defined
as the difference between the
minimum and maximum
propagation delays, either tPLH or
tPHL, for any given group of
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
operating temperature). As
illustrated in Figure 16, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, tPSK is the
difference between the shortest
propagation delay, either tPHL or
tPHL, and the longest propagation
delay, either tPLH or tPHL.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 17
is the timing diagram of a typical
parallel data application with
both the clock and the data lines
being sent through optocouplers.
The figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
Propagation delay skew
represents the uncertainty of
where an edge might be after
being sent through an
optocoupler. Figure 17 shows that
there will be uncertainty in both
the data and the clock lines. It is
important that these two areas of
uncertainty not overlap,
otherwise the clock signal might
arrive before all of the data
outputs have settled, or some of
the data outputs may start to
change before the clock signal has
arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice tPSK. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
The tPSK specified optocouplers
offer the advantages of
guaranteed specifications for
propagation delays, pulse-width
distortion and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
15
Figure 16. Illustration of propagation delay skew - tPSK.Figure 17. Parallel data transmission example.
DATA
t
PSK
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
50%
1.5 V
I
I
V
O
50%I
I
V
O
t
PSK
1.5 V
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2154EN
AV01-0568EN July 18, 2007
