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4
OPERATING
CONSIDERATIONS PA04 • PA04A
GENERAL
Please read Application Note 1 "General Operating Con-
siderations" which covers stability, supplies, heat sinking,
mounting, current limit, SOA interpretation, and specication
interpretation. Visit www.apexmicrotech.com for design tools
that help automate tasks such as calculations for stability,
internal power dissipation, current limit; heat sink selection;
Apex’s complete Application Notes library; Technical Seminar
Workbook; and Evaluation Kits.
CURRENT LIMIT
The two current limit sense lines are to be connected directly
across the current limit sense resistor. For the current limit to
work correctly pin 11 must be connected to the amplier out-
put side and pin 10 connected to the load side of the current
limit resistor, RCL, as shown in Figure 1. This connection will
bypass any parasitic resistances, Rp, formed by sockets and
solder joints as well as internal amplier losses. The current
limiting resistor may not be placed anywhere in the output
circuit except where shown in Figure 1.
The value of the current limit resistor can be calculated as
follows:
.76
RCL =
ILIMIT
Figure 1.
Current Limit.
SAFE OPERATING AREA (SOA)
The MOSFET output stage of this power operational ampli-
er has two distinct limitations:
1. The current handling capability of the MOSFET geometry
and the wire bonds.
2. The junction temperature of the output MOSFETs.
NOTE: The output stage is protected against transient y-
back. However, for protection against sustained, high
energy yback, external fast-recovery diodes should
be used.
SLEEP MODE OPERATION
In the sleep mode, pin 12 (sleep) is tied to pin 9 (+VBOOST).
This disables the amplier’s internal reference and the am-
plier shuts down except for a trickle current of 3 mA which
ows into pin 12. Pin 12 should be left open if the sleep mode
is not required.
Several possible circuits can be built to take advantage of
this mode. In Figure 2A a small signal relay is driven by a logic
gate. This removes the requirement to deal with the common
mode voltage that exists on the shutoff circuitry since the sleep
mode is referenced to the +VBOOST voltage.
In Figure 2B, circuitry is used to level translate the sleep
mode input signal. The differential input activates sleep mode
with a differential logic level signal and allows common mode
voltages to ±VBOOST.
BOOST OPERATION
With the VBOOST feature the small signal stages of the
amplier are operated at higher supply voltages than the
amplier’s high current output stage. +VBOOST (pin 9) and
–VBOOST (pin 5) are connected to the small signal circuitry of
the amplier. +VS (pin 8) and –VS (pin 6) are connected to the
high current output stage. An additional 5V on the VBOOST pins
is sufcient to allow the small signal stages to drive the output
transistors into saturation and improve the output voltage
swing for extra efcient operation when required. When close
swings to the supply rails is not required the +VBOOST and +VS
pins must be strapped together as well as the –VBOOST and –VS
pins. The boost voltage pins must not be at a voltage lower
than the VS pins.
COMPENSATION
The external compensation components CC and RC are con-
nected to pins 3 and 4. Unity gain stability can be achieved at
any compensation capacitance greater than 330 pF with at
least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate. Use the typical operating curves as
a guide to select CC and RC for the application.
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This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.
PA04U REV K OCTOBER 2006 © 2006 Apex Microtechnology Corp.