Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor MT9V135 1/4-Inch VGA CMOS Image Sensor Limited Data Sheet A Complete On-Chip VGA Camera Solution with Digital and Composite Video Output Micron's MT9V135 is a VGA-format, single-chip camera CMOS active-pixel digital image sensor. It captures high-quality color images at VGA resolution and outputs NTSC or PAL interlaced composite video and CCIR 656 digital composite video. The MT9V135 is a complete camera-ona-chip solution. It incorporates sophisticated camera functions and is programmable through a simple two-wire serial interface. Applications Parameters * Security surveillance cameras (incl. CCTV) * Active or passive overlay cameras * Wireless, smart, and evidencequality cameras * Composite and digital video Features * Micron(R) DigitalClarity(R) CMOS imaging technology * System-on-a-chip (SOC)-- completely integrated camera system * NTSC/PAL (true two-field) analog composite video output * ITU-R BT.656 parallel output (8-bit, interlaced) * Simultaneous composite and digital video outputs (simplifies focus and setup of network cameras) * Serial LVDS data output * Low power, interlaced scan CMOS image sensor * Superior low-light performance * Supports use of external devices for addition of custom overlay graphics * Image flow processor (IFP) for sophisticated processing * Color recovery and correction, sharpening, gamma, lens shading correction, and onthe-fly defect correction * Automatic features: auto exposure, auto white balance (AWB), auto black reference (ABR), auto flicker avoidance, auto color saturation, and auto defect identification and correction * Simple two-wire serial programming interface Ordering Information Part Number MT9V135L12STC ES MT9V135L12STCD MT9V135L12STCH Description 48-Pin LLCC ES, Pb-Free Demo kit Demo kit headboard Optical format Active imager size Active pixels 1/4-inch (4:3) 3.63mm(H) x 2.78mm(V) 4.57mm diagonal 640H x 480V NTSC output PAL output 720H x 486V 720H x 576V Pixel size Color filter array Shutter type 5.6m x 5.6m RGB paired Bayer pattern Electronic rolling shutter (ERS) Maximum data rate/ 13.5 Mp/s, master clock 27 MHz Frame rate - VGA 30 fps at 27 MHz (NTSC) (640H x 480V) 25 fps at 27 MHz (PAL) Integration time 16s-33ms (NTSC) (composite video) 16s-40ms (PAL) ADC resolution 10-bit, on-chip Responsivity 2.8 V/lux-s (550nm) Dynamic range 73.4dB 38.8dB SNRMAX Supply I/O digital 2.5V-3.1V (2.8V nominal) voltage Core digital 2.5V-3.1V (2.8V nominal) Analog 2.5V-3.1V (2.8V nominal) Power consumption 344 mW at 2.8V, 25C -30C to +70C Operating temp.1 Packaging 48-pin LLCC Notes: 1. For a greater temperature range, consider using MT9V125. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief General Description General Description The MT9V135 is a VGA CMOS image sensor featuring Micron's breakthrough DigitalClarity technology--a low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low power, and integration advantages of CMOS. The MT9V135 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correction, auto white balance (AWB), and on-the-fly defect identification and correction. The MT9V135 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and PAL video formats. The MT9V135 also includes digital video output that can be switched to the NTSC/PAL encoder. This can be used in conjunction with an external digital signal processor (DSP) to provide an overlay (such as a logo or a menu screen) on top of the live video. The image data can be output on any one of three output ports: * Composite analog video (single-ended and differential support) * Low-voltage differential signaling (LVDS) * CCIR 656 interlaced digital video in parallel 8-bit format Table 1: MT9V135 Detailed Performance Parameters Parameter Value TBD 28 e-/LSB 6 e-RMS at 16X 119 e-/pix/s at 55C Effective fill factor (with microlens) Output gain Read noise Dark current Figure 1: MT9V135 Quantum Efficiency Versus Wavelength PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Functional Overview Functional Overview The MT9V135 is a fully-automatic, single-chip camera, requiring only a single power supply, lens, and clock source for basic operation. Output video is streamed via the chosen output port. The MT9V135 internal registers are configured using a two-wire serial interface. The device can be put into a low-power sleep mode by asserting STANDBY and shutting down the clock. Output signals can be tri-stated. Both tri-stating output signals and entry into standby mode can be achieved via two-wire serial interface register writes. The MT9V135 requires an input clock of 27 MHz to support correct NTSC or PAL timing. Internal Architecture Internally, the MT9V135 consists of a sensor core and an image flow processor (IFP). The IFP is divided in two sections, the color pipe and the camera controller. The sensor core captures raw images that are then input into the IFP. The color pipe section processes the incoming stream to create interpolated, color-corrected output, and the camera controller section controls the sensor core to maintain the desired exposure and color balance. The IFP scales the image and an integrated video encoder generates either NTSC or PAL analog composite output. The MT9V135 supports three different output ports; analog composite video out, LVDS serial out and CCIR 656 interlaced digital video in parallel 8bit format. Figure 2 shows the major functional blocks of the MT9V135. The built-in NTSC/PAL encoder and the LVDS formatter allow simultaneous outputs of composite and digital video signals. This is especially useful during installation of network cameras and allows the installer to adjust the camera view and focus using analog monitoring equipment while the digital video is compressed and formatted for IP network delivery. Figure 2: SCLK SDATA EXTCLK STANDBY Functional Block Diagram Sensor Core SRAM Line Buffers Pixel Data . 640H x 480V . 1/4-inch optical format . True interlaced readout . Auto black compensation . Programmable analog gain . Programmable exposure . 10-bit ADC LVDS Formatter and Driver LVDS_OUT_POS LVDS_OUT_NEG Control Bus Control Bus + Sensor control (gains, shutter, etc.) NTSC/PAL Encoder and DAC DIN[7:0] DAC_OUT_POS DAC_OUT_NEG DIN_CLK Image Flow Processor Camera Control VDD/DGND VAA /AGND VAAPIX Control Bus Auto exposure Auto white balance Flicker detect/avoid PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN Image Data Image Flow Processor Colorpipe Lens shading correction Color interpolation Defect correction Color correction Horizontal Interpolator Gamma correction Color conversion + formatting 3 DOUT0[7:0] PIXCLK FRAME_VALID LINE_VALID Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Functional Overview Figure 3 shows a typical application using a DSP to produce a video overlay (such as a logo or menu text). The parallel digital video output is sent to the DSP, which adds the overlay. The digital video with the overlay is then looped back into the MT9V135 to the NTSC/PAL encoder and LVDS formatter to provide simultaneous composite analog and digital LVDS outputs. Figure 3: Typical Usage Configuration with Overlay NTSC/PAL composite analog output with overlay DIN_CLK PIXCLK MT9V135 DIN[7:0] DOUT[7:0] Parallel digital (CCIR 656) 27MHz Oscillator PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 4 DSP Parallel digital signal with overlay (CCIR 656) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Typical Connections Typical Connections Figure 4 shows a detailed MT9V135 device configuration. For low-noise operation, the MT9V135 requires separate analog and digital power supplies. Incoming digital and analog ground conductors can be tied together next to the die. Power supply voltages VAA (the primary analog voltage) and VAAPIX (the main voltage to the pixel array) must be tied together to avoid current loss. Both power supply rails should be decoupled to ground using capacitors. The MT9V135 requires a single external voltage supply level. Typical Configuration (without use of overlay) VAA AND VAAPIX5 Power VDD VDD_DAC VDD_PLL VAA 1.5K2 VAAPIX 75 Terminated Receiver DAC_POS DAC_NEG SADDR STANDBY from Controller or Digital GND DAC_REF 2.8K STANDBY1 Master Clock CLKIN Two-Wire Serial Interface SDATA SCLK LVDS_POS LVDS_NEG LVDS_ENABLE 1K DIN_CLK DIN[7:0] HORIZ_FLIP NTSC_PAL_SELECT DOUT[7:0] DOUT_LSB[1:0] PIXCLK LINE_VALID FRAME_VALID PEDESTAL RSVD RESET# 10F DGND AGND DGND AGND VAAPIX VDD 1F 0.1F 75 1.5K2 VDD VDD_DAC VDD_PLL Power Power Power 0.1F VAA 1F AGND DGND 75 Figure 4: 0.1F 1F AGND Notes: 1. MT9V135 STANDBY can be connected directly to the customer's ASIC controller or to DGND, depending on the controller's capability. 2. A 1.5K resistor value is recommended, but may be greater for slower (e.g., 100Kb) twowire speed. 3. LVDS_ENABLE should be tied HIGH if LVDS is to be used. 4. Pull down DAC_REF with a 2.8K resistor for 1.0V peak-to-peak video output. For a 1.4V peak-to-peak video output, change the video resistor to 2.4K. 5. VAA and VAAPIX must be tied to the same potential for proper operation. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Typical Connections Table 2: DOUT[0] 48 47 46 PIXCLK DOUT[1] 1 DOUT_LSB1 DOUT[2] 2 DOUT_LSB0 DOUT[3] 3 45 44 43 7 42 FV DIN[5] 8 41 LV DIN[4] 9 40 VDDPLL DIN[3] 10 39 LVDS_POS DIN[2] 11 38 LVDS_NEG DIN[1] 12 37 DGND VDD DAC_POS 17 32 DGND STANDBY 18 31 DAC_REF 20 SDATA 19 21 22 23 24 25 26 27 28 29 30 AGND CLKIN VAAPIX VDD DAC_NEG VAA VDDDAC 33 PEDESTAL 34 16 LVDS_ENABLE 15 NTSC_PAL_SELECT DGND HORIZ_FLIP 35 RSVD 14 SADDR 13 DIN_CLK SCLK DIN[0] 36 Pin Descriptions Name Type 17 19 22 23 21 18 CLKIN RESET_BAR SADDR RSVD SCLK STANDBY Input Input Input Input Input Input 24 HORIZ_FLIP Input 25 NTSC_PAL_S ELECT PEDESTAL Input LVDS_ENAB LE Input 26 4 DIN[6] Pin Assignmen t 27 DOUT[4] 5 DOUT[6] DOUT[7] 6 DOUT[5] DIN[7] 48-pin LLCC Assignment RESET_BAR Figure 5: PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN Input Description Master clock in sensor. Active LOW: asynchronous reset. Two-wire serial interface device ID selection 1:0xBA, 0:0x90. Must be attached to DGND. Two-wire serial interface clock. Multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). If "0" at reset: Default horizontal setting. If "1" at reset: Flips the image readout format in the horizontal direction. If "0" at reset: Default NTSC mode. If "1" at reset: Default PAL mode. If "0" at reset: Does not add pedestal to composite video output. If "1" at reset: Adds pedestal to composite video output. Valid for NTSC only, pull low for PAL operation. Active HIGH: Enables the LVDS output port. Must be high if LVDS is to be used. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Typical Connections Table 2: Pin Assignmen t Pin Descriptions (continued) Name Type DIN[7:0] Input 6, 7, 8, 9, 10, 11, 12, 13 14 20 5, 4, 3, 2, 1, 48, 47, 46 44 DIN_CLK SDATA DOUT[7:0] Input Output Output DOUT_LSB0 Output 45 DOUT_LSB1 Output 42 Output 41 43 35 FRAME_VAL ID LINE_VALID PIXCLK DAC_POS 33 31 39 38 29 15, 32, 37 28 30 16, 36 34 40 DAC_NEG DAC_REF LVDS_POS LVDS_NEG AGND DGND VAA VAAPIX VDD VDDDAC VDDPLL Output Output Output Output Supply Supply Supply Supply Supply Supply Supply Output Output Output Description External data input port selectable at video encoder input. DIN capture clock. (This clock must be synchronous to CLKIN.) Two-wire serial interface data I/O. Pixel Data Output DOUT7 (most significant bit (MSB)), DOUT0 (least significant bit (LSB)). Data output [9:2] in sensor stand-alone mode. Sensor stand-alone mode output 0--typically left unconnected for normal SOC operation. Sensor stand-alone mode output 1--typically left unconnected for normal SOC operation. Active HIGH: FRAME_VALID; indicates active frame. Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. Pixel clock output. Positive video DAC output in differential mode. Video DAC output in single-ended mode. Negative video DAC output in differential mode. External reference resistor for video DAC. LVDS positive output. LVDS negative output. Analog ground. Digital ground. Analog power: 2.5V-3.1V (2.8V nominal). Pixel array analog power supply: 2.5V-3.1V (2.8V nominal). Digital power: 2.5V-3.1V (2.8V nominal). DAC power: 2.5V-3.1V (2.8V nominal). LVDS PLL power: 2.5V-3.1V (2.8V nominal). Notes: 1. ALL power pins (VDD/VDDDAC/VDDPLL/VAA/VAAPIX) must be connected to 2.8V (nominal). Power pins cannot be floated. 2. ALL ground pins (AGND/DGND) must be connected to ground. Ground pins cannot be floated. 3. Inputs are not tolerant to signal voltages above 3.1V. 4. All unused inputs must be tied to GND or VDD. 5. VAA and VAAPIX must be tied to the same potential for proper operation. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Detailed Architecture Overview Sensor Core The sensor consists of a pixel array of 695 x 512, an analog readout chain, 10-bit ADC with programmable gain and black offset, and timing and control, as illustrated in Figure 6. Figure 6: Sensor Core Block Diagram Active Pixel Sensor (APS) Array Control Register Communication Bus to IFP Timing and Control Clock Sync Signals Analog Processing ADC 10-Bit Data to IFP There are 649 columns by 498 rows of optically-active pixels that include a pixel boundary around the VGA (640 x 480) image to avoid boundary effects during color interpolation and correction. The one additional active column and two additional active rows are used to enable horizontally and vertically mirrored readout to start on the same color pixel. Figure 7 on page 9 illustrates the process of capturing the image. The original scene is flipped and mirrored by the sensor optics. Sensor readout starts at the lower right hand corner. The image is presented in true orientation by the output display. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Figure 7: Image Capture Example SCENE (Front view) fI so es oc Pr e ag m in er th Ga OPTICS g d an (Rear view) e IMAGE CAPTURE ag Im IMAGE SENSOR isp D Row by Row y la Start Rasterization Start Readout IMAGE RENDERING DISPLAY (Front view) The sensor core uses a paired RGB Bayer color pattern, as shown in Figure 8 on page 10. Row pairs consist of the following: rows 0, 1, rows 2, 3, rows 4, 5, etc. The even-numbered row pairs (0/1, 4/5, etc.) in the active array contain green and red color pixels. The oddnumbered row pairs (2/3, 6/7, etc.) contain blue and green color pixels. The odd-numbered columns contain green and blue color pixels; even-numbered columns contain red and green color pixels. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Figure 8: Pixel Color Pattern Detail (top right corner) Column Readout Direction .. . Black Pixels G R G R G R G Row Readout Direction First Active Border Pixel (42, 13) G R G R G R G ... B G B G B G B B G B G B G B G R G R G R G G R G R G R G Output Data Format The sensor core image data is read out in an interlaced scan order. Progressive readout-- which is not supported by the color pipe--is an option, but is only intended for raw data output. Valid image data is surrounded by horizontal and vertical blanking, shown in Figure 9 on page 11. For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of the image field. For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical size is 288 pixels per field; 240 image pixels with 24 dark pixels at the top of the image and 24 dark pixels at the bottom of the image field. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Figure 9: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P2,0 P2,1 P2,2.....................................P2,n-1 P2,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE ODD FIELD HORIZONTAL BLANKING Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL EVEN BLANKING VERTICAL/HORIZONTAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 P1,0 P1,1 P1,2.....................................P1,n-1 P1,n P3,0 P3,1 P3,2.....................................P3,n-1 P3,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE EVEN FIELD HORIZONTAL BLANKING Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n 00 00 00 .................. 00 00 00 PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL ODD BLANKING VERTICAL/HORIZONTAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Image Flow Processor The MT9V135 IFP consists of a color processing pipeline, and a measurement and control logic block (the camera controller). The stream of raw data from the sensor enters the pipeline and undergoes several transformations. Image stream processing starts with conditioning the black level and applying a digital gain. The lens shading block compensates for signal loss caused by the lens. Next, the data is interpolated to recover missing color components for each pixel. The resulting interpolated RGB data passes through the current color correction matrix (CCM) as well as the gamma and saturation corrections, and is formatted for final output. The measurement and control logic continuously accumulate image brightness and color statistics. Based on these measurements, the IFP calculates updated values for exposure time and sensor analog gains that are sent to the sensor core via the control bus. Black Level Conditioning The sensor core black level calibration works to maintain black pixel values at a constant level, independent of analog gain, reference current, voltage settings, and temperature conditions. If this black level is above zero, it must be reduced before color processing can begin. The black level subtraction block in the IFP re-maps the black level of the sensor to zero prior to lens shading correction. Following lens shading correction, the black level addition block provides capability for another black level adjustment. However, for good contrast, this level should be set to zero. Digital Gain Controlled by auto exposure logic, the input digital gain stage amplifies the raw image in low-light conditions (range: x1-x8). Test Pattern A built-in test pattern generator produces a test image stream that can be multiplexed with the gain stage. The test pattern can be selected through register settings. Lens Shading Correction (LC) Inexpensive lenses tend to attenuate image intensity near the edges of pixel arrays. Other factors also cause signal and coloration differences across the image. The net result of all these factors is known as lens shading. Lens shading correction (LC) compensates for these differences. Typically, the profile of lens-shading-induced anomalies across the frame is different for each color component. Therefore, lens shading correction is independently calibrated for the color channels. Interpolation and Aperture Correction A demosaic engine converts the single-color-per-pixel Bayer data from the sensor into RGB (10-bit per color channel). The demosaic algorithm analyzes neighboring pixels to generate a best guess for the missing color components. Edge sharpness is preserved as much as possible. Aperture correction sharpens the image by an adjustable amount. To avoid amplifying noise, sharpening can be programmed to phase out as light levels drop. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Defect Correction This device supports 2D defect correction. In 2D defect detection/correction, pixels with values different from their neighbors by greater than a defined threshold are considered defects unless near the image boundary. The approach is termed 2D, as pixels on neighboring lines as well as neighboring pixels on the same line are considered in both detection and correction. Color Correction To obtain good color rendition and saturation, it is necessary to compensate for the differences between the spectral characteristics of the imager color filter array and the spectral response of the human eye. This compensation, also known as color separation, is achieved through linear transformation of the image with a 3 x 3 element color correction matrix. The optimal values for the color correction coefficients depend on the spectra of the incident illumination and can be programmed by the user. Color Saturation Control Both color saturation and sharpness enhancement can be set by the user, or adjusted automatically by tracking the magnitude of the gains used by the auto exposure algorithm. Automatic White Balance (AWB) The MT9V135 has a built-in AWB algorithm designed to compensate for the effects of changing scene illumination the color rendition quality. This sophisticated algorithm consists of three major sub-modules: * A measurement engine (ME) performing statistical analysis of the image * A module selecting the optimal color correction matrix * A module selecting analog color channel gains in the sensor core While the default algorithm settings are adequate in most situations, the user can reprogram base color correction matrices and limit color channel gains. The AWB does not attempt to locate the brightest or grayest elements in the image; it performs in-depth image analysis to differentiate between changes in predominant spectra of illumination and changes in predominant scene colors. Factory defaults are suitable for most applications, however, a wide range of algorithm parameters can be overwritten by the user through the serial interface. Auto Exposure The auto exposure algorithm performs automatic adjustments to image brightness by controlling exposure time and analog gains in the sensor core, as well as digital gain applied to the image. The algorithm relies on the auto exposure measurement engine that tracks speed and amplitude changes in the overall luminance of selected windows in the image. Backlight compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. Other algorithm features include: fast-fluctuating illumination rejection (time averaging), response-speed control, and controlled sensitivity to small changes. While the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters as described above. The auto exposure algorithm enables compensation for a broad range of illumination intensities. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Detailed Architecture Overview Automatic Flicker Detection Flicker occurs when integration time is not an integer multiple of the period of the light intensity. Automatic flicker detection block does not compensate for the flicker; it reduces flicker occurrence by detecting flicker frequency and adjusting the integration time. For integration times shorter than the light intensity period (10ms for 50Hz environments and 8.33ms for 60Hz environments), flicker is unavoidable. Gamma Correction To achieve more life-like quality in an image, the IFP includes gamma correction and color saturation control. Gamma correction operates on the luminance component of the image and enables compensation for non-linear dependence of the display device output versus the driving signal (e.g., monitor brightness versus CRT voltage). In addition, gamma correction provides range compression, converting 10-bit luminance input to 8-bit output. Pre-gamma image processing generates 10-bit luminance values ranging from 0 to 896. Piece-wise linear gamma correction utilized in this imager has ten linear intervals, with end points corresponding to the following input values: Xi=0...10={0,16,32,64,128,256,384,512,640,768,896}. For each input value Xi, the user can program the corresponding output value Yi. Yi values must be monotonically increasing. NTSC/PAL Encoder The MT9V135 has an on-chip video encoder to format the data stream for composite video output in the supported NTSC or PAL formats. The encoder expects CCIR-656 interlaced NTSC or PAL data stream input. By default, the input is taken from the onchip image stream. Input can also be taken from the external DIN port for external image processing used with the on-chip video encoder and composite output. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_2.fm - Rev. A 8/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Electrical Specifications Electrical Specifications Table 3: Electrical Characteristics and Operating Conditions TA = 25C Parameter1 I/O and core digital voltage (VDD) LVDS PLL voltage Video DAC voltage Analog voltage (VAA) Pixel supply voltage (VAAPIX) Leakage current Imager operating temperature2 Storage temperature Condition Min Typ Max Unit n/a n/a n/a n/a n/a STANDBY, no clocks n/a n/a 2.5 2.5 2.5 2.5 2.5 - -30 -30 2.8 2.8 2.8 2.8 2.8 - - - 3.1 3.1 3.1 3.1 3.1 10 +70 +125 V V V V V A C C Notes: 1. VDD, VAA, and VAAPIX must all be at the same potential to avoid excessive current draw. If all three supplies are tied together, care must be taken to avoid excessive noise injection in the analog supplies. 2. Customers requiring a similar part with greater temperature range should consider using the MT9V125. Table 4: Video DAC Electrical Characteristics TA = 25C; All table values are estimates until the block is tested and characterized. Parameter Condition Resolution DNL INL Output local load Single-ended mode Single-ended mode Single-ended mode, output pad (DAC_POS) Single-ended mode, unused output (DAC_NEG) Output voltage Single-ended mode, code 000h Single-ended mode, code 3FFh Output current Single-ended mode, code 000h Single-ended mode, code 3FFh DNL Differential mode INL Differential mode Output local load Differential mode per pad (DAC_POS and DAC_NEG) Output voltage Differential mode, code 000h, pad dacp Differential mode, code 000h, pad dacn Differential mode, code 3FFh, pad dacp Differential mode, code 3FFH, pad dacn Output voltage Differential mode, code 000h, pad dacp Differential mode, code 000h, pad dacn Differential mode, code 3FFh, pad dacp Differential mode, code 3FFH, pad dacn Differential output Differential mode mid level Supply current Estimate PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_3.fm - Rev. A 8/06 EN 15 Min Typ Max Unit - - - - - - - - - - - - 10 0.8 5.7 75 0 0.02 1.42 0.6 37.9 0.7 1.4 37.5 - 1.1 8.1 - - - - - - 1 3 - bits bits bits ohms ohms V V mA mA bits bits ohms - - - - - - - - - 0.37 1.07 1.07 0.37 0.6 37.9 37.9 0.6 0.72 - - - - - - - - - V V V V mA mA mA mA V - - 55 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Electrical Specifications Table 5: Signal Digital I/O Parameters Parameter All Outputs All Inputs EXTCLK Definitions Condition Load capacitance Output signal slew VOH VOL IOH IOL VIH VIL IIN Signal CAP freq Output high voltage Output low voltage Output high current Output low current Input high voltage Input low voltage Input leakage current Input signal capacitance Master clock frequency PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_3.fm - Rev. A 8/06 EN 2.8V, 30pF load 2.8V, 5pF load VDD = 2.8V, VOH = 2.4V VDD = 2.8V, VOL = 0.4V VDD = 2.8V VDD = 2.8V Absolute minimum VGA at 30 fps 16 Min Typ Max Unit 1 - - 2.5 -0.3 16 15.9 1.48 - -2 - 2 - - 0.72 1.25 2.8 - - - - - - 3.5 - 27 30 - - 3.1 0.3 26.5 21.3 - 1.43 2 - - - pF V/ns V/ns V V mA mA V V A pF MHz MHz Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V135: 1/4-Inch VGA SOC Digital Image Sensor Brief Package and Die Diagrams Package and Die Diagrams Figure 10: 48-Pin LLCC Package Outline Drawing 2.35 0.15 D SEATING PLANE SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: PLASTIC LAMINATE LID MATERIAL: BOROSILICATE GLASS 0.55 THICKNESS A 8.8 0.8 TYP 47X 0.93 0.15 48 0.075 TYP C B 5.715 OPTICAL CENTER1 1 48X 0.40 0.05 5.715 OPTICAL CENTER1 48X R 0.175 1.92 0.15 CL 8.8 FIRST CLEAR PIXEL 10.9 CTR 11.43 0.10 0.8 TYP 4.4 CL OPTICAL AREA 1.45 0.125 4.4 11.43 0.10 LEAD FINISH: Au PLATING, 0.50 MICRONS MINIMUM THICKNESS OVER Ni PLATING, 5 MICRONS MINIMUM THICKNESS 10.9 CTR 0.90 FOR REFERENCE ONLY 0.35 FOR REFERENCE ONLY OPTICAL AREA: MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES B AND C : 1 MAXIMUM TILT OF OPTICAL AREA RELATIVE TO SEATING PLANE A : 50 MICRONS MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS D : 100 MICRONS Notes: 1. Optical center position relative to the package center = 0.10 (X,Y). 2. All dimensions in millimeters. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef824c99cd/Source: 09005aef824d23dd MT9V135_PB_3.fm - Rev. A 8/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.