TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
80-mΩ High-Side MOSFET Switch
D
500 mA Continuous Current Per Channel
D
Independent Thermal and Short-Circuit
Protection With Overcurrent Logic Output
D
Operating Range . . . 2.7 V to 5.5 V
D
CMOS- and TTL-Compatible Enable Inputs
D
2.5-ms Typical Rise Time
D
Undervoltage Lockout
D
10 µA Maximum Standby Supply Current
for Single and Dual (20 µA for Triple and
Quad)
D
Bidirectional Switch
D
Ambient Temperature Range, 0°C to 85°C
D
ESD Protection
D
UL Listed – File No. E169910
description
The TPS2041A through TPS2044A and
TPS2051A through TPS2054A power-distribution
switches are intended for applications where
heavy capacitive loads and short circuits are likely to be encountered. These devices incorporate 80-mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches in a single package. Each switch is controlled by an independent logic enable input. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, these devices limit the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low .
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. These power-distribution switches are designed to current limit
at 0.9 A.
TPS201xA
TPS202x
TPS203x
33 mΩ, single 0.2 A – 2 A
0.2 A – 2 A
0.2 A – 2 A
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
80 mΩ, single 600 mA
1 A
500 mA
500 mA
250 mA
250 mA
GENERAL SWITCH CATALOG
TPS2042
TPS2052
TPS2046
TPS2056
80 mΩ, dual 500 mA
500 mA
250 mA
250 mA
TPS2100/1
260 mΩIN1 500 mA
IN2 10 mA
OUT
IN1
IN2 TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
1.3 Ω
TPS2043
TPS2053
TPS2047
TPS2057
80 mΩ, triple
500 mA
500 mA
250 mA
250 mA
TPS2044
TPS2054
TPS2048
TPS2058
80 mΩ, quad
500 mA
500 mA
250 mA
250 mA
80 mΩ, dual
TPS2080
TPS2081
TPS2082
TPS2090
500 mA
500 mA
500 mA
250 mA
TPS2091
TPS2092 250 mA
250 mA
80 mΩ, quad
TPS2085
TPS2086
TPS2087
TPS2095
500 mA
500 mA
500 mA
250 mA
TPS2096
TPS2097 250 mA
250 mA
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN
IN
EN†
OUT
OUT
OUT
OC
TPS2041A, TPS2051A
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
EN1†
EN2†
OC1
OUT1
OUT2
OC2
TPS2042A, TPS2052A
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1†
EN2†
GNDB
IN2
EN3†
EN4†
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
TPS2044A, TPS2054A
D PACKAGE
(TOP VIEW)
†All enable inputs are active high for the TPS205xA series.
NC – No connect
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1†
EN2†
GNDB
IN2
EN3†
NC
OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC
TPS2043A, TPS2053A
D PACKAGE
(TOP VIEW)
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM CONTINUOUS
TYPICAL SHORT-CIRCUIT
NUMBER OF
PACKAGED DEVICES
TAENABLE
MAXIMUM
CONTINUOUS
LOAD CURRENT
(A)
CURRENT LIMIT AT 25°C
(A)
NUMBER
OF
SWITCHES SOIC
(D)†
Active low
Single
TPS2041AD
Active high
Single
TPS2051AD
Active low
Dual
TPS2042AD
0
°
Cto85
°
C
Active high
05
09
D
u
al
TPS2052AD
0°C
to
85°C
Active low
0
.
5
0
.
9
Tri
p
le
TPS2043AD
Active high
Triple
TPS2053AD
Active low
Quad
TPS2044AD
Active high
Q
u
ad
TPS2054AD
†The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2041ADR)
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
TPS2041A
OUT
OC
IN
EN‡
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
‡Active high for TPS205xA series
†Current sense
TPS2042A
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GND
EN1‡
IN
EN2‡
OC1
OUT1
OUT2
OC2
‡Active high for TPS205xA series
†Current sense
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
TPS2043A
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO
CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1‡
IN1
EN2‡
OC1
OUT1
OUT2
OC2
OUT3
OC3
IN2
EN3‡
GNDB
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
‡Active high for TPS205xA series
†Current sense
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1‡
IN1
EN2‡
OC1
OUT
1
OUT
2
OC2
Thermal
Sense
Driver Current
Limit
Charge
Pump
UVLO CS †
Driver Current
Limit
CS †
Thermal
Sense
Charge
Pump
Power Switch
GNDB
EN3‡
IN2
EN4‡
OC3
OUT3
OUT4
OC4
TPS2044A
‡Active high for TPS205xA series
†Current sense
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TPS2041A and TPS2051A
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2041A TPS2051A
EN 4 – I Enable input. Logic low turns on power switch.
EN – 4 I Enable input. Logic high turns on power switch.
GND 1 1 I Ground
IN 2, 3 2, 3 IInput voltage
OC 5 5 O Overcurrent. Logic output active low
OUT 6, 7, 8 6, 7, 8 OPower-switch output
TPS2042A and TPS2052A
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2042A TPS2052A
EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent. Logic output active low, for power switch, IN-OUT1
OC2 5 5 O Overcurrent. Logic output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TPS2043A and TPS2053A
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2043A TPS2053A
EN1 3 – I Enable input, logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input, logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input, logic low turns on power switch, IN2-OUT3.
EN1 – 3 I Enable input, logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input, logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input, logic high turns on power switch, IN2-OUT3.
GNDA 1 1 Ground for IN1 switch and circuitry.
GNDB 5 5 Ground for IN2 switch and circuitry.
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
NC 8, 9, 10 8, 9, 10 No connection
OC1 16 16 OOvercurrent, logic output active low, IN1-OUT1
OC2 13 13 OOvercurrent, logic output active low, IN1-OUT2
OC3 12 12 OOvercurrent, logic output active low, IN2-OUT3
OUT1 15 15 OPower-switch output, IN1-OUT1
OUT2 14 14 OPower-switch output, IN1-OUT2
OUT3 11 11 OPower-switch output, IN2-OUT3
TPS2044A and TPS2054A
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2044A TPS2054A
EN1 3 – I Enable input. logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input. Logic low turns on power switch, IN2-OUT3.
EN4 8 – I Enable input. Logic low turns on power switch, IN2-OUT4.
EN1 – 3 I Enable input. Logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input. Logic high turns on power switch, IN2-OUT3.
EN4 – 8 I Enable input. Logic high turns on power switch, IN2-OUT4.
GNDA 1 1 Ground for IN1 switch and circuitry.
GNDB 5 5 Ground for IN2 switch and circuitry.
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
OC1 16 16 OOvercurrent. Logic output active low, IN1-OUT1
OC2 13 13 OOvercurrent. Logic output active low, IN1-OUT2
OC3 12 12 OOvercurrent. Logic output active low, IN2-OUT3
OC4 9 9 O Overcurrent. Logic output active low, IN2-OUT4
OUT1 15 15 OPower-switch output, IN1-OUT1
OUT2 14 14 OPower-switch output, IN1-OUT2
OUT3 11 11 OPower-switch output, IN2-OUT3
OUT4 10 10 OPower-switch output, IN2-OUT4
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx, ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 10 µA on the single and dual devices (20 µA on
the triple and quad devices) when a logic high is present on ENx (TPS204xA†) or a logic low is present on ENx
(TPS205xA†). A logic zero input on ENx or a logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant-current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS204xA and TPS205xA implement a dual-threshold thermal trip to allow fully independent operation of
the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.
†
Product series designations TPS204x and TPS205x refer to devices presented in this data sheet and not necessarily to other TI devices
numbered in this sequence.
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO(OUT) (see Note 1) –0.3 V to VI(IN) + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI(ENx) or VI(ENx) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(OUT) internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ0°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . .
Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACT OR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D–8 725 mW 5.9 mW/°C464 mW 377 mW
D–16 1123 mW 9 mW/°C719 mW 584 mW
recommended operating conditions
MIN MAX UNIT
Input voltage, VI(IN) 2.7 5.5 V
Input voltage, VI(EN) or VI(EN) 0 5.5 V
Continuous output current, IO(OUT) (per switch) 0 500 mA
Operating virtual junction temperature, TJ0 125 °C
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = VI(IN) (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS†
TPS204xA TPS205xA
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX
UNIT
VI(IN) = 5 V,
IO = 0.5 A TJ = 25°C, 80 100 80 100
Static drain-source on-state
resistance, 5-V operation VI(IN) = 5 V,
IO = 0.5 A TJ = 85°C, 90 120 90 120
VI(IN) = 5 V,
IO = 0.5 A TJ = 125°C, 100 135 100 135 mΩ
DS(on) VI(IN) = 3.3 V,
IO = 0.5 A TJ = 25°C, 90 125 90 125
Static drain-source on-state
resistance, 3.3-V operation VI(IN) = 3.3 V,
IO = 0.5 A TJ = 85°C, 110 145 110 145
VI(IN) = 3.3 V,
IO = 0.5 A TJ = 125°C, 120 160 120 160
Rise time out
p
ut
VI(IN) = 5.5 V,
CL = 1 µF, TJ = 25°C,
RL=10 Ω2.5 2.5
ms
r
Rise
time
,
o
u
tp
u
t
VI(IN) = 2.7 V,
CL = 1 µF, TJ = 25°C,
RL=10 Ω3 3
ms
Fall time out
p
ut
VI(IN) = 5.5 V,
CL = 1 µF, TJ = 25°C,
RL=10 Ω4.4 4.4
ms
f
Fall
time
,
o
u
tp
u
t
VI(IN) = 2.7 V,
CL = 1 µF, TJ = 25°C,
RL=10 Ω2.5 2.5
ms
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input ENx or ENx
PARAMETER
TEST CONDITIONS
TPS204xA TPS205xA
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 2 V
VIL
Low level in
p
ut voltage
4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 0.8 V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
2.7 V≤ VI(IN) ≤ 4.5 V 0.4 0.4
II
In
p
ut current
TPS204xA VI(ENx) = 0 V or VI(ENx) = VI(IN) –0.5 0.5
µA
I
I
Inp
u
t
c
u
rrent
TPS205xA VI(ENx) = VI(IN) or VI(ENx) = 0 V –0.5 0.5 µ
A
ton T urnon time CL = 100 µF, RL=10 Ω 20 20 ms
toff Turnoff time CL = 100 µF, RL=10 Ω40 40
current limit
PARAMETER
TEST CONDITIONS†
TPS204xA TPS205xA
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX
UNIT
IOS Short-circuit output current VI(IN) = 5 V, OUT connected to GND,
Device enabled into short circuit 0.7 1 1.3 0.7 1 1.3 A
†Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = VI(IN) (unless otherwise noted) (continued)
supply current (TPS2041A, TPS2051A)
PARAMETER
TEST CONDITIONS
TPS2041A TPS2051A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
TJ = 25°C 0.025 1
Supply current, low-level No Load VI(EN) = VI(IN) –40°C ≤ TJ ≤ 125°C 10
µA
y,
output on OUT
VI(EN) =0V
TJ = 25°C 0.025 1 µ
A
V
I(EN) =
0
V
–40°C ≤ TJ ≤ 125°C 10
V0V
TJ = 25°C 85 110
Supply current, No Load
V
I(EN) =
0
V
–40°C ≤ TJ ≤ 125°C 100
µA
y,
high-level output on OUT
VI(EN) =V
I(IN)
TJ = 25°C 85 110 µ
A
V
I(EN) =
V
I(IN) –40°C ≤ TJ ≤ 125°C 100
Leakage current
OUT
connected
VI(EN) = VI(IN) –40°C ≤ TJ ≤ 125°C 100
µA
Leakage
c
u
rrent
connec
t
e
d
to ground VI(EN)= 0 V –40°C ≤ TJ ≤ 125°C 100 µ
A
Reverse leakage current
IN = High VI(EN) = 0 V
TJ=25
°
C
0.3
µA
Re
v
erse
leakage
c
u
rrent
g
impedance VI(EN) = VI(IN)
T
J =
25°C
0.3 µ
A
supply current (TPS2042A, TPS2052A)
PARAMETER
TEST CONDITIONS
TPS2042A TPS2052A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
TJ = 25°C 0.025 1
Supply current, low-level No Load VI(ENx) = VI(IN) –40°C ≤ TJ ≤ 125°C 10
µA
y,
output on OUT
VI(EN ) =0V
TJ = 25°C 0.025 1 µ
A
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C 10
V( ) 0V
TJ = 25°C 85 110
Supply current, No Load
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C 100
µA
y,
high-level output on OUT
VI(EN ) =V
I(IN)
TJ = 25°C 85 110 µ
A
V
I(ENx) =
V
I(IN) –40°C ≤ TJ ≤ 125°C 100
Leakage current
OUT
connected
VI(ENx) = VI(IN) –40°C ≤ TJ ≤ 125°C 100
µA
Leakage
c
u
rrent
connec
t
e
d
to ground VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 100 µ
A
Reverse leakage current
IN = high VI(EN) = 0 V
TJ=25
°
C
0.3
µA
Re
v
erse
leakage
c
u
rrent
g
impedance VI(EN) = VI(IN)
T
J =
25°C
0.3 µ
A
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = VI(IN) (unless otherwise noted) (continued)
supply current (TPS2043A, TPS2053A)
PARAMETER
TEST CONDITIONS
TPS2043A TPS2053A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
TJ = 25°C 0.05 2
Supply current, No Load VI(ENx) = VI(INx) –40°C ≤ TJ ≤ 125°C 20
µA
y,
low-level output on OUTx
VI(EN ) =0V
TJ = 25°C 0.05 2 µ
A
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C 20
V0V
TJ = 25°C 160 200
Supply current, No Load
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C 200
µA
y,
high-level output on OUTx
VI(EN ) =V
I(IN )
TJ = 25°C 160 200 µ
A
V
I(ENx) =
V
I(INx) –40°C ≤ TJ ≤ 125°C 200
Leakage current
OUTx connected VI(ENx) = VI(INx) –40°C ≤ TJ ≤ 125°C 200
µA
Leakage
c
u
rrent
to ground VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 200 µ
A
Reverse leakage IN = high VI(ENx) = 0 V
TJ=25
°
C
0.3
µA
g
current
g
impedance VI(ENx) = VI(IN)
T
J =
25°C
0.3 µ
A
supply current (TPS2044A, TPS2054A)
PARA-
TEST CONDITIONS
TPS2044A TPS2054A
UNIT
METER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
TJ = 25°C 0.05 2
Supply current, No Load VI(ENx) = VI(INx) –40°C ≤ TJ ≤ 125°C 20
µA
y,
low-level output on OUTx
VI(EN ) =0V
TJ = 25°C 0.05 2 µ
A
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C 20
V0V
TJ = 25°C 170 220
Supply current, No Load
V
I(ENx) =
0
V
–40°C ≤ TJ ≤ 125°C 200
µA
y,
high-level output on OUTx
VI(EN ) =V
I(IN )
TJ = 25°C 170 220 µ
A
V
I(ENx) =
V
I(INx) –40°C ≤ TJ ≤ 125°C 200
Leakage current
OUTx connected VI(ENx) = VI(INx) –40°C ≤ TJ ≤ 125°C 200
µA
Leakage
c
u
rrent
to ground VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C 200 µ
A
Reverse leakage IN = high VI(EN) = 0 V
TJ=25
°
C
0.3
µA
g
current
g
impedance VI(EN) = VI(IN)
T
J =
25°C
0.3 µ
A
undervoltage lockout
PARAMETER
TEST CONDITIONS
TPS204xA TPS205xA
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV
overcurrent OC
PARAMETER
TEST CONDITIONS
TPS204xA TPS205xA
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
Sink current†VO = 5 V 10 10 mA
Output low voltage IO = 5 V, VOL(OC)0.5 0.5 V
Off-state current†VO = 5 V, VO = 3.3 V 1 1 µA
†Specified by design, not production tested.
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL CL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE W AVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(EN)
VO(OUT)
ton toff
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time
with 0.1-µF Load Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load
VO(OUT)
(2 V/div)
0123456
t – Time – ms 78910
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 10 Ω
VI(EN)
(5 V/div)
04812
t – Time – ms 16 20
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 10 Ω
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
2 6 10 14 18
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Turnon Delay and Rise Time
with 1-µF Load Figure 5. Turnoff Delay and Fall Time
with 1-µF Load
0123456
t – Time – ms 78910
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
Figure 6. TPS2051A, Short-Circuit Current,
Device Enabled into Short Figure 7. TPS2051A, Threshold Trip Current
with Ramped Load on Enabled Device
0123456
t – Time – ms 78910
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
VI(EN)
(5 V/div)
0102030405060
t – Time – ms 70 80 90 100
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
VO(OUT)
(2 V/div)
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0 2 4 6 8 10 12
t – Time – ms 14 16 18 20
VI(EN)
(5 V/div)
IO(OUT)
(0.2 A/div)
470 µF
220 µF
100 µF
VI(IN) = 5 V
TA = 25°C
RL = 10 Ω
VO(OC)
(5 V/div)
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
Ramp = 1 A/100 ms
0 20 40 60 80 100 120
t – Time – ms 140 160 180 200
Figure 8. OC Response With Ramped Load
on Enabled Device Figure 9. Inrush Current with 100-µF, 220-µF
and 470-µF Load Capacitance
Figure 10. 4-Ω Load Connected to Enabled Device Figure 11. 1-Ω Load Connected
to Enabled Device
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
0 1000 2000 3000 4000 5000
VO(OC)
(5 V/div)
t – Time – µs
IO(OUT)
(1 A/div)
VI(IN) = 5 V
TA = 25°C
0 200 400 600 800 1000
VO(OC)
(5 V/div)
t – Time – µs
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
2.9
2.6
2.3
22.5 3 3.5 4 4.5
Turnon Delay Time – ms
3.2
TURNON DELAY TIME
vs
INPUT VOLTAGE
3.5
5 5.5 6
VI – Input Voltage – V
CL = 1 µF
RL = 10 Ω
TA = 25°C
Figure 13
4
6
8
10
12
2.5 3 3.5 4 4.5 5 5.5 6
Turnon Delay Time – ms
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
VI – Input Voltage – V
CL = 1 µF
RL = 10 Ω
TA = 25°C
Figure 14
1.8
2.1
2.4
2.7
3
2.5 3 3.5 4 4.5 5 5.5 6
– Rise Time – ms
RISE TIME
vs
INPUT VOLTAGE
rt
CL = 1 µF
RL = 10 Ω
TA = 25°C
VI – Input Voltage – V
Figure 15
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.5 3 3.5 4 4.5 5 5.5 6
– Fall Time – ms
FALL TIME
vs
INPUT VOLTAGE
ft
CL = 1 µF
RL = 10 Ω
TA = 25°C
VI – Input Voltage – V
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
40
50
60
70
80
90
100
–40 0 25 85 125
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
– Supply Current, Output Enabled –
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
II(IN) Aµ
TJ – Junction Temperature – °C
Figure 17
VI(IN) = 4.5 V
0
20
40
60
80
100
120
140
160
–40 0 25 85 125
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 3.3 V
VI(IN) = 2.7 V
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
– Supply Current, Output Disabled – nA
II(IN)
TJ – Junction Temperature – °C
Figure 18
0
20
40
60
80
100
120
140
160
0 25 85 125
IO = 0.5 A
VI(IN) = 3 V
VI(IN) = 4.5 V
VI(IN) = 5 V
VI(IN) = 2.7 V VI(IN) = 3.3 V
– Static Drain-Source On-State Resistance – m
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
Ω
rDS(on)
TJ – Junction Temperature – °C
Figure 19
0
10
20
30
40
50
60
70
100 200 300 400 500
TA = 25°C
VI(IN) = 2.7 V
VI(IN) = 3.3 V
VI(IN) = 4.5 V
VI(IN) = 5 V
– Input-to-Output Voltage – mV
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
VI(IN) –VO(OUT)
IL – Load Current – A
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
0.6
0.7
0.8
0.9
1
1.1
1.2
–40 025 85 125
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 2.7 V
VI(IN) = 3.3 V
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Short-circuit Output Current – A
IOS
Figure 21
1
1.04
1.08
1.12
1.16
1.2
2.5 3 3.5 4 4.5 5 5.5 6
Threshold Trip Current – A
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
VI – Input Voltage – V
TA = 25°C
Load Ramp = 1 A/10 ms
Figure 22
2.1
2.15
2.2
2.25
2.3
2.35
–40 0 25 85 125
Start Threshold
Stop Threshold
UVLO – Undervoltage Lockout – V
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
Figure 23
0
50
100
150
200
250
0 2.5 5 7.5 10 12.5
Current Limit Response –
Peak Current – A
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
sµ
VI(IN) = 5 V
TA = 25°C
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
IN
OC
EN GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF 22 µF
Load
1
OUT
TPS2041A
Power Supply
2.7 V to 5.5 V
Figure 24. Typical Application (Example, TPS2041A)
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS204xA and TPS205xA sense the
short and immediately switch into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS204xA and TPS205xA are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS204xA and
TPS205xA family of devices are designed to reduce false overcurrent reporting. An internal overcurrent
transient filter eliminates the need for external components to remove unwanted pulses. Using low-ESR
electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events
by providing a low-impedance energy source, also reducing erroneous overcurrent reporting.
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS2041A
Rpullup
V+
Figure 25. Typical Circuit for OC Pin (Example, TPS2041A)
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on)
of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use
the highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the
power dissipation per switch can be calcultaed by:
PD
+
rDS(on)
I2
Depending on which device is being used, multiply this number by the number of switches being used. This step
will render the total power dissipation from the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ
+
PD
R
q
JA
)
TA
Where: TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin)
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS204xA and TPS205xA into constant-current mode, which
causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across
the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high
levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built
into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back
on. The switch continues to cycle in this manner until the load fault or input power is removed.
The TPS204xA and TPS205xA implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or
overcurrent occurs.
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D
Hosts/self-powered hubs (SPH)
D
Bus-powered hubs (BPH)
D
Low-power, bus-powered functions
D
High-power, bus-powered functions
D
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS204xA and
TPS205xA can provide power-distribution solutions for many of these classes of devices.
host/self-powered and bus-powered hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figures 26 and 27). This power supply must provide from 5.25 V to 4.75 V to the board
side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current-limit protection and must report overcurrent conditions to the USB controller . Typical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
IN
OC
EN
GND
0.1 µF
2, 3
5
4
7
0.1 µF 120 µFGND
OUT
TPS2041A
Power Supply
D+
D–
VBUS
Downstream
USB Ports
USB
Control
3.3 V 5 V
Figure 26. Typical One-Port Solution
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
IN1
OC1
EN1
OC2
EN2
GNDA
0.1 µF
2
11
3
13
4
15
14
33 µF
33 µF
GND
1
OUT1
OUT2
TPS2044A
Power Supply D+
D–
VBUS
GND
D+
D–
VBUS
Downstream
USB Ports
USB
Controller
3.3 V 5 V
OC3
EN3
OC4
EN4
12
7
9
8
6IN2
+
+
5
GNDB
11
10 33 µF
33 µF
GND
OUT3
OUT4
D+
D–
VBUS
GND
D+
D–
VBUS
+
+
Figure 27. Typical Four-Port USB Host/Self-Powered Hub
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on powerup, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller , the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
low-power bus-powered functions and high-power bus-powered functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and
can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of
44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 28).
IN
OC
EN
GND
0.1 µF2,3
5
4
6, 7, 8
0.1 µF 10 µF
GND
1
OUT
TPS2041A
Power Supply
D+
D–
VBUS
USB
Control
3.3 V
10 µFInternal
Function
Figure 28. High-Power Bus-Powered Function (Example, TPS2041A)
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
D
Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
D
Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)
D
Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS204xA and TPS205xA allows them to meet each of these requirements. The
integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level
enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as
the input ports for bus-power functions (see Figures 29 through 32).
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 29. Hybrid Self/Bus-Powered Hub Implementation, TPS2041A
†USB rev 1.1 requires 120 µF per hub.
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D –
5 V
GND
D +
D –
5 V
D +
D –
5 V
D +
D –
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D –
Upstream
Port
TPS2041A
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2041A EN Input
OC EN
OUT
5 V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
GND
EN
OC
IN
TPS2041A
OUT
EN
OC
IN
TPS2041A
OUT
EN
OC
IN
TPS2041A
OUT
EN
OC
IN
TPS2041A
OUT
TPS76333
0.1 µF
0.1 µF
0.1 µF
0.1 µF
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 30. Hybrid Self/Bus-Powered Hub Implementation, TPS2042A
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
EN1
IN
OC1
OUT1
D +
D –
5 V
GND
D +
D –
5 V
D +
D –
5 V
D +
D –
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
TPS2042A
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D –
Upstream
Port
TPS2041A
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2042A EN Input
OC EN
OUT
5 V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN2
OC2
OUT2
EN1
IN
OC1
OUT1
TPS2042A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
TPS76333
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 31. Hybrid Self/Bus-Powered Hub Implementation, TPS2043A
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D –
5 V
GND
D +
D –
5 V
D +
D –
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
47 µF†
1/2 SN75240
A
BC
D
GND
GND
47 µF†
47 µF†
D +
D –
Upstream
Port
TPS2041A
1/2 SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2043A EN Input
OC EN
OUT
5 V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN1
OC1
OUT1
TPS2043A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
EN3
OC3
OUT3
IN2
GNDA
GNDB
TPS76333
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 32. Hybrid Self/Bus-Powered Hub Implementation, TPS2044A
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
VCC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D –
5 V
GND
D +
D –
5 V
D +
D –
5 V
D +
D –
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
A
BC
D
33 µF†
SN75240
A
BC
D
GND
GND
GND
33 µF†
33 µF†
33 µF†
D +
D –
Upstream
Port
TPS2041A
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2041 EN Input
OC EN
OUT
5 V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN1
OC1
OUT1
TPS2044A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†USB rev 1.1 requires 120 µF per hub.
EN3
OC3
OUT3
EN4
OC4
OUT4
IN2
GNDA
GNDB
TPS76333
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
generic hot-plug applications (see Figure 33)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xA and TPS205xA, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS204xA and TPS205xA also ensures the switch will be off after the card has been removed, and the
switch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for
every insertion of the card or module.
Power
Supply Block of
Circuitry
TPS2041A
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
Figure 33. Typical Hot-Plug Implementation (Example, TPS2041A)
By placing the TPS204xA and TPS205xA between the VCC input and the rest of the circuitry, the input power
will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2041AD NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2041ADG4 NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2041ADR NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2041ADRG4 NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2042AD NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2042ADG4 NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2042ADR NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2042ADRG4 NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2043AD NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2043ADG4 NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2043ADR NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2043ADRG4 NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2044AD NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2044ADG4 NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2044ADR NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2044ADRG4 NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2051AD NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2051ADG4 NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2051ADR NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2051ADRG4 NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2052AD NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2052ADG4 NRND SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2052ADR NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2052ADRG4 NRND SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2053AD NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 4-Aug-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2053ADG4 NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2053ADR NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2053ADRG4 NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2054AD NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2054ADG4 NRND SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2054ADR NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2054ADRG4 NRND SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Aug-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2041ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2042ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2043ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2044ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2051ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2052ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2053ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2054ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2041ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2042ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2043ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2044ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2051ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2052ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2053ADR SOIC D 16 2500 333.2 345.9 28.6
TPS2054ADR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jul-2011
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and www.ti.com/automotive
Automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprfTI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated