Rev. 1.61 1/10 Copyright © 2010 by Silicon Laboratories Si4133
Si4133
Si4123/22/13/12
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS
FOR WIRELESS COMMUNICATIONS
FEATURES
Applications
Description
The Si4133 is a monolithic integrated circuit that performs both IF and dual-
band RF synthesis for wireless communications applications. The Si4133
includes three VCOs, loop filters, reference and VCO dividers, and phase
detectors. Divider and powerdown settings are programmable with a three-
wire serial interface.
Functional Block Diagram
Dual-band RF synthesizers
RF1: 900 MHz to 1.8 GHz
RF2: 750 MHz to 1.5 GHz
IF synthesizer
IF: 62.5 to 1000 MHz
Integrated VCOs, loop filters,
varactors, and resonators
Minimal (2) n umber of external
components required
Low phase noise
Programmable powerdown modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP,
28-lead QFN
Lead-free and RoHS compliant
Dual-band communications
Digital cellular telephones GSM 850, E-GSM 900, DCS 1800,
PCS 1900
Digital cordless phones
Analog cordless phones
Wireless local loop
IFOUT
IFLA
IFLB
RFOUT
XIN
PWDN
SDATA
SCLK
SEN
IF
RF2
RF1
Powerdown
Control
Reference
Amplifier
Serial
Interface
AUXOUT IFDIV
R
R
R
N
N
N
Phase
Detector
22-bit
Data
Register
Test
Mux
RFLC
RFLD
RFLA
RFLB
Phase
Detector
Phase
Detector
Patents pending
Ordering Information:
See page 31.
Pin Assignments
Si4133-GT
Si4133-GM
124
223
322
421
520
619
718
817
916
10 15
11 14
12 13
SCLK
SDATA
GNDR
RFLD
RFLC
RFLB
GNDR
RFLA
GNDR
GNDR
RFOUT
VDDR
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
GND
Pad
SCLK
SDATA
GNDR
RFLD
RFLC
RFLB
GNDR
RFLA
RFOUT
VDDR SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
21
20
19
18
17
16
15
8 9 10 11 12 13 14
28 27 26 25 24 23 22
1
2
3
4
5
6
7
GNDR
GNDR
GNDR GNDD
GNDI
GNDR
Si4133
2 Rev. 1.61
Si4133
Rev. 1.61 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2. Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Extended Frequency Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.4. Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.5. Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6. PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.7. RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.8. Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.9. Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.10. Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5. Pin Descriptions: Si4133-GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4133-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Si4133 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: Si4133-GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Package Outline: Si4133-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Si4133
4 Rev. 1.61
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA–40 25 85 °C
Supply Voltage VDD 2.7 3.0 3.6 V
Supply Voltages Difference V(VDDR – VDDD),
(VDDI – VDDD)–0.3 — 0.3 V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperatur e of 25 °C unless oth erwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter Symbol Value Unit
DC Supply Voltage VDD –0.5 to 4.0 V
Input Current3IIN ±10 mA
Input Voltage3VIN –0.3 to VDD+0.3 V
Storage Temperature Range TSTG –55 to 150 oC
Notes:
1. Permanent device damage may occu r if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and asse mbly of
this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDATA, SEN, PWDN and XIN.
Si4133
Rev. 1.61 5
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Total Supply Current1RF1 and IF operating — 18 27 mA
RF1 Mode Supply Curre nt1—1016mA
RF2 Mode Supply Curre nt1—916mA
IF Mode Supply Current1—813mA
Standby Current PWDN = 0 — 1 — µA
High Level Input Voltage2VIH 0.7 VDD ——V
Low Level Input Voltage2VIL — — 0.3 VDD V
High Level Input Current2IIH VIH = 3.6 V,
VDD = 3.6 V –10 — 10 µA
Low Level Input Current2IIL VIL = 0 V,
VDD= 3.6 V –10 — 10 µA
High Level Output Voltage3VOH IOH = –500 µA VDD–0.4 — — V
Low Level Output Voltage3VOL IOH = 500 µA — — 0.4 V
Notes:
1. RF1 = 1.6 GHz, RF2 = 1.1 GHz, IFOUT = 550 MHz, LPWR = 0.
2. For signals SCLK, SDATA, SEN, and PWDN.
3. For signal AUXOUT.
Si4133
6 Rev. 1.61
Figure 1. SCLK Timing Diagram
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1Symbol Test Condition Min Typ Max Unit
SCLK Cycle Time tclk Figure 1 40 — — ns
SCLK Rise Time trFigure 1 — — 50 ns
SCLK Fall Time tfFigure 1 — — 50 ns
SCLK High Time thFigure 1 10 — — ns
SCLK Low Time tlFigure 1 10 — — ns
SDATA Setup Time to SCLK2tsu Figure 2 5 — — ns
SDATA Hold Time from SCLK2thold Figure 2 0 — — ns
SEN to SCLKDelay Time2ten1 Figure 2 10 — — ns
SCLK to SENDelay Time2ten2 Figure 2 12 — — ns
SEN to SCLKDelay Time2ten3 Figure 2 12 — — ns
SEN Pulse Width twFigure 2 10 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveforms unless otherwise noted.
2. Timing is not referenced to 50% level of the waveform. See Figure 2.
SCLK 80%
20%
50%
trtf
tl
tclk
th
Si4133
Rev. 1.61 7
Figure 2. Serial Interface Timing Diagram
Figure 3. Serial Word Format
D17 D16 D15 A1 A0
tsu
ten1
thold
tw
ten2
ten3
SCLK
SDATA
SENB
D
17 D
16 D
15 D
14 D
13 D
12 D
11 D
10 D
9D
8D
7D
6D
5D
4D
3D
2D
1D
0A
3A
2A
1A
0
data
field address
field
Fi rst b it
c loc k ed in Last bit
clocked in
Si4133
8 Rev. 1.61
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1Symbol Test Condition Min Typ Max Unit
XIN Input Frequency fREF 2—26MHz
Reference Amplifier Sensitivity VREF 0.5 — VDD
+0.3 V VPP
Phase Detector Update Frequency ff= fREF/R 0.010 — 1.0 MHz
RF1 VCO Center Frequency Range fCEN 947 — 1720 MHz
RF1 VCO Tuning Range2Extended frequency
operation 1850 — 2050 MHz
RF2 VCO Center Frequency Range fCEN 789 — 1429 MHz
RF Tuning Range from fCEN Note: LEXT ±10% –5 — 5 %
IF VCO Center Frequency Range fCEN 526 — 952 MHz
IFOUT Tuning Range with IFDIV 62.5 — 1000 MHz
IFOUT Tuning Range from fCEN Note: LEXT ±10% –5 — 5 %
RF1 VCO Pushing Open loop — 500 — kHz/V
RF2 VCO Pushing — 400 — kHz/V
IF VCO Pushing — 300 — kHz/V
RF1 VCO Pulling VSWR = 2:1, all
phases, open loop — 400 — kHzPP
RF2 VCO Pulling — 300 — kHzPP
IF VCO Pulling — 100 — kHzPP
RF1 Phase Noise 1 MHz offset — –132 — dBc/Hz
RF1 Integrat ed Phas e Error 10 H z to 10 0 kHz — 0.9 — degrees
rms
RF2 Phase Noise 1 MHz offset — –134 — dBc/Hz
RF2 Integrat ed Phas e Error 10 H z to 10 0 kHz — 0.7 — degrees
rms
IF Phase Noise 100 kHz offset — –117 — dBc/Hz
IF Integrated Phase Error 100 Hz to 100 kHz — 0.4 — degrees
rms
Notes:
1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted.
2. Extended frequency operation only. VDD 3.0 V, QFN only, VCO T uning Range fixed by directly shorting the RFLA and
RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation.
3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN.
Si4133
Rev. 1.61 9
RF1 Harmonic Suppression Second Harmonic — –26 –20 dBc
RF2 Harmonic Suppression — –26 –20 dBc
IF Harmonic Suppression — –26 –20 dBc
RFOUT Power Level ZL = 50 –8 –3 1 dBm
RFOUT Power Level2ZL = 50RF1 active,
Extended frequency
operation
–14 –7 1 dBm
IFOUT Power Level ZL = 50 –8 –4 0 dBm
RF1 Output Reference Spurs Offset = 200 kHz — –65 — dBc
Offset = 400 kHz — –71 — dBc
Offset = 600 kHz — –75 — dBc
RF2 Output Reference Spurs Offset = 200 kHz — –65 — dBc
Offset = 400 kHz — –71 — dBc
Offset = 600 kHz — –75 — dBc
Powerup Request to Synthesizer Ready3
Time tpup Fi gu re s 4, 5 — 40/f50/f
Powerdown Request to Synthesizer Off4
Time tpdn Fi gu re s 4, 5 — — 100 ns
Table 5. RF and IF Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1Symbol Test Condition Min Typ Max Unit
Notes:
1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted.
2. Extended frequency operation only. VDD 3.0 V, QFN only, VCO T uning Range fixed by directly shorting the RFLA and
RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation.
3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN.
Si4133
10 Rev. 1.61
Figure 4. Software Power Management Timing Diagram
Figure 5. Hardware Power Management Timing Diagram
PDIB = 0
PDRB = 0
PDIB = 1
PDRB = 1
tpup tpdn
IT
IPWDN
SEN
SDATA
RF and IF synthes i zers settled to
within 0.1 ppm frequency error.
tpup tpdn
IT
IPWDN
PWDN
RF and IF synthes i zers settled to
within 0.1 ppm frequency error.
Si4133
Rev. 1.61 11
Figure 6. Typical Transient Response RF1 at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
Si4133
12 Rev. 1.61
Figure 7. Typical RF1 Phase Noise at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
102103104105106
−140
−130
−120
−110
−100
−90
−80
−70
−60
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
Si4133
Rev. 1.61 13
Figure 9. Typical RF2 Phase Noise at 1.2 GHz
with 200 kHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 1.2 GHz
with 200 kHz Phase Detector Update Frequency
102103104105106
−140
−130
−120
−110
−100
−90
−80
−70
−60
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
Si4133
14 Rev. 1.61
Figure 11. Typical IF Phase Noise at 550 MHz
with 200 kHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 550 MHz
with 200 kHz Phase Detector Update Frequency
102103104105106
−150
−140
−130
−120
−110
−100
−90
−80
−70
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
Si4133
Rev. 1.61 15
2. Typical Application Circuits
Figure 13. Si4133-GT
Figure 14. Si4133-GM
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
VDDR
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
AUXOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Si4133-GT
RFOUT
560 pF 2 nH
Printed Trace
Inductor or
Chip Inductor
Printed Trace
Inductors
IFOUT
560 pF40 nH
AUXOUT
External Clock
560 pF
From
System
Controller 0.022
VDD
0.022
VDD
0.022 VDD
30 *
* Add 30 series resistance if using IF output divide values 2, 4, or 8.
PWDN PWDN
F
F
F
* Add 30 series resistance if using IF output divide values 2, 4, or 8.
VDD
30 *
4
5
6
7
1
2
3
8 9 10 11 12 13 14
15
16
17
18
19
20
21
22232425262728
Si4133-GM
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR External Clock
From
System
Controller
VDD
VDD
IFOUT
AUXOUT
RFOUT
0.022
0.022F
0.022
Printed Trace
Inductor or
Chip Induc tor
Printed Trace
Inductors
560 pF
560 pF
40 nH
2 nH
560 pF
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
GNDD
GNDR
SDAT A
SCLK
VDDI
IFOUT
GNDI
PWDN
SEN
F
F
Si4133
16 Rev. 1.61
3. Functional Description
The Si4133 is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for wireless
communications applications. This integrated circuit
(IC), with minimal external components, completes the
frequency synthesis function necessary for RF
communications systems.
The Si4133 has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4133 suitable for demanding wireless
communications applications. Phase detectors, loop
filters, and reference and output frequency dividers are
integrated. The IC is programmed with a three-wire
serial interface.
Two PLLs are provided for dual-band RF synthesis.
These RF PLLs are multiplexed so that only one PLL is
active at a time, as determined by the setting of an
internal register. The active PLL is the last one to be
written. The center frequency of the VCO in each PLL is
set by the value of an external inductance. Inaccuracies
in these inductances are compensated for by the self-
tuning algorithm. The algorithm is run after powerup or
after a change in the programmed output frequency.
Each RF PLL, when active, can adjust the RF output
frequency by ±5% of its VCO’s center frequency.
Because the two VCOs can be set to have widely
separated center frequencies, the RF output can be
programmed to service two widely separated frequency
bands by programming the corresponding N-Divider.
One RF VCO is optimized to have its center frequency
set between 947 MHz and 1.72 GHz, while the second
RF VCO is optimized to have its center frequency set
between 789 MHz and 1. 42 9 GHz.
One PLL is provided for IF frequency synthesis. The
center frequency of this circuit’s VCO is set by the
connection of an external inductance. The PLL can
adjust the IF output frequency by ±5% of the VCO
center frequency. Inaccuracies in the value of the
external inductance are compensated for by the
Si4133’s proprietary self-tuning algorithm. This
algorithm is initiated each time the PLL is powered-up
(by either the PWDN pin or by software) and/or each
time a new output frequency is programmed.
The IF VCO can have its center frequency set as low as
526 MHz and as high as 952 MHz. An IF output divider
divides down the IF output frequencies, if needed. The
divider is programmable and is capable of dividing by 1,
2, 4, or 8.
The unique PLL architecture used in the Si4133
produces settling (lock) times that are comparable in
speed to fractional-N architectures without the high
phase noise or spurious modulation effects often
associated with those designs.
3.1. Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4133 is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SEN is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. D ata in th e sh ift register is the n tr ansf erre d o n
the rising edge of SEN into the internal data register
addressed in the address field. The serial interface is
disabled when SEN is high.
Table 12 on page 21 summarizes the data register
functions and addresses. The internal shift register
ignores leading bits before the 22 required bits.
3.2. Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies
±5% of the center frequencies of their VCOs. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances are acceptable. The Si4133 compensates
for inaccuracies in each inductance by executing a self-
tuning algorithm after PLL powerup or after a change in
the programmed output frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package must be
considered when determining the correct external
inductance. The total inductance (LTOT) presented to
each VCO is the sum of the external inductance (LEXT)
and the package inductance (LPKG). Each VCO has a
nominal capacitance (CNOM) in parallel with the total
inductance, and the center frequency is as follows:
or
Tables 6 and 7 summarize the characteristics of each
VCO.
fCEN 1
2LTOT CNOM
-----------------------------------------------
=
fCEN 1
2LPKG LEXT
+CNOM
------------------------------------------------------------------------
=
Si4133
Rev. 1.61 17
Figure 15. External Inductance Connection
As a design example, consider that the goal is to
synthesize frequencies in a 25 MHz band between
1120 and 1145 MHz using the Si4133-GT. The center
frequency should be defined as midway between the
two extremes, or 1132.5 MHz. The PLL can adjust the
VCO output frequency ±5% of the center frequency, or
±56.6 MHz of 1132.5 MHz (i.e., from approximately
1076 to 1189 MHz). The RF2 VCO has a CNOM of
4.8 pF. A 4.1 nH inductance in parallel with this
capacitance yields the required center frequency. An
external inductance of 1.8 nH should be connected
between RFLC and RFLD as show n in Figure 15. This,
in addition to 2.3 nH of package inductance, presents
the correct total inductance to the VCO. In
manufacturing, the external inductance can vary ±10%
of its nominal value and the Si4133 corrects for the
variation with the self-tuning algor ithm.
For more information on designing the external trace
inductors, refer to Application Note 31: Inductor Design
for the Si41xx Synthesizer Family.
3.3. Extended Frequency Operation
The Si4133 may operate at an extended frequency
range of 1850 MHz to 2050 MHz by connecting the
RFLA and RFLB pins directly. For information on
configuring the Si4133 for extended frequency
operation, refer to Application Note 41: Extended
Frequency Operation of Silicon Laboratories Frequency
Synthesizers.
3.4. Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately after
powerup of a PLL or, if the PLL is already powered, af ter
a change in its programmed output frequency. This
algorithm attempts to tune the VCO so that its free-
running frequency is ne ar the required ou tput frequency.
In doing so, the algorithm compensates for
manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It also
reduces the frequency error for which the PLL must
correct to get the precise required outpu t frequency. The
self-tuning algorithm leaves the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output freque ncy.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL completes frequency locking,
eliminating any remaining frequency error. From then
on, it maintains frequency-lock, compensating for
effects of temperature and supply voltage variations.
The Si4133’s self-tuning algorithm compensates for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur after self-tuning is limited. For external
inductances with temperature coefficients
approximately ±150 ppm/oC, the PLL can maintain lock
for changes in temperature of approximately ±30 oC.
Applications where the PLL is regularly powered down
or the frequency is periodically reprogrammed minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned in either case. In
applications where the ambient temperature can drift
substantially after self-tuning, it might be necessary to
monitor the lock-detect bar (LDETB) signal on the
AUXOUT pin to determine whether a PLL is about to
run out of locking capability. See “3.10. Auxiliary Output
Table 6. Si4133-GT VCO Characteristics
VCO fCEN Range
(MHz) CNOM
(pF) LPKG
(nH) LEXT Range
(nH)
Min Max Min Max
RF1 947 1720 4.3 2.0 0.0 4.6
RF2 789 1429 4.8 2.3 0.3 6.2
IF 526 952 6.5 2.1 2.2 12.0
Table 7. Si4133-GM VCO Characteristics
VCO fCEN Range
(MHz) CNOM
(pF) LPKG
(nH) LEXT Range
(nH)
Min Max Min Max
RF1 947 1720 4.3 1.5 0.5 5.1
RF2 789 1429 4.8 1.5 1.1 7.0
IF 526 952 6.5 1.6 2.7 12.5
LPKG
2
LPKG
2
LEXT
Si4133
18 Rev. 1.61
(AUXOUT)” for how to select LDETB. The LDETB
signal is low after self-tuning is completed but rises
when the IF or RF PLL nears the limit of its
compensation range. LDETB is also high when either
PLL is executing the self-tuning algorithm. The output
frequency is still locked when LDETB goes high, but the
PLL eventually loses lock if the temperature continues
to drift in the same direction. Therefore, if LDETB goes
high both the IF and RF PLLs should be re-tuned
promptly by initiating the self-tuning algorithm.
3.5. Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has R and N registers so that each can be programmed
independently. Programming either the R- or N-Divider
register for RF1 or RF2 automatically selects the
associated output.
The reference frequency on the XIN pin is divided by R
and this signal is input to the PLL’s phase detector. The
other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL acts to make
these frequencies equal.
That is, after an initial transient:
or
The R values are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The N values are set by programming the RF1 N-
Divider register (Register 3), the RF2 N-D ivider register
(Register 4), and the IF N-Divider register (Register 5).
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits is automatically handled. Only the
appropriate N v alue should be programmed.
3.6. PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f (equal to fREF/R) and
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. See Register 1. Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bit s to 00, and the lo west by
setting the bits to 11. The values of the available gains,
relative to the highest gain, are as follows:
The gain value bits is automatically set with the Auto KP
bit (bit 2) in the Main Configuration register to 1. In
setting this bit, the gain values are optimized for a given
value of N. In general, a higher phase detector gain
decreases in-band phase noise and increase the speed
of the PLL transient until the point at which stability
begins to be compromised. The optimal gain depends
on N. Table 9 lists recommended settings for different
values of N. These are the settings when the Auto KP bit
is set.
The VCO gain and loop filter characteristics are not
programmable.
The settling time for the PLL is directly p roportional to it s
phase detector update period T (T equals 1/f). A
typical transient response is shown in Figure 6 on page
11. During the first 13 update periods the Si4133
executes the self-tuning algorithm. From then on the
PLL controls the output frequency. Because of the
unique architecture of the Si4133 PLLs, the time
required to settle the output frequency to 0.1 ppm error
is automatically 25 update periods. The total time after
powerup or a cha nge in program med freque ncy until the
synthesized frequency is settled—including time for
self-tuning—is approximately 40 update periods.
Note: The settling time analysis holds for RF1 f 500 kHz.
For RF1 f > 500 kHz, the settling time is larger.
fOUT
N
------------fREF
R
-----------
=
fOUT N
R
----fREF
=
Table 8. Gain Values (Register 1)
KP Bits Relative P.D.
Gain
00 1
01 1/2
10 1/4
11 1/8
Table 9. Optimal KP Settings
NRF1
KP1<1:0> RF2
KP2<3:2> IF
KPI<5:4>
2047 00 00 00
2048 to 4095 00 00 01
4096 to 8191 00 01 10
8192 to 16383 01 10 11
16384 to 32767 10 11 11
32768 11 11 11
Si4133
Rev. 1.61 19
3.7. RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO respectively. The
RF output amplifier receives its input from the RF1 or
RF2 VCO, depending on which R- or N-Divider register
is written last. For example, programming the N-Divider
register for RF1 automatically selects the RF1 VCO
output.
Figures 13 and 14 show application diagrams for the
Si4133. The RF output signal must be ac coupled to its
load through a capacitor. An external inductance
between the RFOUT pin and the ac coupling capacitor
is required as part of an output matching network to
maximize power delivered to the load. This 2 nH
inductance can be realized with a PC board trace. The
network is made to provide an adequate match to an
external 50 load for both the RF1 and RF2 frequency
bands. The matching network also filters the output
signal to reduce harmonic distortion.
The IFOUT pin must also be ac coupled to its load
through a capacitor. The IF output level is dependent
upon the load . Figure 18 on page 20 displays the output
level versus load resistance for a variety of output
frequencies. For resistive loads greater than 500 the
output level saturates and the bias currents in the IF
output amplifier are higher than required. The LPWR bit
in the Main Configuration register (Register 0) can be
set to 1 to reduce the bias currents and therefore reduce
the power dissipated by the IF amplifier. For loads less
than 500  LPWR should be set to 0 to maximize the
output level.
For IF frequencies greater than 500 MHz, a matching
network is required to drive a 50 load. See Figure 16.
The value of LMATCH can be determined from Table 10.
Figure 16. IF Frequencies > 500 MHz
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200 resistive load or higher. For
resistive loads greater than 500 (f < 500 MHz) the
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 17.
Figure 17. IF Frequencies < 500 MHz
3.8. Reference Frequency Amplifier
The Si4133 provides a reference frequency amplifier. If
the driving signal has CMOS levels it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be ac coupled to the XIN pin
through a 560 pF capacitor.
3.9. Powerdown Modes
Table 11 summarizes the powerdown functionality. The
Si4133 can be powered down by taking the PWDN pin low
or by setting bits in the Powerdown register (Register 2).
When the PW D N pin is low, the Si4133 is powered down
regardless of the Powerdown register settings. When the
PWDN pin is high, power management is in control of the
Powerdown register bits.
The IF and RF sections of the Si4133 circuitry can be
individually powered down by setting the Powerdown
register bits PDIB and PDRB low, respectively. The
reference frequency amplifier is also powered up if the
PDRB and PDIB bi ts are high. Also, setting the AUT OPDB
bit to 1 in the Main Configuration register (Register 0) is
equivalent to setting both bits in the Powerdown register to
1.
The serial interface remains available and can be written in
all powerdown modes.
Table 10. LMATCH Va lues
Frequency LMATCH
500–600 MHz 40 nH
600–800 MHz 27 nH
800 MHz–1 GHz 18 nH
IFOUT LMATCH
560 pF
50
IFOUT
>500 pF
>200
Si4133
20 Rev. 1.61
3.10. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the AUXSEL bits to 11. This signal can be used to indicate that the IF
or RF PLL is going to lose lock because of excessive ambient temperature drift and should be re-tuned. The
LDETB signal indicates a logical OR result if both IF and RF are simultaneously generating a signal.
Figure 18. Typical IF Output Voltage vs. Load Resistance at 550 MHz
Table 11. Powerdown Configuration
PWDN Pin AUTOPDB PDIB PDRB IF Circuitry RF Circuitry
PWDN = 0 XXXOFFOFF
PWDN = 1
000OFFOFF
001OFFON
010ONOFF
011ONON
1xxONON
0
50
100
150
200
250
300
350
400
450
0 200 400 600 800 1000 1200
Load Resistance ()
Output Voltage (mVrms)
LPWR=0 LPWR=1
Si4133
Rev. 1.61 21
4. Control Registers
Note: Registers 9–15 are reserved. Writes to these registers might resul t in unpredictable behavior. Registers not listed here
are reserved and should not be written.
Ta bl e 12 . R egis t er Summary
Register Name Bit
17 Bit
16 Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2Bit
1Bit
0
0 Main
Configura-
tion
000 0AUXSEL
[1:0] IFDIV
[1:0] 0000
LPWR 0AUTO
PDB AUTO
KPRF
PWR 0
1 Phase
Detector
Gain
000000000000K
PI[1:0] KP2[1:0] KP1[1:0]
2 Powerdown 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB
3RF1
N-Divider NRF1[17:0]
4RF2
N-Divider 0N
RF2[16:0]
5IF N-Divider00 N
IF[15:0]
6RF1
R-Divider 000 0 0 R
RF1[12:0]
7RF2
R-Divider 000 0 0 R
RF2[12:0]
8 IF R-Divider 0 0 0 0 0 RIF[12:0]
9 Reserved
.
.
.
15 Reserved
Si4133
22 Rev. 1.61
Register 0. Mai n Co nf igu r at io n Address Field = A[3:0] = 0000
Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name 0 0 0 0 AUXSEL
[1:0] IFDIV
[1:0] 0000
LPWR 0AUTO
PDB AUTO
KPRF
PWR 0
Bit Name Function
17:14 Reserved Program to zero.
13:12 AUXSEL[1:0] Auxiliary Output Pin Definition.
00 = Reserved.
01 = Force output low.
10 = Reserved.
11 = Lock Detect—LDETB.
11:10 IFDIV[1:0] IF Output Divider.
00 = IFOUT = IFVCO Frequency
01 = IFOUT = IFVCO Frequency/2
10 = IFOUT = IFVCO Frequency/4
11 = IFOUT = IFVCO Frequency/8
9:6 Reserved Program to zero.
5 LPWR Output Power-Level Settings for IF Synthesizer Circuit.
0 = RLOAD 500 —normal powe r mode.
1 = RLOAD 500 —low power mode.
4 Reserved Progr am to zero.
3 AUTOPDB Auto Powerdown.
0 = Software powerdown is co ntrolled by Register 2.
1 = Equivalent to setting all bits in Register 2 = 1.
2AUTOK
PAuto KP Setting.
0 = KPs are controlled by Register 1.
1 = KPs are set according to Table 9 on page 18.
1 RFPWR Program to zero. (Used for extended frequency operation. See AN41 for
more information.)
0 Reserved Progr am to zero.
Si4133
Rev. 1.61 23
Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name 000000000000K
PI[1:0] KP2[1:0] KP1[1:0]
Bit Name Function
17:6 Reserved Program to zero.
5:4 KPI[1:0] IF Phase Detector Gain Constant.*
N Value KPI
<2048 = 00
2048–4095 = 01
4096–8191 = 10
>8191 = 11
3:2 KP2[1:0] RF2 Phase Detector Gain Constant.*
N Value KP2
<4096 = 00
4096–8191 = 01
8192–16383 = 10
>16383 = 11
1:0 KP1[1:0] RF1 Phase Detector Gain Constant.*
N Value KP1
<8192 = 00
8192–16383 = 01
16384–32767 = 10
>32767 = 11
*Note: When AUTOKP = 1, these bits do not need to be programmed. When AUTOKP = 0, use these recommended values
for programmin g Phase Dete ctor Gain.
Si4133
24 Rev. 1.61
Register 2. Powerd ow n Address Field (A[3:0]) = 0010
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3 D2 D1 D0
Name 000000000000000 0
PDIB PDRB
Bit Name Function
17:2 Reserved Program to zero.
1 PDIB Powerdown IF Synthesizer.
0 = IF synthesizer powered down.
1 = IF synthesizer on.
0 PDRB Powerdown RF Synthesizer.
0 = RF synthesizer powered down.
1 = RF synthesizer on.
Note: Enabling any PLL with PDIB or PDRB automatically powers on the reference amplifier.
Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name NRF1[17:0]
Bit Name Function
17:0 NRF1[17:0] N-Divider for RF1 Synthesizer.
Register 4. RF2 N-Divider Address Field = A[3:0] = 0100
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name 0N
RF2[16:0]
Bit Name Function
17 Reserved Program to zero.
16:0 NRF2[16:0] N-Divider for RF2 Synthesizer.
Si4133
Rev. 1.61 25
Register 5. IF N-Divider Address Field (A[3:0]) = 0101
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name 00 N
IF[15:0]
Bit Name Function
17:16 Reserved Program to zero.
15:0 NIF[15:0] N-Divider for IF Synthesizer.
Register 6. RF1 R-Divider Address Field (A[3:0]) = 0110
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name 00000 R
RF1[12:0]
Name Function
17:13 Reserved Program to zero.
12:0 RRF1[12:0] R-Divider for RF1 Synthesizer.
RRF1 can be any value from 7 to 8189 if KP1 = 00
8 to 8189 if KP1 = 01
10 to 8189 if KP1 = 10
14 to 8189 if KP1 = 11
Register 7. RF2 R-Divider Address Field (A[3:0]) = 0111
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name 00000 R
RF2[12:0]
Bit Name Function
17:13 Reserved Program to zero.
12:0 RRF2[12:0] R-Divider for RF2 Synthesizer.
RRF2 can be any value from 7 to 8189 if KP2 = 00
8 to 8189 if KP2 = 01
10 to 8189 if KP2 = 10
14 to 8189 if KP2 = 11
Si4133
26 Rev. 1.61
Register 8. IF R-Divider Address Field (A[3:0]) = 1000
Bit D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Name 00000 R
IF[12:0]
Bit Name Function
17:13 Re served Program to zero.
12:0 RIF[12:0] R-Divider for IF Synthesizer.
RIF can be any value from 7 to 8189 if KP1 = 00
8 to 8189 if KP1 = 01
10 to 8189 if KP1 = 10
14 to 8189 if KP1 = 11
Si4133
Rev. 1.61 27
5. Pin Descriptions: Si4133-GT
Pin Number Name De scription
1 SCLK Serial clock input
2 SDATA Serial data input
3 GNDR Common ground for RF analog circuitry
4 RFLD Pins for inductor connection to RF2 VCO
5 RFLC Pins for inductor connection to RF2 VCO
6 GNDR Common ground for RF analog circuitry
7 RFLB Pins for inductor connection to RF1 VCO
8 RFLA Pins for inductor connection to RF1 VCO
9 GNDR Common ground for RF analog circuitry
10 GNDR Common ground for RF analog circuitry
11 RFOUT Radio frequency (RF) output of the selected RF VCO
12 VDDR Supply voltage for the RF analog circuitry
13 AUXOUT Auxiliary output
14 PWDN Powerdown input pin
15 XIN Reference frequency amplifier input
16 GNDD Common ground for digital circuitry
17 VDDD Supply voltage for digital circuitry
18 GNDD Common ground for digital circuitry
19 IFLA Pins for inductor connection to IF VCO
20 IFLB Pins for inductor connection to IF VCO
21 GNDI Common ground for IF analog circuitry
22 IFOUT Intermediate frequency (IF) output of the IF VCO
23 VDDI Supply voltage for IF analog circuitry
24 SEN Enable serial port input
124
223
322
421
520
619
718
817
916
10 15
11 14
12 13
SCLK
SDATA
GNDR
RFLD
RFLC
RFLB
GNDR
RFLA
GNDR
GNDR
RFOUT
VDDR
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
Si4133
28 Rev. 1.61
Table 13. Pin Descriptions for Si4133 Derivatives—TSSOP
Pin Number Si4133 Si4123 Si4122 Si4113 Si4112
1 SCLK SCLK SCLK SCLK SCLK
2 SDATA SDATA SDATA SDATA SDATA
3 GNDR GNDR GNDR GNDR GNDD
4 RFLDGNDRRFLDRFLDGNDD
5 RFLCGNDRRFLCRFLCGNDD
6 GNDR GNDR GNDR GNDR GNDD
7 RFLB RFLB GNDR RFLB GNDD
8 RFLA RFLA GNDR RFLA GNDD
9 GNDR GNDR GNDR GNDR GNDD
10 GNDR GNDR GNDR GNDR GNDD
11 RFOUT RFOUT RFOUT RFOUT GNDD
12 VDDR VDDR VDDR VDDR VDDD
13 AUXOUT AUXOUT AUXOUT AUXOUT AUXOUT
14 PWDN PWDN PWDN PWDN PWDN
15 XIN XIN XIN XIN XIN
16 GNDD GNDD GNDD GNDD GNDD
17 VDDD VDDD VDDD VDDD VDDD
18 GNDD GNDD GNDD GNDD GNDD
19 IFLA IFLA IFLA GNDD IFLA
20 IFLB IFLB IFLB GNDD IFLB
21 GNDI GNDI GNDI GNDD GNDI
22 IFOUT IFOUT IFOUT GNDD IFOUT
23 VDDI VDDI VDDI VDDD VDDI
24 SEN SEN SEN SEN SEN
Si4133
Rev. 1.61 29
6. Pin Descriptions: Si4133-GM
Pin Number Name De scription
1 GNDR Common ground for RF analog circuitry
2 RFLD Pins for inductor connection to RF2 VCO
3 RFLC Pins for inductor connection to RF2 VCO
4 GNDR Common ground for RF analog circuitry
5 RFLB Pins for inductor connection to RF1 VCO
6 RFLA Pins for inductor connection to RF1 VCO
7 GNDR Common ground for RF analog circuitry
8 GNDR Common ground for RF analog circuitry
9 GNDR Common ground for RF analog circuitry
10 RFOUT Radio frequency (RF) output of the selected RF VCO
11 VDDR Supply voltage for the RF analog circuitry
12 AUXOUT Auxiliary output
13 PWDN Powerdown input pin
14 GNDD Common ground for digital circuitry
15 XIN Reference frequency amplifier input
16 GNDD Common ground for digital circuitry
17 VDDD Supply voltage for digital circuitry
18 GNDD Common ground for digital circuitry
19 IFLA Pins for inductor connection to IF VCO
20 IFLB Pins for inductor connection to IF VCO
21 GNDI Common ground for IF analog circuitry
22 GNDI Common ground for IF analog circuitry
23 IFOUT Intermediate frequency (IF) output of the IF VCO
24 VDDI Supply voltage for IF analog circuitry
25 SEN Enable serial port input
26 SCLK Serial clock input
27 SDATA Serial data input
28 GNDR Common ground for RF analog circuitry
SCLK
SDATA
GNDR
RFLD
RFLC
RFLB
GNDR
RFLA
RFOUT
VDDR SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
21
20
19
18
17
16
15
8 9 10 11 12 13 14
28 27 26 25 24 23 22
1
2
3
4
5
6
7
GNDR
GNDR
GNDR GNDD
GNDI
GNDR
GND
Pad
Si4133
30 Rev. 1.61
Table 14. Pin Descriptions for Si4133 Derivatives—QFN
Pin Number Si4133 Si4123 Si4122 Si4113 S i4112
1 GNDR GNDR GNDR GNDR GNDD
2 RFLDGNDRRFLDRFLDGNDD
3 RFLCGNDRRFLCRFLCGNDD
4 GNDR GNDR GNDR GNDR GNDD
5 RFLB RFLB GNDR RFLB GNDD
6 RFLA RFLA GNDR RFLA GNDD
7 GNDR GNDR GNDR GNDR GNDD
8 GNDR GNDR GNDR GNDR GNDD
9 GNDR GNDR GNDR GNDR GNDD
10 RFOUT RFOUT RFOUT RFOUT GNDD
11 VDDR VDDR VDDR VDDR VDDD
12 AUXOUT AUXOUT AUXOUT AUXOUT AUXOUT
13 PWDN PWDN PWDN PWDN PWDN
14 GNDD GNDD GNDD GNDD GNDD
15 XIN XIN XIN XIN XIN
16 GNDD GNDD GNDD GNDD GNDD
17 VDDD VDDD VDDD VDDD VDDD
18 GNDD GNDD GNDD GNDD GNDD
19 IFLA IFLA IFLA GNDD IFLA
20 IFLB IFLB IFLB GNDD IFLB
21 GNDI GNDI GNDI GNDD GNDI
22 GNDI GNDI GNDI GNDD GNDI
23 IFOUT IFOUT IFOUT GNDD IFOUT
24 VDDI VDDI VDDI VDDD VDDI
25 SEN SEN SEN SEN SEN
26 SCLK SCLK SCLK SCLK SCLK
27 SDATA SDATA SDATA SDATA SDATA
28 GNDR GNDR GNDR GNDR GNDD
Si4133
Rev. 1.61 31
7. Ordering Guide
8. Si4133 Derivative Devices
The Si4133 performs both IF and dual-band RF frequency synthesis. The Si4112, Si4113, Si4122, and the Si4123
are derivatives of this device. Table 15 outlines which synthesizers each derivative device features and the pins
and registers that coincide with each synthesizer.
Ordering Part
Number Description Operating Temperature
Si4133-D-GM RF1/RF2/IF OUT, Lead Free, QFN –40 to 85 ºC
Si4133-D-GT RF1/RF2/IF OUT, Lead Free, TSSOP –40 to 85 ºC
Si4123-D-GM RF1/IF OUT, Lead Free, QFN –40 to 85 ºC
Si4123-D-GT RF1/IF OUT, Lead Free, TSSOP –40 to 85 ºC
Si4122-D-GM RF2/IF OUT, Lead Free, QFN –40 to 85 ºC
Si4122-D-GT RF2/IF OUT, Lead Free, TSSOP –40 to 85 ºC
Si4113-D-GM RF1/RF2 OUT, Lead Free, QFN –40 to 85 ºC
Si4113-D-GT RF1/RF2 OU T, Lead Fr ee , TSSOP –40 to 85 ºC
Si4113-D-ZT1 RF1/RF2 OUT, NiPd, TSSOP –40 to 85 ºC
Si4112-D-GM IF OUT, Lead Free, QFN –40 to 85 ºC
Si4112-D-GT IF OUT, Lead Free, TSSOP –40 to 85 ºC
Table 15. Si4133 Derivatives
Name Synthesizer Pins Registers
Si4112 IF IFLA, IFLB NIF, RIF, PDIB, IFDIV, LPWR, AUTOPDB = 0,
PDRB = 0
Si4113 RF1, RF2 RFLA, RFLB, RFLC, RFLD NRF1, NRF2, RRF1, RRF2, PDRB, AUTOPDB = 0,
PDIB = 0
Si4122 RF2, IF RFLC, RFLD, IFLA, IFLB NRF2, RRF2, PDRB, NIF, RIF, PDIB, IFDIV, LPWR
Si4123 RF1, IF RFLA, RFLB, IFLA, IFLB NRF1, RRF1, PDRB, NIF, RIF, PDIB, IFDIV, LPWR
Si4133 RF1, RF2, IF RFLA, RFLB, RFLC, RFLD,
IFLA, IFLB NRF1, NRF2, RRF1, RRF2, PDRB, NIF, RIF, PDIB,
IFDIV, LPWR
Si4133
32 Rev. 1.61
9. Package Outline: Si4133-GT
Figure 19 illustrates the package details for the Si4133-GT. Table 16 lists the values for the dimensions shown in
the illustration.
Figure 19. 24-Pin Thin Shrink Small Outline Package (TSSOP)
Table 16. Package Diagram Dimensions
Symbol Millimeters
Min Nom Max
A——1.20
A1 0.05 — 0.15
b 0.19 — 0.30
c 0.09 — 0.20
D 7.70 7.80 7.90
e 0.65 BSC
E 6.40 BSC
E1 4.30 4.40 4.50
L 0.45 0.60 0.75
10° —8°
bbb 0.10
ddd 0.20
L
1
c
D
A1
A
b
E1 E
e
See Detail G
Detail G
12 3
ddd CBA
A
C
24
bbb CBA
M
B
Si4133
Rev. 1.61 33
10. Package Outline: Si4133-GM
Figure 20 illustrates the package details for the Si4133-GM. Table 17 lists the values for the dimensions shown in
the illustration.
Figure 20. 28-Pin Quad Flat No-Lead (QFN)
Table 17. Package Dimensions
Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 L 0.50 0.60 0.70
A1 0.00 0.01 0.05 aaa — — 0.10
b 0.18 0.23 0.30 bbb — — 0.10
D, E 5.00 BSC ccc — — 0 .05
e 0.50 BSC ddd — — 0.10
D2, E2 2.55 2.70 2.85 ——12
Notes:
1. Dimensioning and tolerancin g per ANSI Y14.5M-1994.
2. This package outline conforms to JEDEC MS-220, variant VHHD-1.
3. Recommended card reflow profile is per the JEDEC /IPC J-STD-020B specification for Small Body
Components.
Si4133
34 Rev. 1.61
DOCUMENT CHANGE LIST
Revision 1.4 to Revision 1.5
"7.Ordering Guide" on page 31 updated.
Changed MLP to QFN (same package, generic
name)
Revision 1.5 to Revision 1.6
Updated "7.Ordering Guide" on page 31.
Revision 1.6 to Revision 1.61
Updated contact infor m ation.
Si4133
Rev. 1.61 35
NOTES:
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
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