THIS SPEC IS OBSOLETE
Spec No
:
38
-
05475
Spec
Title
:
CY7C1049DV33, 4
-
MBIT (512K X 8) STATIC
RAM
R
eplaced by:
None
CY7C1049DV33
4-Mbit (512K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05475 Rev. *J Revised December 6, 2016
4-Mbit (512K × 8) Static RAM
Features
■Pin and function compatible with CY7C1049CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA at 10 ns
■Low CMOS standby power
❐ISB2 = 10 mA
■2.0 V data retention
■Automatic power down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free 36-pin (400 Mil) molded SOJ and 44-pin
TSOP II packages
Functional Description
The CY7C1049DV33 is a high performance CMOS Static RAM
organized as 512K words by 8-bits. Easy memory expansion is
provided by an Active LOW Chip Enable (CE), an Active LOW
Output Enable (OE), and tristate drivers. You can write to the
device by taking Chip Enable (CE) and Write Enable (WE) inputs
LOW. Data on the eight I/O pins (IO0 through IO7) is then written
into the location specified on the address pins (A0 through A18).
You can read from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the I/O pins.
The eight input or output pins (IO0 through IO7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1049DV33 is available in standard 400 Mil wide 36
-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
For a complete list of related documentation, click here.
Logic Block Diagram
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A10
A13
A14
A15
A16
A17
A11
A12
A18
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 2 of 14
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 5
AC Switching Characteristics .........................................6
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 9
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 3 of 14
Pin Configuration
Selection Guide
Description -10 (Industrial) Unit
Maximum access time 10 ns
Maximum operating current 90 mA
Maximum CMOS standby current 10 mA
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
NC
18
17
20
19
27
28
25
26
22
21
23
24
44-pin TSOP II
Top View
NC
NC
NC
NC
A
0
A
1
A
2
A
8
A
7
A
11
A
10
NC
NC
NC
A
9
NC NC
A
18
A
17
A
16
A
3
A
6
A
4
CE
IO
0
IO
1
IO
2
IO
3
WE
A
5
A
13
A
14
IO
4
IO
5
IO
6
IO
7
OE
A
15
V
CC
V
CC
V
SS
V
SS
A
12
10
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
12
13
16
15
29
30
18
17 20
19
27
28
25
26
22
21
23
24
36-pin SOJ
Top View
NC
A
0
A
1
A
2
A
8
A
7
A
11
A
10
NC
A
9
A
18
A
17
A
16
A
3
A
6
A
4
CE
IO
0
IO
1
IO
2
IO
3
WE
A
5
A
13
A
14
IO
4
IO
5
IO
6
IO
7
OE
A
15
V
CC
V
CC
GND
GND
A
12
10
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 4 of 14
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage on
VCC to relative GND[1] .................................–0.3 V to +4.6 V
DC voltage applied to outputs
in High Z State[1] ................................. –0.3 V to VCC + 0.3 V
DC input voltage[1] .............................. –0.3 V to VCC + 0.3 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage .......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Range
Ambient
Temperature VCC Speed
Industrial –40 C to +85 C 3.3 V 0.3 V 10 ns
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-10 (Industrial)
UnitMin Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V
VIH[1] Input HIGH voltage 2.0 VCC + 0.3 V
VIL[1] Input LOW voltage[1] –0.3 0.8 V
IIX Input leakage current GND < VI < VCC –1 +1 A
IOZ Output leakage current GND < VOUT < VCC,
Output Disabled
–1 +1 A
ICC VCC operating supply current VCC = Max,
f = fMAX = 1/tRC
100 MHz – 90 mA
83 MHz – 80 mA
66 MHz – 70 mA
40 MHz – 60 mA
ISB1 Automatic CE
Power down current
—TTL Inputs
Max VCC, CE > VIH; VIN > VIH or
VIN < VIL, f = fMAX
–20mA
ISB2 Automatic CE
Power down current
—CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V,
f = 0
–10mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT I/O capacitance 8pF
Note
1. VIL (min.) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 5 of 14
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
36-pin SOJ
Package
44-pin TSOP II
Package Unit
JA Thermal resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, two layer printed
circuit board
57.91 50.66 C/W
JC Thermal resistance
(Junction to Case)
36.73 17.17 C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms [4]
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions [4] Min Max Unit
VDR VCC for data retention 2.0 – V
ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V
VIN > VCC – 0.3 V or VIN < 0.3 V
–10mA
tCDR[2] Chip deselect to data retention time 0 – ns
tR[5] Operation recovery time tRC –ns
Figure 2. Data Retention Waveform
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(b)
(a)
3.3 V
OUTPUT
5 pF
(c)
R 317
R2
351
High Z characteristics:
10 ns device
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Notes
2. Tested initially and after any design or process changes that may affect these parameters.
3. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load shown
in Figure 1 (c).
4. No input may exceed VCC + 0.3 V.
5. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 6 of 14
AC Switching Characteristics
Over the Operating Range [6]
Parameter Description
-10 (Industrial)
UnitMin Max
Read Cycle
tpower[7] VCC (typical) to the first access 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE LOW to data valid –10 ns
tDOE OE LOW to data valid –5ns
tLZOE OE LOW to Low Z[8] 0–ns
tHZOE OE HIGH to High Z[8, 9] –5ns
tLZCE CE LOW to Low Z[8] 3–ns
tHZCE CE HIGH to High Z[8, 9] –5ns
tPU CE LOW to power up 0 –ns
tPD CE HIGH to power down –10 ns
Write Cycle[10, 11]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end 7 –ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7 –ns
tSD Data setup to write end 5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to Low Z[8] 3–ns
tHZWE WE LOW to High Z[8, 9] –5ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30 pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access is performed.
8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 1 on page 5. Transition is measured when the outputs enter a high impedance state.
10. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 7 of 14
Switching Waveforms
Figure 3. Read Cycle No. 1[12, 13]
Figure 4. Read Cycle No. 2 (OE Controlled)[13, 14]
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[15, 16]
PREVIOUS DATA VALID DATAOUT VALID
tRC
tAA
tOHA
ADDRESS
DATA I/O
50%
50%
DATAOUT VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA I/O
VCC
SUPPLY
CURRENT
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 16
Notes
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 8 of 14
Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW)[17]
Figure 7. Write Cycle No. 3 (CE Controlled)[17, 19]
Switching Waveforms (continued)
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 18
tWC
DATAIN VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
Notes
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
18. During this period the I/Os are in the output state and input signals must not be applied.
19. Data I/O is high impedance if OE = VIH.
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 9 of 14
Truth Table
CE OE WE IO0–IO7Mode Power
H X X High Z Power down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
10 CY7C1049DV33-10VXI 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1049DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Temperature Range: X = I
I = Industrial
Pb-free
Package Type: XX = V or ZS
V = 36-pin (400-Mil) Molded SOJ
ZS = 44-pin TSOP II
Speed: XX = 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
9 = Data width × 8-bits
04 = 4-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 V33 - XX XX704 9 D X X
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 10 of 14
Package Diagrams
Figure 8. 36-pin (400-Mil) Molded SOJ V36.4, (51-85090)
51-85090 *F
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 11 of 14
Figure 9. 44-pin TSOP Z44-II, (51-85087)
Package Diagrams (continued)
51-85087 *E
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 12 of 14
Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SOJ small outline J-lead
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
WE write enable
Symbol Unit of Measure
°C degree Celcius
MHz megahertz
µA microamperes
µs microseconds
mA milliamperes
mm millimeter
ms milliseconds
ns nanoseconds
ohms
% percent
pF pico Farad
VVolts
WWatts
CY7C1049DV33
Document Number: 38-05475 Rev. *J Page 13 of 14
Document History Page
Document Title: CY7C1049DV33, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05475
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Datasheet for C9 IPP
*A 233729 See ECN SYT 1.AC, DC parameters are modified as per EROS (Specification # 01-2165)
2.Pb-free offering in the Ordering Information Table
*B 351096 See ECN PCI Changed status from Advance to Preliminary.
Removed 20 ns Speed bin
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80, and 67 mA to 90, 80 and, 75 mA for 8, 10, and
12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed
bins respectively
Added VIH(max) specification in Note# 2
Changed reference voltage level for measurement of High Z parameters from 500
mV to 200 mV
Added Data Retention Characteristics, Waveform, and footnotes 11 and 12
Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44
Changed part names from Z to ZS in the Ordering Information Table
Added 8 ns parts in the Ordering Information Table
Added Pb-free Ordering Information
Shaded Ordering Information Table
*C 446328 See ECN NXR Changed status from Preliminary to Final.
Removed -8 speed bin
Removed Commercial Operating Range product information
Added Automotive Operating Range product information
Updated Thermal Resistance table
Updated footnote #8 on High Z parameter measurement
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table
*D 1274726 See ECN VKN/AESA Updated Pin Configuration.
Corrected typo in the 44-pin TSOP II pinout.
*E 2899972 03/29/2010 AJU Updated Package Diagrams.
*F 3059162 10/14/2010 PRAS Added Ordering Code Definitions.
Updated Package Diagrams.
*G 3266084 05/28/2011 PRAS Updated Functional Description (Removed “Refer to the Cypress application note
AN1064, SRAM System Guidelines for best practice recommendations.”).
Added Acronyms and Units of Measure.
Updated to new template.
*H 3440302 11/16/2011 TAVA Removed Automotive Temperature Range related information in all instances
across the document.
Updated Switching Waveforms.
Updated Ordering Information:
Updated part numbers.
*I 4574311 11/19/2014 TAVA Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85090 – Changed revision from *E to *F.
*J 5544150 12/06/2016 VINI Obsolete document.
Completing Sunset Review.
Document Number: 38-05475 Rev. *J Revised December 6, 2016 Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1049DV33
© Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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