NB3L202KMNG - ON SEMICONDUCTOR

January, 2018 − Rev. 4 1Publication Order Number:

NB3L202K/D

NB3L202K

2.5 V, 3.3 V Differential 1:2

HCSL Fanout Buffer

Description

The NB3L202K is a differential 1:2 Clock fanout buffer with

High−speed Current Steering Logic (HCSL) outputs. Inputs can

directly accept differential LVPECL, LVDS, and HCSL signals.

Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are

accepted with a proper external Vth reference supply per Figures 4

and 6. The input signal will be translated to HCSL and provides two

identical copies operating up to 350 MHz.

The NB3L202K is optimized for ultra−low phase noise, propagation

delay variation and low output–to–output skew, and is DB200H

compliant. As such, system designers can take advantage of the

NB3L202K’s performance to distribute low skew clocks across the

backplane or the motherboard making it ideal for Clock and Data

distribution applications such as PCI Express, FBDIMM, Networking,

Mobile Computing, Gigabit Ethernet, etc.

Output drive current is set by connecting a 475 W resistor from

IREF (Pin 10) to GND per Figure 11. Outputs can also interface to

LVDS receivers when terminated per Figure 12.

Features

•Maximum Input Clock Frequency > 350 MHz

•2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation

•2 HCSL Outputs

•DB200H Compliant

•PCIe Gen 3, Gen 4 Compliant

•Individual OE Control Pin for Each Output

•100 ps Max Output−to−Output Skew Performance

•1 ns Typical Propagation Delay

•500 ps Typical Rise and Fall Times

•80 fs Maximum Additive RMS Phase Jitter

•−40°C to +85°C Ambient Operating Temperature

•QFN 16−pin Package, 3 mm x 3 mm

•These Devices are Pb−Free and are RoHS Compliant

Typical Applications

•PCI Express

•FBDIMM

•Mobile Computing

•Networking

•Gigabit Ethernet

MARKING

DIAGRAM

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See detailed ordering and shipping information page 13 of this

data sheet.

ORDERING INFORMATION

NB3L202K = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

QFN16

3x3

CASE 485FM

NB3L

202K

ALYWG

NB3L202K

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Figure 1. Simplified Block Diagram

Figure 2. 16−Pin QFN Pinout

(Top View)

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Table 1. PIN DESCRIPTION

Pin Number Pin Name I/O Description

1 GND Power Ground

2 CLK_IN I, DIF Differential True input

3 CLK_IN# I, DIF Differential Complementary input

4 VDD Power Core power supply

5 GND_O Power Ground for outputs

6 DIF_1# O, DIF 0.7 V Differential Complementary Output

7 DIF_1 O, DIF 0.7 V Differential True Output

8 VDD_O Power Power supply for outputs

9 GND Power Ground

10 IREF I A precision resistor is attached to this pin to set the differential output current.

Use RREF = 475 W, 1% for 100 W trace, with 50 W termination.

Use RREF = 412 W, 1% for 85 W trace, with 43 W termination.

11 OE0# I, SE LVTTL / LVCMOS active low input for enabling output DIF_0/0#. 0 enables outputs,

1 disables outputs. Internal pull down.

12 OE1# I, SE LVTTL / LVCMOS active low input for enabling output DIF_1/1#. 0 enables outputs,

1 disables outputs. Internal pull down.

13 VDD_O Power Power supply for outputs

14 DIF_0 O, DIF 0.7 V Differential True Output

15 DIF_0# O, DIF 0.7 V Differential Complementary Output

16 GND_O Power Ground for outputs

EP Exposed

Pad Thermal The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die

for improved heat transfer out of package. The exposed pad must be attached to a

heat−sinking conduit. The pad is electrically connected to the die, and must be electri-

cally and thermally connected to GND on the PC board.

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Table 2. ATTRIBUTES

Characteristics Value

ESD Protection Human Body Model > 2000 V

RPD − Pull−down Resistor 50 kW

Moisture Sensitivity (Note 1) Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 1344

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Unit

VDD Core Supply Voltage − 4.6 V

VDD_O I/O Supply Voltage − 4.6 V

VIH Input High Voltage (Note 2) − 4.6 V

VIL Input Low Voltage −0.5 − V

IOUT Maximum Output Current − 24 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm

500 lfpm 42

35 °C/W

qJC Thermal Resistance (Junction−to−Case) (Note 3) 4°C/W

Tsol Wave Solder 265 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

2. Maximum VIH is not to exceed maximum VDD.

3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

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Table 4. DC CHARACTERISTICS VDD = VDD_O = 3.3 V ±10% or 2.5 V ±5%, TA = −40°C to 85°C

Symbol Characteristics Min Typ Max Unit

POWER SUPPLY CURRENT

VDD Core Power Supply Voltage VDD = 3.3 V ±10%

VDD = 2.5 V ±5% 2.970

2.375 3.3

2.5 3.630

2.625 V

VDD_O Output Power Supply Voltage VDD_O = 3.3 V ±10%

VDD_O = 2.5 V ±5% 2.970

2.375 3.3

2.5 3.630

2.625 V

IDD + IDD_O Total Power Supply Current (all outputs active @ 350 MHz, RREF = 412 W,

RL = 43 W)80 110 mA

Istdby Standby Current, all OE pins de−asserted with inputs @ 350 MHz 50 65 mA

lincr Incremental output current for additional output; One OE Enabled 15 23 mA

Istdby + lincr Standby Current plus incremental current for one additional differential output;

One OE Enabled @ 350 MHz 65 88 mA

HCSL OUTPUTS (Notes 4, 5)

VOH Output HIGH Voltage 660 850 mV

VOL Output LOW Voltage −150 mV

VOUT Output Swing (Single−Ended)

Output Swing (Differential) 400

800 750

1500 mV

DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Note 6) (Figures 4 and 6)

VIH CLK_IN/CLK_IN# Single-ended Input HIGH Voltage 0.5 VDD V

VIL CLK_IN/CLK_IN# Single-ended Input LOW Voltage GND VIH − 0.3 V

Vth Input Threshold Reference Voltage Range (Note 7) 0.25 VDD − 1.0 V

VISE Single-ended Input Voltage (VIH − VIL)0.5 VDD V

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 8) (Figures 5 and 7)

VIHD Differential Input HIGH Voltage 0.5 VDD − 0.85 V

VILD Differential Input LOW Voltage 0 VIHD −

0.25 V

VID Differential Input Voltage (VIHD − VILD) 0.25 1.3 V

VIHCMR Input Common Mode Range (Differential Configuration) (Note 9) (Figure 8) 0.5 VDD − 0.85 V

IIL Input Leakage Current 0 < VIN < VDD (Note 10) −55mA

LVTTL / LVCMOS INPUTS (OEx#)

VIH Input HIGH Voltage 2.0 VDD + 0.3 V

VIL Input LOW Voltage −0.3 0.8 V

IIL Input LOW Current (VIN = GND) −10 +10 mA

IIH Input HIGH Current (VIN = VDD) 100 mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Test configuration is RS = 33.2 W, RL = 49.9, CL = 2 pF, RREF = 475 W.

5. Measurement taken from Single−Ended waveform unless specified otherwise.

6. VIH, VIL, Vth and VISE parameters must be complied with simultaneously.

7. Vth is applied to the complementary input when operating in single−ended mode.

8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.

9. The common mode voltage is defined as VIH.

10.Does not include inputs with pulldown resistors.

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Table 5. AC TIMING CHARACTERISTICS VDD = VDD_O = 3.3 V ±10% or 2.5 V ±5%, TA = −40°C to 85°C (Note 15)

Symbol Characteristics Min Typ Max Unit

Fmax Maximum Input Frequency 350 MHz

Trise/Tfall Rise Time / Fall Time (Notes 13, 17 and 33) (Figure 13) 175 500 700 ps

Output Slew Rate Output Slew Rate (Notes 13 and 17) 0.5 2.0 V/ns

DTrise/DTfall Rise/Fall Time Variation (Notes 17 and 26) 125 ps

Slew Rate Matching (Notes 18, 27 and 28) 20%

Vhigh Voltage High (Notes 17, and 20) (Figure 14) 660 700 850 mV

Vlow Voltage Low (Notes 17, and 21) (Figure 14) −150 0 +150 mV

Input Slew Rate (Note 29 and 32) 0.35 V/ns

Vcross absolute Absolute Crossing Point Voltages (Notes 12, 17 and 24)

Relative Crossing Point Voltages can be calculated (Notes 16, 17

and 24) (Figure 16)

250 550 mV

Total DVcross Total Variation of Vcross Over All Edges (Notes 17 and 25) 140 mV

Duty Cycle (Note 18) (Figure 15) 45 55 %

Vovs Maximum Voltage (Overshoot) (Notes 17 and 22) (Figure 14) Vhigh + 0.3 V

Vuds Maximum Voltage (Undershoot) (Notes 17 and 23) (Figure 14) Vlow − 0.3 V

Vrb Ringback Voltage (Note 17) (Figure 14) 0.2 N/A V

Toe_lat OE Latency (Note 11) 4 6 12 Cycles

tpd Input−to−Output Delay CLK_IN, DIF_[1:0] (Note 31) 0.6 1.0 1.4 ns

tSKEW Output−to−Output Skew across 2 outputs DIF_[1:0] (Notes 30 and 31) 0 5.0 20 ps

tJITTERfAdditive RMS Phase Jitter fcarrier = 156.25 MHz, 12 kHz − 20 MHz Inte-

grated Range 46 80 fs

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-

formance may not be indicated by the Electrical Characteristics if operated under different conditions.

11.Time from deassertion until outputs are >200 mV.

12.Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.

13.Measured from VOL = 0.175 V to VOH = 0.525 V. Only valid for Rising Clock and Falling Clock#.

14.This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing

15.Test configuration is RS = 33.2 W, RP = 49.9, CL = 2 pF, RREF = 475 W.

16.Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhigh avg − 0.700). Vcross(rel) Max = 0.550 − 0.5

(0.700 – Vhigh avg), (see Figure 16 for further clarification).

17.Measurement taken from Single Ended waveform.

18.Measurement taken from differential waveform.

19.Unless otherwise noted, all specifications in this table apply to all frequencies.

20.Vhigh is defined as the statistical average High value as obtained by using the Oscilloscope Vhigh Math function.

21.Vlow is defined as the statistical average Low value as obtained by using the Oscilloscope Vlow Math function.

22.Overshoot is defined as the absolute value of the maximum voltage.

23.Undershoot is defined as the absolute value of the minimum voltage.

24.The crossing point must meet the absolute and relative crossing point specifications simultaneously.

25.DVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum allowed vari-

ance in Vcross for any particular system.

26.Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

27.Matching applies to rising edge rate for clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average

crosspoint where clock rising meets Clock# falling. The median crosspoint is used to calculate the voltage threshold the oscilloscope is to

use for the edge rate calculations.

28.Slew Rate matching is derived using the following, 2 * (Trise – Tfall) / (Trise + Tfall).

29.Input slew rate is based on single ended measurement. This is the minimum input slew rate at which the NB3L202K devices are guaranteed

to meet all performance specifications.

30.Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.

31.Measured from differential cross−point to differential cross−point with scope averaging on to find mean value.

32.The differential input clock is expected to be sourced from a high performance clock oscillator.

33.Measured at 3.3 V ± 10% with typical HCSL input levels.

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Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature

The above phase noise data was captured using Agilent

E5052A/B. The data displays the input phase noise and

output phase noise used to calculate the additive phase jitter

at a specified integration range. The additive RMS phase

jitter contributed by the device (integrated between 12 kHz

and 20 MHz) is 45.7 fs.

The additive RMS phase jitter performance of the fanout

buffer is highly dependent on the phase noise of the input

source.

To obtain the most accurate additive phase noise

measurement, it is vital that the source phase noise be

notably lower than that of the DUT. If the phase noise of the

source i s similar or greater than the device under test output,

the source noise will dominate the additive phase jitter

calculation and lead to an artificially low result for the

additive phase noise measurement within the integration

range.

Additive RMS phase jitter +RMS phase jitter of output2*RMS phase jitter of input2

45.7 fs +73.7 fs2*57.8 fs2

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Table 6. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS

(VDD = VDD_O = 3.3 V ±10% or 2.5 V ±5%, TA = −40°C to 85°C)

Symbol Parameter Conditions (Notes 34 and 39) Min Typ Max Unit

tjphPCIeG1

Additive Phase Jitter

PCIe Gen 1 (Notes 35 and 36) 10 ps (p−p)

tjphPCIeG2

PCIe Gen 2 Lo Band

10 kHz < f < 1.5 MHz (Notes 35 and 38) 0.3 ps

(rms)

PCIe Gen 2 High Band

1.5 MHz < f < Nyquist (50 MHz)

(Notes 35 and 38) 0.7 ps

(rms)

tjPCIeG3 PCIe Gen 3

(PLL BW= 2−4 MHz or 2−5 MHz, CDR = 10 MHz)

(Notes 35 and 38) 0.07 0.4 ps

tjPCIeG4 PCIe Gen 4

(PLL BW= 2−4 MHz or 2−5 MHz, CDR = 10 MHz)

(Notes 35 and 38) 0.07 0.4 ps

tjphQPI_SMI

QPI & SMI

(100.00 MHz or 133.33 MHz, 4.8 Gb/s,

6.4 Gb/s 12UI) (Notes 37 and 38) 0.3 ps

(rms)

QPI & SMI

(100.00 MHz, 8.0 Gb/s, 12UI) (Notes 37 and 38) 0.1 ps

(rms)

QPI & SMI

(100.00 MHz, 9.6 Gb/s, 12UI) (Notes 37 and 38) 0.1 ps

(rms)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

34.Applies to all outputs.

35.See http://www.pcisig.com for complete specs

36.Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.

37.Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.

38.For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)2 = (total jitter)2 - (input jitter)2

39.Guaranteed by design and characterization, not tested in production

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CLK_IN

Vth

CLK_IN#

Vth

Figure 4. Differential Input Driven

Single−Ended

VIH

VIL

VIHmax

VILmax

VIH

Vth

VIL

VIHmin

VILmin

VDD

Vthmax

Vthmin

GND

Vth

CLK_IN

CLK_IN#

VILDmax

VIHDmax

VIHDtyp

VILDtyp

VIHDmin

VILDmin

VIHCMR

GND

VID = VIHD − VILD

VDD

CLK_IN

CLK_IN#

DIF_n#

DIF_n

tPLH

tPHL

VOUTPP = VOH(DIF_n) −

VOL(DIF_n)

VINPP = VIH(CLK_IN) −

VIL(CLK_IN)

VIHD

VILD

VID = |VIHD(IN) − VILD(IN)|

CLK_IN

CLK_IN#

Figure 5. Differential Inputs

Driven Differentially

Figure 6. Vth Diagram Figure 7. Differential Inputs Driven Differentially

Figure 8. VIHCMR Diagram Figure 9. AC Reference Measurement

CLK_IN

CLK_IN#

VIHCMR MAX

VIHCMR MIN

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Figure 10. Typical Termination Configuration for Output Driver and Device Evaluation

A. Connect 475 W resistor RREF from IREF pin to GND.

B. RS1, RS2: 33 W for Test and Evaluation. Select to Minimizing Ringing.

C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit.

D. RL1, RL2 Termination and Load Resistors Located at Received Inputs.

CL1

2 pF CL2

2 pF

Z0 = 50 W

Receiver

RS1

RS2

HCSL

Driver

RREF

RL1

50 W

RL2

50 W

DIF_n#

DIF_n

IREF

Figure 11. HCSL Simplified Output Structure

IREF C1

3.3 V

MMir

MDum

IOUT

VMirror

RREF

Out_predrv

OUT

~1.1 V

MOUTB MOUT

MIref

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Figure 12. HCSL Interface Termination to LVDS

HCSL

Device LVDS

Device

Zo = 50 W

RL = 150 WRL = 150 W

100 W100 W

GND

RREF

IREF

NB3L202K

MEASUREMENT POINTS FOR DIFFERENTIAL

TRise (Clock)

TFall (Clock#)

Figure 13. Single−Ended Measurement Points for Trise, Tfall

VOH = 0.525 V

VOL = 0.175 V

VCross

Figure 14. Single−Ended Measurement Points for Vovs, Vuds, Vrb

Vovs

Vhigh

Vrb

Vlow

Vuds

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TPeriod

High Duty Cycle% Low Duty Cycle%

Skew measurement point

0.000 V

Figure 15. Differential (CLOCK – CLOCK#) Measurement Points (Tperiod, Duty Cycle)

Crossing Point (mV)

Vhigh Average (mV)

Equ 1: Vcross(rel) Max = 0.550 − 0.5(0.7 − Vhigh avg)

Equ 2: Vcross(rel) Min = 0.250 + 0.5(Vhigh avg − 0.7)

ForVhigh< 700mV

Use Equ.1 ForVhigh> 700mV

Use Equ.2

Figure 16. Vcross Range Clarification (Note 40)

40.The picture above illustrates the effect of Vhigh above and below 700 mV on the Vcross range. The purpose of this is to prevent a 250 mV

Vcross with an 850 mV Vhigh. In addition, this prevents the case of a 550 mV Vcross with a 660 mV Vhigh. The actual specification for Vcross

is dependent upon the measured amplitude of Vhigh.

Vcross(rel) Max

Vcross(rel) Min

550

500

450

400

350

300

250

200 625 650 675 700 725 750 775 800 825 850

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Signal and Feature Operation

Table 7. OE# FUNCTIONALITY (Notes 41, 42 and 43)

CLK_IN / CLK_IN# OE# (Pin) DIF DIF # Notes

Running 1 Low Low 41

Running 0 Running Running

Not Running xxx

41.The outputs are tri−stated, but the termination networks pull them low

42.OE# pins are asynchronous asserted−low signals.

43.Each OE# pin controls two pair of DIF outputs.

OE# Assertion (Transition from ‘1’ to ‘0’)

All differential outputs that were tri−stated (low due to

termination pull down) will resume normal operation in a

glitch free manner. The latency from the assertion to active

outputs is 4 − 12 DIF clock periods.

Note: Input clock must remain running for a minimum of

12 clock cycles.

OE# De−Assertion (Transition from ‘0’ to ‘1’)

The maximum latency from the de−assertion to tristated

(low due to termination pull down) outputs is 12 DIF clock

periods.

Table 8. NB3L202K RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS

Board Target Trace/Term Z Reference R, Iref = VDD/(3*RREF)Output Current VOH @ Z Rs Rp

100 W Differential

50 W Single−Ended RREF = 475 W 1%,

IREF = 2.32 mA IOH = 6 * IREF 0.7 V @ 50 33 W

5% 50 W

85 W Differential

43 W Single−Ended RREF = 412 W, 1%,

IREF = 2.67 mA IOH = 6 * IREF 0.7V @ 43.2 27 W

5% 43 W

ORDERING INFORMATION

Device Package Shipping†

NB3L202KMNG QFN16

(Pb−Free) 123 Units / Rail

NB3L202KMNTXG QFN16

(Pb−Free) 3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

QFN16 3x3, 0.5P

CASE 485FM

ISSUE A

DATE 30 JAN 2018

SCALE 2:1

16X

SEATING

PLANE

0.15 C

16 13

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. OUTLINE MEETS JEDEC DIMENSIONS PER

MO−220, VARIATION VEED−6.

ÇÇÇ

0.15 CTOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN 1

LOCATION

0.10 C

0.08 C

(A3)

16X

0.10 C

0.05 C

A B

NOTE 3

16X

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

XXXXX

ALYWG

(Note: Microdot may be in either location)

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.50

PITCH

3.30

DIMENSIONS: MILLIMETERS

0.65

16X

0.30

16X

OUTLINE

PACKAGE

RECOMMENDED

3.30

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

b0.18 0.30

D3.00 BSC

D2 1.25 1.55

E3.00 BSC

E2 1.25 1.55

e0.50 BSC

L0.30 0.50

A3 0.20 REF

NOTE 4

e/2

0.20 −−−

1.55

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

DETAIL A

DETAIL B

ÉÉ

ÇÇ

DETAIL A

DETAIL B

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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