PW
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FEATURES APPLICATIONS
DESCRIPTION
SYSTEM PARTITIONING DIAGRAM
LDO, Therm Output Drive & UVLO
Power Management
LDO, TOUT and Power mode control
I2C
Capacity Prediction <1% Error
SMBus
Pack +
Pack -
Discharge / Charge /
Pre-Charge FETs
Cell and Pack
Voltage
Measurement
Pre-Charge
FET Drive
2-Tier Over Current Protection
32kHz Clock
Generator
bq2084
768 Bytes of
User Flash
Fuse
1st Level OV and
UV Protection
Pack Under Voltage
Power Mode
Control
Pre-charge Control
Delay Counters
Cell Balancing Algorithm and Control
Cell Balancing
Drive
System Interface
System Watchdog
Voltage Level Translator
System Interface
32kHz
Power Mode Control
Fail-Safe Protection
T1
1st Level OC
Protection
Temperature Measurement
<1% Error TINT
Supply Voltage
bq29312
PCH FET Drive
RAM Registers
SBS v1.1 Data
bq29312 RAM/Comms Validation
2nd Level Over Voltage Protection
XAlert
Sleep
Sense Resistor
(10 - 30 mΩ)
PF Input
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
THREE AND FOUR CELL LITHIUM-ION ORLITHIUM-POLYMER BATTERY PROTECTION AFE
•Notebook PCs•2-, 3-, or 4-Cell Series Protection Control
•Medical and Test Equipment•Can Directly Interface With the bq2084 Gas
•Portable InstrumentationGauges
•Provides Individual Cell Voltages and BatteryVoltage to Battery Management Host
The bq29312 is a 2-, 3-, or 4-cell lithium-ion battery•Integrated Cell Balancing Drive
pack protection analog front end (AFE) IC that•I
2
C Compatible User Interface Allows Access
incorporates a 3.3-V, 25-mA low-dropout regulatorto Battery Information
(LDO). The bq29312 also integrates an I
2
C compat-•Programmable Threshold and Delay for Over
ible interface to extract battery parameters such asLoad and Short Circuit During Charge and
cell voltages and control output status. Other par-Discharge
ameters such as current protection thresholds anddelays can be programmed into the bq29312 to•System Alert Interrupt Output
increase the flexibility of the battery management•Host Control Can Initiate Sleep Power Mode
system.and Ship Mode
The bq29312 provides safety protection for over-•Integrated 3.3-V, 25-mA LDO
charge, overload, short-circuit, overvoltage, and•Supply Voltage Range From 4.5 V to 25 V
undervoltage conditions in conjunction with the bat-tery management host. In overload and short-circuit•Low Supply Current of 60-µA Typical
conditions, the bq29312 turns the FET drive offautonomously dependant on the internal configurationsetting.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (Continued)
PACKAGE DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The communications interface allows the host to observe and control the current status of the bq29312. Itenables cell balancing, enters different power modes, sets overload levels, sets the overload blanking delay time,sets short-circuit threshold levels for charge and discharge, and sets the short-circuit blanking delay time.
Cell balancing of each cell is performed via a cell bypass path, which is enabled via the internal control registeraccessible via the I
2
C compatible interface. The maximum bypass current is set via an external series resistorand internal FET on resistance (typical 400 Ω).
ORDERING INFORMATION
PACKAGED
(1)T
A
TSSOP (PW)
bq29312PW–25 °C to 85 °C
bq29312PWR
(1) For the most current package and ordering information, see the Package Option Addendum at theend of this document, or see the TI website at www.ti.com .
POWER RATINGPOWER RATING DERATING FACTORPACKAGE
T
A
≤25 °C ABOVE T
A
≤25 °C
T
A
≤70 °C T
A
= 85 °C
PW 874 mW 6.99 W/ °C 559 mW 454 mW
over operating free-air temperature range unless otherwise noted
(1) (2)
bq29312
V
SS
Supply voltage range PACK, BAT –0.3 V to 34 VVC1, VC2, VC3, VC4 –0.3 V to 34 VSR1, SR2 –1.0 V to 1.0 VVC5 –1.0 V to 4.0 VV
I
Input voltage range
VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 to
–0.3 to 8.5 VVC5
WDI, SLEEP, SCLK, SDATA –0.3 to 8.5 VZVCHG –0.3 V to 34 VDSG, CHG –0.3 V to BATOD –0.3 V to 34 VV
O
Output voltage range
PMS –0.3 V to PACK – 0.2 VTOUT, SCLK, SDATA, CELL, XALERT –0.3 to 7 VCurrent for cell balancing 10 mAContinuous total power dissipation See Dissipation Rating TableT
stg
Storage temperature range –65 °C to 150 °CLead temperature (soldering, 10 sec) 300 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground of this device except VCn – VC(n + 1), where n = 1, 2, 3, 4 cell voltage.
2
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RECOMMENDED OPERATING CONDITIONS
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
MIN NOM MAX UNIT
Supply Voltage (BAT or PACK) 4.5
(1)
25 VV
I(STARTUP)
Start-up voltage (PACK) 5.0 VVC1, VC2, VC3, VC4 0 BATSR1, SR2 –0.5 0.5VC5 –0.5 3.0V
I
Input voltage range VVCn – VC(n+1), (n = 1, 2, 3, 4 ) 0 5.0PMS 0 PACKSLEEP 0 REGV
IH
0.8 ×REG REG VLogic level input voltage SCLK, SDATA, WDI
0.2 ×V
IL
0
REGV
IH
V
PACK
– 0.2 V
PACK
VPMS logic level PMSV
IL
0 0.2PMS pull up/pull down resistance RPMS 100 1000 k ΩV
O
Output voltage OD 25 VI
O
Output current XALERT, SDATA 200 µACELL ±10 µAInput current,External 3.3 V REGI
I
SLEEP -0.5 1.0 µAcapacitor
C
(REG)
4.7 µFR
(CELL)
100 ΩExtend CELL output filter
C
(CELL)
100 nFOD 1 mAI
OL
Input frequency
WDI 32.768 kHzWDI high time 2 28 µsT
A
Operating temperature –25 85 °C
(1) V
(PACK)
supply voltage must rise above start-up voltage on power up to enable the internal regulator which drives REG and TOUT asrequired. Once V
(PACK)
is above the start-up voltage, it can fall down to the minimum supply voltage and still meet the specifications ofthe bq29312.
3
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ELECTRICAL CHARACTERISTICS
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
T
A
= 25 °C, C
(REG)
= 4.7 µF, BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
No load at REG, TOUT, XALERT, SCLK, and SDATA. 60 90I
CC1
Supply current 1 ZVCHG = off ,VMEN = on, WDI no clock, µAT
A
= –25 °C to 85 °C 100Select VC5 = VC4 = 0 V
Supply current 2
No load at REG, TOUT, XALERT, SCLK, and SDATA.I
CC2
(Depends of VM T
A
= –25 °C to 85 °C 25 50 µAZVCHG = off, VMEN = off, WDI no clocktopology selected)
No load at REG, TOUT, XALERT, SCLK, andI
(SLEEP)
Sleep current SDATA.CHG, DSG and ZVCHG = off, REG = on, T
A
= –25 °C to 85 °C 20 40 µAVMEN = off, WDI no clock, SLEEP = REG or OPEN
REG, CHG, DSG and ZVCHG = off, REG = off,I
(SHIP)
Ship current T
A
= –25 °C to 85 °C 0.1 1.0 µAVMEN = off, WDI no clock, VPACK= 0 V
3.3 V LDO
8.0 V < BAT or PACK ≤25 V, I
O
≤25 mA –4% 3.3 2%
V6.5 V < BAT or PACK ≤8 V, I
O
≤25 mA –9% 3.3 2%Regulator outputV
(REG)
T
A
= –25 °C to 85 °Cvoltage
5.4 V ≤BATor PACK ≤6.5 V, I
O
≤16 mA –9% 3.3 2% V
4.5 V ≤BAT or PACK ≤25 V, I
O
≤2 mA –2% 3.3 2% V
Regulator output∆V
(EGTEMP)
change with 5.4 V ≤BAT ≤25 V, I
O
= 2 mA, T
A
= –25 °C to 85 °C±0.2%temperature
∆V
(REGLINE)
Line regulation 5.4 V ≤BAT or PACK ≤25 V, I
O
= 2 mA 3 10 mV
BAT = 14 V, 0.2 mA ≤I
O
≤2 mA 7 15∆V
(REGLOAD)
Load regulation mVBAT = 14 V, 0.2 mA ≤I
O
≤25 mA 40 100
BAT = 14 V, REG = 3.0 V 25 100I
MAX
Current limit mABAT = 14 V, REG = 0 V 12 50
CELL VOLTAGE MONITOR
V
(Cn)
– V
(Cn + 1)
= 0 V, 8.0 V ≤BAT or PACK ≤25 V 0.975V
(CELL OUT)
CELL output VV
(Cn)
– V
(Cn + 1)
= 4.5 V, 8.0 V ≤BAT or PACK ≤25 V 0.3
REF CELL output Mode
(1)
, 8.0 V ≤BAT or PACK ≤25 V –1% 0.975 1% V
PACK/PACK CELL output Mode
(2)
–5% 5% V25
K = (CELL output (VC5 = 0.0 V, VC4 = 4.5 V)
0.147 0.150 0.153– CELL output (VC5 = VC4 = 0.0 V)/ 4.5K CELL scale factor
K = (CELL output (VC2 = 13.5 V, VC1 = 18.0 V)
0.147 0.150 0.153– CELL output (VC2 = VC1 = 13.5 V)/ 4.5
CELL output offset CELL output (VC2 = 17.0 V, VC1 = 17.0 V)VICR –1 mVerror CELL output (VC2 = VC1 = 0.0 V)
Cell balance internalR
(BAL)
rds
(ON)
for internal FET switch at V
DS
= 2.0 V 200 400 800 Ωresistance
(1) Register Address =0x04, b2(CAL0) = b3(CAL1) = 1, Register Address = 0x03, b0(VMEN) = 1(2) Register Address = 0x03, b1(PACKOUT) = 1, b0( VMEN) = 1
4
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ELECTRICAL CHARACTERISTICS (Continued)
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
T
A
= 25 °C, C
(REG)
= 4.7 µF, BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN NOM MAX UNIT
OVER LOAD (OL) AND SHORT CIRCUIT (SC) DETECTION
V
OL
OL detection threshold range, typical
(1)
–50 –205 mV
∆V
OL
OL detection threshold program step 5 mV
V
HYS(OL)
OL detection threshold hysteresis 7 10 13 mV
Charge 100 475V
(SC)
SC detection threshold range, typical
(2)
mVDischarge –100 –475
Charge 25∆V
(SC)
SC detection threshold program step mVDischarge –25
V
HYS(SC)
SC detection threshold hysteresis Charge and Discharge 40 50 60 mV
V
OL
= 50 mV (min) 40 50 60
V
(OL_acr)
OL detection threshold accuracy
(1)
Discharge V
OL
= 100 mV 90 100 110 mV
V
OL
= 205 mV (max) 184 205 226
V
SC
= 100 mV (min) 80 100 120
V
(SC_acr)
SC detection threshold accuracy
(2)
Charge and Discharge V
SC
= 200 mV 180 200 220 mV
V
SC
= 475 mV (max) 426 475 523
FET DRIVE CIRCUIT
V
(FETOND)
= V
(BAT)
– V
(DSG)
BAT= 20 V 12 15 18VGS connect 1 M ΩOutput voltage, charge and discharge FETsV
(FETON)
Von
V
(FETONC)
=V
(PACK)
– V
(CHG)
PACK = 20 V 12 15 18VGS connect 1 M Ω
V
(ZCHG)
ZVCHG clamp voltage PACK= 4.5 V 3.3 3.5 3.7 V
V
(FETOFF)
= V
(PACK)
– V
(DSG)
PACK= 16 V 0.2Output voltage, charge and discharge FETsV
(FETOFF)
Voff
V
(FETOFF
)=V
(BAT)
– V
(CHG)
BAT = 16 V 0.2
V
DSG
:10%–90% 40 200t
r
Rise time C
L
= 4700 pF µsV
CHG
:10%–90% 40 200
V
DSG
:90%–10% 40 200t
f
Fall time C
L
= 4700 pF µsV
CHG
:90%–10% 40 200
THERMISTOR DRIVE
I
O
= –1 mA at TOUT pin, rds
(ON)
= (V
REG
– V
O
(TOUT))/1 mA,r
DS(on)
TOUT pass-element series resistance 50 100 ΩT
A
= –25 °C to 85 °C
LOGIC
XALERT T
A
= –25 °C to 85 °C 60 100 200R
(PUP)
Internal pullup resistance k ΩSDATA, SCLK, T
A
= –25 °C to 85 °C 6 10 20
XALERT, I
O
= 200 µA, T
A
= –25 °C to 85 °C 0.2
V
OL
Logic level output voltage SDATA, I
O
= 50 µA, T
A
= –25 °C to 85 °C 0.4 V
OD I
O
= 1 mA, T
A
= –25 °C to 85 °C 0.6
(1) See OL register for setting detection threshold(2) See SC register for setting detection threshold
5
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AC ELECTRICAL CHARACTERISTICS
AC TIMING SPECIFICATIONS (I
2
C COMPATIBLE SERIAL INTERFACE)
tsu(STA)
SCLK
SDATA
SCLK
SDATA
SCLK
SDATA
tw(H) tw(L) tftr
trtf
Start
Condition SDA
Input SDA
Change
Stop
Condition
th(STA) th(DAT) tsu(DAT) th(ch)
Start Condition tv
1 2 3 7 8 9
MSB ACK
Stop Condition
tsu(STOP)
1 2 3 7 8 9
MSB ACK
tsu(BUF)
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
T
A
= 25 °C, C
(REG)
= 4.7 µF, BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN NOM MAX UNIT
t
(WDTINT)
WDT start-up detect time 250 700 2000 mst
(WDWT)
WDT detect time 100 µs
PARAMETER MIN MAX UNIT
t
r
SCLK SDATA rise time 1000 nst
f
SCLK SDAT fall time 300 nst
w(H)
SCLK pulse width high 4.0 µst
w(L)
SCLK pulse width low 4.7 µst
su(STA)
Setup time for START condition 4.7 µst
h(STA)
START condition hold time after which first clock pulse is generated 4.0 µst
su(DAT)
Data setup time 250 nst
h(DAT)
Data hold time 0 µst
su(STOP)
Setup time for STOP condition 4.0 µst
su(BUF)
Time the bus must be free before new transmission can start 4.7 µst
V
Clock low to data out valid 900 nst
h(CH)
Data out hold time after clock low 0 nsf
SCL
Clock frequency 0 100 kHz
6
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PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
OD
PMS
PACK
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
GND
SDATA
SCLK
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
PW PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
DESCRIPTIONNAME NO.
BAT 1 Diode protected BAT+ terminal and primary power source.DSG 2 Push-pull output discharge FET gate driveVC1 3 Sense voltage input terminal for most positive cell and balance current input for most positive cell.Sense voltage input terminal for second most positive cell, balance current input for second most positive cell andVC2 4
return balance current for most positive cell.Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and returnVC3 5
balance current for second most positive cell.Sense voltage input terminal for least positive cell, balance current input for least positive cell and return balanceVC4 6
current for third most positive cell.VC5 7 Sense voltage input terminal for most negative cell, return balance current for least positive cell.SR1 8 Current sense positive terminal when charging relative to SR2SR2 9 Current sense negative terminal when discharging relative to SR2 current sense terminalWDI 10 Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.CELL 11 Output of scaled value of the measured cell voltage.GND 12 Analog ground pin and negative pack terminalSCLK 13 Open-drain bidirectional serial interface clock with internal 10 k Ωpull-up to V
(REG)
.SDATA 14 Open-drain bidirectional serial interface data with internal 10 k Ωpull-up to V
(REG)
.GND 15 Connect to GNDXALERT 16 Open-drain output used to indicate status register changes. With internal 100 k Ωpull-up to V
(REG)
TOUT 17 Provides thermistor bias currentREG 18 Integrated 3.3-V regulator outputSLEEP 19 This pin is pulled up to V
(REG)
internally, open or H level makes Sleep modeCHG 20 Push-pull output charge FET gate driveZVCHG 21 The ZVCHG FET drive is connected herePACK 22 PACK positive terminal and alternative power sourcePMS 23 0-V charge configuration select pin, CHG terminal ON/OFF is determined by this pin.OD 24 NCH FET open drain output
7
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GND
CELL1..4
SR1
SR2
Over-Load
Comparator
Short Circuit
SHORT_CIRCUIT
DELAY
Open
Drain
Output
Watchdog
Timer
OD
Cell Voltage
Translation
Power
Mode
Circuit Drive
Control
VCELL
RSNS
RCELL
CCELL
TOUT
RTHERM
CTHERM THERMISTOR
Cell
Selection
Switches
3.3V LDO
POR
SHIP_ON
SLEEP_ON
BAT PACK REG
C(REG)
FET
Logic
Gate Driver CHG_ON
DSG_ON
ZVCHG_ON
DSGCHGZVCHG
PACK- PACK+
R(ZVCHG)
PMS
GG VDD
VC1
VC2
VC5
CELL 3
CELL 4
VC3
VC4 CELL 1
CELL 2
GG TS
INPUT
GG ANALOG
INPUT
SLEEP
REG
WDI
SLEEP
CONTROL
32kHz INPUT
FROM GG
GG INTERFACE
SDATA
ALERT TO GG
OPEN DRAIN
OUTPUT
GG INTERFACE
SCLK
SDATA
SCLK
XALERT
SERIAL INTERFACE
Status
Output Ctl
State Ctl
Function Ctl
CELL_SEL
OCDV
OCDT
SCC
SCD
Registers
Comparator
OVER_CURRENT
REG
200 k
200 k
0.2 A
Current Source _
+
-
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTIONAL BLOCK DIAGRAM
8
www.ti.com
No Power
POWER SUPPLY TO PACK
FETS: OFF(*2)
REG: start Working
I2C: OFF
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
INITIALIZE FETS: OFF
REG: ON
I2C: ON
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : ON
THERMISTOR PWER CTRL : OFF
HOST FAULT MODE
REG >2.4 V REG < 2.3 V
FETS: ON *2
REG: ON
I2C: ON
CURRENT FAULT : ON
CELL MONITOR : ON
WATCHDOG : ON
THERMISTOR PWER CTRL : ON
NORMAL MODE
RESET WDTF LATCH
HOST CLOCK STOP
STATE CTL REGISTER b1 = 1
AND NO SUPPLY POWER TO PACK
FETS: OFF
REG: ON
I2C: ON
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
SLEEP MODE
SLEEP MODE EXIT BY
STATE CTL REGISTER b1 = 0
AND SLEEP PIN = GND
*1
FETS: OFF
REG: OFF
I2C: OFF
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
SHIP MODE
SHIP MODE SET BY STATE CTL REGISTER
b1 = 1 AND NO SUPPLY POWER TO PACK
FETS: OFF
REG: ON
I2C: ON
CURRENT FAULT : ON
CELL MONITOR : ON
WATCHDOG : ON
THERMISTOR PWER CTRL : ON
CURRENT DETECT MODE
STATE CTL REGISTER b0 = 1
or SLEEP PIN = REG or OPEN
*1
RESET CURRENT LATCH
IFAULT
SHIP MODE SET BY
STATE CTL REGISTER
b1 = 1 AND NO SUPPLY
POWER TO PACK
Interrupt Request When
Enrering These States
*1: Interrupt Request is Granted When Only External Sleep Pin Changes
*2: When PMS connect to Pack, Default State of CHG FET is ON.
SHIP MODE EXIT BY POWER
SUPPLY TO PACK
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
STATE DIAGRAM
9
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FUNCTIONAL DESCRIPTION
Low-Dropout Regulator (REG)
Initialization
Overload Detection
Short-Circuit Detection
Overload and Short-Circuit Delay
Overload and Short-Circuit Response
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
The inputs for this regulator can be derived from the battery cell stack (BAT) or the pack positive terminal(PACK). The output is typically 3.3 V with the minimum output capacitance for stable operation is 4.7 µF and isalso internally current limited. During normal operation, the regulator limits output current to typically 50 mA.
The bq29312 internal control circuit is powered by the REG voltage, which it also monitors. When the voltage atREG falls below 2.3 V, the internal circuit turns off the FETs and disables all controllable functions, including theREG and TOUT outputs. REG does not start up unless a voltage above V
(STARTUP)
is supplied to the PACKterminal. After the regulator has started, based on PACK voltage, it keeps operating through the BAT input, evenif the PACK voltage is removed. If the BAT input is below the minimum operating range, then the bq29312 doesnot operate if the supply to the PACK input is removed. After start up, when the REG voltage is above 2.4 V, thebq29312 is in Normal mode.
The initial state of the CHG output depends on the PMS input. If PMS = PACK then CHG = ON however, if PMS= GND then CHG = OFF.
The overload detection is used to detect abnormal currents in the discharge direction. This feature is used toprotect the pass FETs, cells and any other inline components from excessive current conditions. The detectioncircuit also incorporates a blanking delay before driving the control for the pass FETs to the OFF state. Theoverload sense voltage is set in the OLV register, and delay time is set in the OLT register. The overloadthreshold can be programmed from 50 mV to 205 mV in 5-mV steps with the default being 50 mV and hysteresisof 10 mV.
The short current circuit detection is used to detect abnormal current in either the charge or discharge direction.This safety feature is used to protect the pass FETs, cells, and any other inline components from excessivecurrent conditions. The detection circuit also incorporates a blanking delay before driving the control for the passFETs to the OFF state. The short- circuit thresholds and delay time are set in the SCC and SCD registersrespectively where SCC is for charging and SCD is for discharge. The short-circuit threshold can be programmedfrom 100 mV to 475 mV in 25-mV steps with the default being 100 mV and hysteresis of 50 mV.
The overload delay (default =1 ms) allows the system to momentarily accept a high current condition withoutdisconnecting the supply to the load. The delay time can be increased via the OLT register, which can beprogrammed for a range of 1 ms to 31 ms with steps of 2 ms.
The short-circuit delay (default = 0 µs) is programmable in the SCC and SCD registers. This register can beprogrammed from 0 µs to 915 µs with steps of 61 µs.
When an overload or short-circuit fault is detected, the FETs are turned off. The STATUS (b0 …b2) registerreports the details of short-circuit (charge), short-circuit (discharge), and overload. The respective STATUS(b0 …b2) bits are set to 1 and the XALERT output is triggered. This condition is latched until the CONTROL (b0)is set and then reset. If a FET is turned on via resetting CONTROL (b0) and the error condition is still present onthe system, then the device reenters the protection response state.
10
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Cell Voltage
Calibration of Cell Voltage Monitor Amplifier Gain
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTIONAL DESCRIPTION (continued)
The cell voltage is translated to allow a system host to measure individual series elements of the battery. Theseries element voltage is translated to a GND-based voltage equal to 0.15 ±0.002 of the series element voltage.This provides a range from 0 V to 4.5 V. The translation output is inversely proportional to the input using thefollowing equation.
Where, V
(CELL OUT)
= –K ×V
(CELL IN)
+ 0.975 (V)
Programming CELL_SEL (b1, b0) selects the individual series element. The CELL_SEL (b3, b2) selects thevoltage monitor mode, cell monitor, offset etc.
The cell voltage monitor amplifier has an offset and to increase accuracy this can be calibrated.
There are a couple of method by calibration circumstance.
The following procedure shows how to measure and calculate the offset and gain as one of example.•Step 1– Set CAL1=1, CAL0=1, CELL1=0, CELL0=0, VMEN=1– V
REF
is trimmed to 0.975 V within ±1%, measuring V
REF
eliminates its error.– Measure internal reference voltage V
REF
from VCELL directly.– VREF=measured reference voltage•Step 2– Set CAL1=0, CAL0=0, CELL1=0, CELL0=0, VMEN=1– The output voltage includes the offset and represented by:V
O(4-5)
= V
REF
+ (1 + K) ×V
OS
(V)Where K = CELL Scaling Factor– V
OS
= Offset voltage at input of the internal operational-amplifier•Step 3– Set CAL1=1, CAL0=0, CELL1=0, CELL0=0, VMEN=1– Measuring scaled REF voltage through VCELL amp.– The output voltage includes the scale factor error and offset and is represented by:V
(OUTR)
= V
REF
+ (1 + K) ×V
OS
– K ×V
REF
(V)•Step 4– Calculate (V
O(4-5)
– V
(OUTR
)/V
REF– The result is the actual scaling factor, K
(ACT)
and is represented by:K
(ACT)
= (V
O(4-5)
– V
(OUTR)
)/V
REF
= (V
REF
+ (1 + K) ×V
OS
) - (V
REF
+ (1 + K) ×V
OS
– K ×V
REF
)/ V
REF
= K ×V
REF
/V
REF
= K•Step 5– Calculate the actual offset value where:V
OS(ACT)
= (V
O(4-5)
– V
REF
)/(1 + K
(ACT)
)•Step 6– Calibrated cell voltage is calculated by:VCn – VC(n+1) = {V
REF
+ (1 + K
(ACT)
)×V
OS(ACT)
– V
(CELLOUT)
}/K
(ACT)
– {V
O(4-5)
– V
(CELLOUT)
}/K
(ACT)
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Cell Balance Control
Thermistor Drive Circuit (TOUT)
Open Drain Drive Circuit (OD)
XALERT (XALERT)
Latch Clear (LTCLR)
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTIONAL DESCRIPTION (continued)For improved measurement accuracy, V
OS(ACT)
for each cell voltage should be measured.•Set CAL1=0, CAL0=0, CELL1=0, CELL0=1, VMEN=1•Set CAL1=0, CAL0=0, CELL1=1, CELL0=0, VMEN=1•Set CAL1=0, CAL0=0, CELL1=1, CELL0=1, VMEN=1
Measuring V
O(3-4)
, V
O(2-3),
V
O(1-2),•VC4 – VC5 = {V
O(4-5)
– V(
CELLOUT)
}/ K
(ACT)•VC3 – VC4 = {V
O(3-4)
– V
(CELLOUT)
}/ K
(ACT)•VC2 – VC3 = {V
O(2-3)
– V
(CELLOUT)
}/ K
(ACT)•VC1 – VC2 = {V
O(1-2)
– V
(CELLOUT)
}/ K
(ACT)
The cell balance control allows a small bypass path to be controlled for any one series element. The purpose ofthis bypass path is to reduce the current into any one cell during charging to bring the series elements to thesame voltage. Series resistors placed between the input pins and the positive series element nodes control thebypass current value. Individual series element selection is made using bits 4 through 7 of the CELL_SELregister.
The TOUT pin can be enabled to drive a thermistor from REG. The typical thermistor resistance is 10 k Ωat25 °C. The default-state is OFF to conserve power. The maximum output impedance is 100 Ω. TOUT is enabledin FUNCTION CTL Register (bit 5).
The open drain output has 1-mA current source drive with a maximum output voltage of 25 V. The OD output isenabled or disabled by OUTPUT CTL Register (bit 4) and has a default state of OFF.
XALERT is driven low when an OL or SC current fault is detected, if the SLEEP pin changes state or a watchdogfault occurs. To clear XALERT, toggle (from 0, set to 1 then reset to 0) OUTPUT CTL (bit 0), then read theSTATUS register.
When a current limit fault or watch dog timer fault occurs, the state is latched. To clear these faults, toggle (from0, set 1 then reset to 0) LTCLR in the OUTPUT CTL register (bit 0).
Figure 1 is the LTCLR and XALERT clear example after sensing short-circuit.
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2-, 3-, or 4-Cell Configuration
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTIONAL DESCRIPTION (continued)
Figure 1. LTCLR and XALERT Clear Example After Sensing Short LTCLR and XALER Clear Example
In a 3-cell configuration, VC1 is shorted to VC2. In a 2-cell configuration, VC1 and VC2 are shorted to VC3.
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Watchdog Input (WDI)
GG Clock Never Starts
REG
GG 32 kHz Output
tWDTINT ∼ 700 mS
CHG, DSG and
ZVCHG = OFF
EXT FET Control
GG Clock Stop
CHG, DSG and
ZVCHG = OFF
tWDWT About 100 µS
REG
GG 32 kHz Output
Watchdog Sense
EXT FET Control
DSG and CHG FET Driver Control
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTIONAL DESCRIPTION (continued)
The WDI input is required as a time base for delay timing when determining overload and short-circuit delayperiods and is used as part of the system watchdog.
Initially the watchdog monitors the hosts oscillator start up, if there is no response from the host within 700 ms ofthe bq29312 reaching its minimum operating voltage, then the bq29312 turns both CHG, DSG and ZVCHG FETsOFF.
Once the watchdog has been started during this wake up period, it monitors the host for an oscillation stopcondition, which is defined as a period of 100 µs (typ) where no clock input is received. If an oscillator stopcondition is identified, then the watchdog turns the CHG, DSG and ZVCHG FETs OFF. When the host clockoscillation is started, WDF is released, but the flag is latched until LTCLR is toggled.
Figure 2. Watchdog Timing Chart—WDI Fault at Startup
Figure 3. Watchdog Timing Chart—WDI Fault After Startup
The bq29312 drives the DSG, CHG, and ZVCHG FET off if an OL or SC safety threshold is breached dependingon the current direction. The host can force any FET on or off only if the bq29312 integrated protection controlallows. The DSG and CHG FET drive gate-to-drain voltage is clamped to 15 V (typ).
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Precharge and 0 V Charging—Theory of Operation
SLEEP Control Input (SLEEP)
Power Modes
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTIONAL DESCRIPTION (continued)The default-state of the CHG and DSG FET drive is off, when PMS = GND. A host can control the FET drive byprogramming OUTPUT CTL (b3...b1) where b1 is used to control the discharge FET, b2 is used to control thecharge FET and b3 is used to control the ZVCHG FET. These controls are only valid when not in the initializedstate. The CHG drive FET can be powered by PACK and the DSG FET can be powered by BAT.
The bq29312 supports both a charger that has a precharge mode and one that does not. The bq29312 alsosupports charging even when the battery falls to 0 V. Detail is described in the application section.
The SLEEP input is pulled-up internally to REG. When SLEEP is pulled to REG, the bq29312 enters the SLEEPmode. The SLEEP mode disables all the FET outputs and the OL, SC and watchdog faults are also disabled.The RAM configuration is still valid on exit of the SLEEP mode. The host can force the bq29312 into SLEEPmode via register control also.
Table 1. SLEEP Control Input
SLEEPITEM EXIT SLEEPFUNCTION I
2
C READ/WRITE
I
2
C Read/Write ActiveREG Output ActiveExternal pin control:CHG, DSG, ZVCHG, TOUT, ODOC and SC protection:
Write is available, Last pre-sleep entry configuration is valid.(If changeSCD, SCC and OCD
but read is disabled configuration, latest write data is valid.)CELL Translation DisabledPACKOUT, VMENCell Balancing:
CB[3:0]
Watchdog: WDDIS
The bq29312 has three power modes, Normal, Sleep, and Ship. The following table outlines the operationalfunctions during these power modes.
Table 2. Power Modes
POWER TO EXIT POWERTO ENTER POWER MODE MODE DESCRIPTIONMODE MODE
Normal SLEEP = GND and The battery is in normal operation with protection, powerSTATE CTL( b0) = 0 and management and battery monitoring functions available andSTATE CTL( b1) = 0 operating.
The supply current of this mode varies as the host can enableand disable various power management features.Sleep {SLEEP = REG (floating) or SLEEP = GND and All functions stop except LDO and I
2
C interface.STATE CTL( b0) = 1 } and STATE CTL( b0) = 0
On entry to this mode, all registers are masked off keeping theirSTATE CTL( b1) = 0
state.
The host controller can change the RAM registers via the I
2
Cinterface, but reading data is disabled until exit of Sleep mode.Ship STATE CTL( b1) = 1 Supply voltage to PACK The bq29312 is completely shut down as in the sleep mode. InAnd supply at the PACK pin is addition the REG output is disabled, I
2
C interface is poweredremoved down and memory is not valid.
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Communications
A5
SCLK
SDATA A6 ACKR/WA0A4 R5R6R7 R0 D7ACK D6 D5 D0 ACK
0 0 00
… … …
… … …
Slave Address Register Address DataStart Stop
Note: Slave = bq29312
A5
SCLK
SDATA
Stop
A6 ACKR/WA0 R6R7 R0 A6ACK A0 R/W ACK D7
0 1 0
D6 D0 NACK
… … … …
… … …
0 0
Slave Address Register Address
Data
Start
Note: Slave = bq29312
Slave Address Slave Drives
The Data Master Drives
NACK and Stop
A5
SCLK
SDATA
Stop
A6 ACKR/WA0 R6R7 R0 A6ACK A0 R/W ACK D7
0 0 0
D0 NACKA5
Stop Start
… … … …
……
……
Slave Address Register
Address
Start
Note: Slave = bq29312
Slave Address Slave Drives
The Data Master Drives
NACK and Stop
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
The I
2
C compatible serial communications provides read and write access to the bq29312 data area. The data isclocked via separate data (SDATA) and clock (SCLK) pins. The bq29312 acts as a slave device and does notgenerate clock pulses. Communication to the bq29312 is provided from GPIO pins or an I
2
C supporting port of ahost system controller. The slave address for the bq29312 is 7 bits and the value is 0100 000 (0x20).
(MSB) I
2
C ADDRESS +R/W BIT (LSB)
(MSB) I
2
C ADDRESS (0x20) (LSB)
Write
(1)
00 1 0 0 0 0 0Read 1
(1) Bit 0: 0 = write, 1= read
The bq29312 does not have the following functions compatible with the I
2
C specification.•The bq29312 is always regarded as a slave.•The bq29312 does not return a NACK for an invalid register address.•The bq29312 does not support the general code of the I
2
C specification, and therefore does not return anACK.
•The bq29312 does not support the address auto increment, which allows continuous reading and writing.•The bq29312 allows data to written or read from the same location without resending the location address.
Figure 4. I
2
C-Bus Write to bq29312
Figure 5. I
2
C-Bus Read from bq29312: Protocol A
Figure 6. I
2
C-Bus Read from bq29312: Protocol B
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Register Map
STATUS : Status register
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
The bq29312 has 9 addressable registers. These registers provide status, control, and configuration informationfor the battery protection system.
Table 3. Addressable Registers
NAME ADDR TYPE DESCRIPTION
STATUS 0x00 R Status registerOUTPUT CTL 0x01 R/W Output pin control from system hostSTATE CTL 0x02 R/W State controlFUNCTION CTL 0x03 R/W Function controlCELL _SEL 0x04 R/W Battery cell select for cell translation and balance bypass and select mode for calibrationOLV 0x05 R/W Overload threshold voltageOLT 0x06 R/W Overload delay timeSCC 0x07 R/W Short-circuit current threshold voltage and delay for chargeSCD 0x08 R/W Short-circuit current threshold voltage and delay for discharge
STATUS REGISTER (0x00)
7 6 5 4 3 2 1 00 0 ZVCLMP SLEEPDET WDF OL SCCHG SCDSG
The STATUS register provides information about the current state of the bq29312. Reading the STATUS registerclears the XALERT pin.
STATUS b0 (SCDSG): This bit indicates a short-circuit in the discharge direction.0 = Current below the short-circuit threshold in the discharge direction (default).1 = Current greater than or equal to the short-circuit threshold in the discharge direction.
STATUS b1 (SCCHG): This bit indicates a short-circuit in the charge direction.0 = Current below the short-circuit threshold in the charge direction (default).1 = Current greater than or equal to the short-circuit threshold in the charge direction.
STATUS b2 (OL): This bit indicates an overload condition.0 = Current less than or equal to the overload threshold (default).1 = Current greater than overload threshold.
STATUS b3 (WDF): This bit indicates a watchdog fault condition has occurred.0 = 32 kHz oscillation is normal (default).1 = 32 kHz oscillation stopped or not started and the watchdog has timed out.
STATUS b4 (SLEEPDET): This bit indicates the bq29312 is SLEEP mode.0 = bq29312 is not SLEEP mode (default).1 = bq29312 is SLEEP mode.
STATUS b5 (ZVCLMP): This bit indicates ZVCHG output is clamped.0 = ZVCHG pin is not clamped (default).1 = ZVCHG pin is clamped.
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OUTPUT CTL: Output Control Register
STATE CTL: State Control Register
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
OUTPUT CTL REGISTER (0x01)
7 6 5 4 3 2 1 00 0 0 OD XZVCHG CHG DSG LTCLR
The OUTPUT CTL register controls the outputs of the bq29312 and can be used to clear certain states.
OUTPUT CTL b0 (LTCLR): When a current limit fault or watchdog timer fault is latched, this bit releases the faultlatch when toggled from 0 to 1 and back to 0 (default =0).0 = (default)
0->1 ->0 clears the fault latches
OUTPUT CTL b1 (DSG): This bit controls the external discharge FET.0 = discharge FET is off and is controlled by the system host (default).1 = discharge FET is on and the bq29312 is in normal operating mode.
OUTPUT CTL b2 (CHG): This bit controls the external charge FET.
PMS=GND
0 = charge FET is off and is controlled by the system host (default).1 = charge FET is on and the bq29312 is in normal operating mode.
PMS=PACK
0 = charge FET is off and is controlled by the system host.1 = charge FET is on and the bq29312 is in normal operating mode (default).
OUTPUT CTL b3 (XZVCHG): This bit controls the external ZVCHG FET.0 = ZVCHG FET is on and is controlled by the system host (default).1 = ZVCHG FET is off and the bq29312 is in normal operating mode.
OUTPUT CTL b4 (OD): This bit enables or disables the OD output.0 = OD is high impedance (default).1 = OD output is active (GND).
STATE CTL REGISTER (0x02)
7 6 5 4 3 2 1 00 0 0 0 0 WDDIS SHIP SLEEP
The STATE CTL register controls the state of the bq29312.
STATE CTL b0 (SLEEP): This bit is used to enter the sleep power mode.0 = bq29312 exits sleep mode (default).1 = bq29312 enters the sleep mode.
STATE CTL b1 (SHIP): This bit is used to enter the ship power mode when pack supply voltage is not applied.0 = bq29312 in normal mode (default).1 = bq29312 enters ship mode when pack voltage is removed.
STATE CTL b2 (WDDIS): This bit is used to enable or disable the watchdog timer function.0 = enable clock monitoring (default).1 = disable clock monitoring.
NOTE: Use caution when setting the WDDIS. For example, when the 32-kHz input fails, the overload andshort-circuit delay timers no longer function because they use the same WDI input. If the WDI input clock stops,these current protections do not function. WDF should be enabled at any time for maximum safety. If thewatchdog function is disabled, the CHG and DSG FETs should be turned off.
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FUNCTION CTL: Function Control Register
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
FUNCTION CTL REGISTER (0x03)
7 6 5 4 3 2 1 00 0 TOUT XSCD SSCC XOL PACKOUT VMEN
The FUNCTION CTL register enables and disables functons of the bq29312.
FUNCTION CTL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function.0 = disable voltage monitoring (default). CELL output is pulled down to GND level.1 = enable voltage monitoring.
FUNCTION CTL b1 (PACKOUT): This bit is used to translate the PACK input to the CELL pin when VMEN=1The pack voltage is divided by 25 and is presented on CELL regardless of the CELL_SEL register settings.0 = disable PACK OUT (default).1 = enable PACK OUT.
FUNCTION CTL b2 (XOL): This bit enables or disables the over current sense function.0 = enable over load sense (default).1 = disable over load sense.
FUNCTION CTL b3 (XSCC): This bit enables or disables the short current sense function of charging.0 = enable short-circuit current sense in charge direction (default).1 = disable short-circuit current sense in charge direction.
FUNCTION CTL b4 (XSCD): This bit enables or disables the short current sense function of discharge.0 = enable short-circuit current sense in discharge direction (default).1 = disable short-circuit current sense in discharge direction.
FUNCTION CTL b5 (TOUT): This bit controls the power to the thermistor.0 = thermistor power is off (default).1 = thermistor power is on.
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CELL SEL: Cell Select Register
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
CELL_SEL REGISTER (0x04)
7 6 5 4 3 2 1 0CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0
This register determines cell selection for voltage measurement and translation, cell balancing and theoperational mode of the cell voltage monitoring.
CELL_SEL b0–b1 (CELL0–CELL1): These two bits select the series cell for voltage measurement translation.
CELL1 CELL0 SELECTED CELL
0 0 VC4–VC5, Bottom series element (Default)0 1 VC4–VC3, Second lowest series element1 0 VC3–VC2, Second highest series element1 1 VC1–VC2, Top series element
CELL_SEL b2–b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block.
CAL1 CAL0 SELECTED MODE
0 0 Cell translation for selected cell (default)0 1 Offset measurement for selected cell1 0 Monitor the V
REF
value for gain calibration1 1 Monitor the V
REF
directly value for gain calibration, bypassing the translation circuit
CELL_SEL b4–b7 (CB0–CB3): These 4 bits select the series cell for cell balance bypass path.
CELL SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path0 = disable bottom series cell balance charge bypass path (default).1 = enable bottom series cell balance charge bypass path.
CELL SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.0 = disable series cell balance charge bypass path (default).1 = enable series cell balance charge bypass path.
CELL SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path.0 = disable series cell balance charge bypass path (default).1 = enable series cell balance charge bypass path.
CELL SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path.0 = disable series cell balance charge bypass path (default).1 = enable series cell balance charge bypass path.
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OLV: Overload Voltage Threshold Register
OLT: Overload Blanking Delay Time Register
SCC: Short Circuit in Charge Configuration Register
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
OLV REGISTER (0x05)
7 6 5 4 3 2 1 00 0 0 OLV4 OLV3 OLV2 OLV1 OLV0
OLV (b4–b0): These five bits select the value of the over load threshold with a default of 00000.
OLV (b4–b0) configuration bits with corresponding voltage threshold00000 0.050 V 01000 0.090 V 10000 0.130 V 11000 0.170 V00001 0.055 V 01001 0.095 V 10001 0.135 V 11001 0.175 V00010 0.060 V 01010 0.100 V 10010 0.140 V 11010 0.180 V00011 0.065 V 01011 0.105 V 10011 0.145 V 11011 0.185 V00100 0.070 V 01100 0.110 V 10100 0.150 V 11100 0.190 V00101 0.075 V 01101 0.115 V 10101 0.155 V 11101 0.195 V00110 0.080 V 01110 0.120 V 10110 0.160 V 11110 0.200 V00111 0.085 V 01111 0.125 V 10111 0.165 V 11111 0.205 V
OLT REGISTER (0x06)
7 6 5 4 3 2 1 00 0 0 0 OLT3 OLT2 OLT1 OLT0
OLT(b3–b0): These four bits select the value of the delay time for overload with a default of 0000.
OLT(b3–b0) configuration bits with corresponding delay time0000 1 ms 0100 9 ms 1000 17 ms 1100 25 ms0001 3 ms 0101 11 ms 1001 19 ms 1101 27 ms0010 5 ms 0110 13 ms 1010 21 ms 1110 29 ms0011 7 ms 0111 15 ms 1011 23 ms 1111 31 ms
SCC REGISTER (0x07)
7 6 5 4 3 2 1 0SCCT3 SCCT2 SCCT1 SCCT0 SCCV3 SCCV2 SCCV1 SCCV0
This register selects the short-circuit threshold voltage and delay for charge.
SCC(b3–b0) : These bits select the value of the short-circuit voltage threshold with 0000 as the default.
SCC(b3–b0) with corresponding SC threshold voltage0000 0.100 V 0100 0.200 V 1000 0.300 V 1100 0.400 V0001 0.125 V 0101 0.225 V 1001 0.325 V 1101 0.425 V0010 0.150 V 0110 0.250 V 1010 0.350 V 1110 0.450 V0011 0.175 V 0111 0.275 V 1011 0.375 V 1111 0.475 V
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SCD: Short Circuit in Discharge Configuration Register
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
SCC(b7–b4): These bits select the value of the short-circuit delay time. Exceeding the short-circuit voltagethreshold for longer than this period will turn off the corresponding CHG, DSG, and ZVCHG output. 0000 is thedefault.
SCC(b7–b4) with corresponding SC delay time0000 0 µs 0100 244 µs 1000 488 µs 1100 732 µs0001 61 µs 0101 305 µs 1001 549 µs 1101 793 µs0010 122 µs 0110 366 µs 1010 610 µs 1110 854 µs0011 183 µs 0111 427 µs 1011 671 µs 1111 915 µs
SCD REGISTER (0x08)
7 6 5 4 3 2 1 0SCDT3 SCDT2 SCDT1 SCDT0 SCDV3 SCDV2 SCDV1 SCDV0
This register selects the short-circuit threshold voltage and delay for discharge.
SCD(b3–b0) with corresponding SC threshold voltage with 0000 as the default.
SCD(b3–b0): These bits select the value of the short-circuit voltage threshold0000 0.10 V 0100 0.20 V 1000 0.30 V 1100 0.40 V0001 0.125 V 0101 0.225 V 1001 0.325 V 1101 0.425 V0010 0.150 V 0110 0.250 V 1010 0.350 V 1110 0.450 V0011 0.175 V 0111 0.275 V 1011 0.375 V 1111 0.475 V
SCD(b7–b4): These bits select the value of the short-circuit delay time. Exceeding the short-circuit voltagethreshold for longer than this period will turn off the corresponding CHG, DSG, and ZVCHG output as has 0000as the default.
SCD(b7-b4) with corresponding SC delay time0000 0 µs 0100 244 µs 1000 488 µs 1100 732 µs0001 61 µs 0101 305 µs 1001 549 µs 1101 793 µs0010 122 µs 0110 366 µs 1010 610 µs 1110 854 µs0011 183 µs 0111 427 µs 1011 671 µs 1111 915 µs
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APPLICATION INFORMATION
Precharge and 0-V Charging—Theory of Operation
0-V Charge FET Mode
PACK
ZVCHG
PMS
REG
CHG
DSG
BAT
ZVCHG-FET
R(ZVCHG)
4.7 µF
Battery
DSG-FET CHG-FET Pack+ IZVCHG
IFASTCHG
CV
CC
Charger
DC Input
bq29312
I(ZVCHG) = 0 V Percharge Current
I(FASTCHG) = Fast Current
OD
NC
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
In order to charge, the charge FET (CHG-FET) must be turned on to create a current path. When the V
(BAT)
is 0V and CHG-FET = ON, the V
(PACK)
is as low as the battery voltage. In this case, the supply voltage for the deviceis too low to operate. There are 3 possible configurations for this function and the bq29312 can be easilyconfigured according to the application needs. The 3 modes are 0-V Charge FET Mode, Common FET Modeand Precharge FET Mode.1. 0-V Charge FET Mode – Dedicates a precharge current path using an additional FET (ZVCHG-FET) tosustain the PACK+ voltage level. The host charger is expected to provide a precharge function.2. Common FET Mode – Does not use a dedicated precharge FET. The charge FET (CHG-FET) is assured tobe set to ON state as default. The charger is expected to provide a precharge function.3. Precharge FET Mode – Dedicates a precharge current path using an additional open drain (OD) pin driveFET (PCHG-FET) FET to sustain the PACK+ voltage level. The charger does not provide any prechargefunction.
In this mode, a dedicated precharge current path using an additional FET (ZVCHG-FET) is required to sustain asuitable PACK+ voltage level. The charger is expected to provide the precharge function in this mode where theprecharge current level is suitable to charge cells below a set level, typically below 3 V per cell. When the lowestcell voltage rises above this level, then a fast charging current is applied by the charger.
The circuit diagram for this method is shown in Figure 7 , showing how the additional FET is added in parallelwith the charge FET (CHG-FET).
Figure 7. 0-V Charge FET Mode Circuit
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VDS
Precharge
Current
ID
VGS
Point A
Point B
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)In order to pass 0 V or precharge current an appropriate gate-source voltage V
(GS)
, for ZVCHG-FET must beapplied. Here, V
(PACK)
can be expressed in terms of V
(GS)
as follows:V
(PACK)
= V
(ZVCHG)
+ V
(GS)
(ZVCHG-FET gate - source voltage)
Figure 8. Drain Current vs Drain-Source Voltage Characteristics
In the bq29312, the initial state is for CHG-FET = OFF and ZVCHG-FET = ON with the V
(ZVCHG)
clamped at 3.5 Vinitially. Then the charger applies a constant current and raises V
(PACK)
high enough to pass the prechargecurrent, point A. For example, if the V
(GS)
is 2 V at this point, V
(PACK)
is 3.5 V + 2 V = 5.5 V. Also, theZVCHG-FET is used in its MOS saturation region at this point so that V
(DS)
is expressed as follows:V
(PACK)
= V
(BAT)
+ V
F
+ V
DS(ZVCHG-FET)
where V
(F)
= 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V.
This derives the following equation:V
DS
= 4.8 V - V
(BAT)
As the battery is charged V
(BAT)
increases and the V
(DS)
voltage decreases reaching its linear region. Forexample: If the linear region is 0.2 V, this state continues until V
(BAT)
= 4.6 V, (4.8 V - 0.2 V).
As V
(BAT)
increases further, V
(PACK)
and the V
(GS)
voltage increase. But the V
DS
remains at 0.2 V because theZVCHG-FET is driven in its MOS linear region, point B.V
(PACK)
= V
F
+ 0.2 V +
V(BAT)
where V
F
= 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V
The R
(ZVCHG)
purpose is to split heat dissipation across the ZVCHG-FET and the resistor.
ZVCHG pin behavior is shown in Figure 9 where V
(ZVCHG)
is set to 0 V at the beginning.
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t - Time - mS
Voltage - V
0 4 8 12 16
4
20
10
0
8
2
6
14
18
12
16
20
V(PACK)
3.5 V
V(ZVCHG)=
V(PACK) - 8 V
V(ZVCHG)= V(PACK) / 2
V(BAT)
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)
Figure 9. Voltage Transition at ZVCHG, PACK and BAT
As V
(PACK)
exceeds 7 V, V
(ZVCHG)
= V
(PACK)
/2. However, V
(ZVCHG)
is maintained to limit the voltage between PACKand ZVCHG at a maximum of 8 V(typ). This limitation is intended to avoid excessive voltage between the gateand the source of ZVCHG-FET.
The signal timing is shown in Figure 10 . When precharge begins (V
(BAT)
= 0 V) V
(PACK)
is clamped to 3.5 V andholds the supply voltage for bq29312 operation. After V
(BAT)
reaches sufficient voltage high enough for bq29312operation, the CHG-FET and the DSG-FET are turned ON and ZVCHG-FET is turned OFF.
Although the current path is changed, the same precharging current is still applied. When V
(BAT)
reaches the fastcharging voltage (typical 3 V per cell), the charger switches into fast charging mode.
25
www.ti.com
ON ZVCHG FET = OFF
OFF CHG FET = ON
OFF CHG FET = ON
3.5 V+VGS(ZVCHGFET)
0 V
3.3 V
0 V
V = VPACK*(1/2)
3.5 V (typ.)
0 V
”L” (1 V)
”L” (1 V)
0 V
Fast Charge Current
0 V and Precharge Current
0 A
0 V Charge
Mode Precharge
Mode
Fast Charge Mode
V(PACK)
REG
ZVCHG
GHD
DSG
Battery
Voltage
Charge
Current
Common FET
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)
Figure 10. Signal Timing of Pins During 0 V Charging and Precharging (0 V Charge FET)
This mode does not require a dedicated precharge FET (ZVCHG-FET). The charge FET (CHG-FET) is ON atinitialization of the bq29312 when PMS = V
(PACK)
allowing for 0 V or precharge current to flow. The applicationcircuit is shown in Figure 11 . The charger is expected to provide the precharge function in this mode, where thecharger provides a precharge current level suitable to charge cells below a set level, typically below 3.0 V percell. When the lowest cell voltage rises above this level then a fast charging current is applied.
When the charger is connected the voltage at PMS rises. Once it is above 0.7 V, the CHG output is driven toGND which turns ON the CHG-FET. The charging current flows through the CHG-FET and a back diode ofDSG-FET. The pack voltage is represented by the following equation.V
(PACK)
= V
(BAT)
+ V
F
+ V
DS(CHG-FET)
Where V
F
= 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V.
While V
(PACK)
is maintained above 0.7 V the precharging current is maintained. While V
(PACK)
and V
(BAT)
areunder the bq29312 supply voltage then the bq29312 regulator is inactive and the host controller is not functional.Thus, any protection features of this chipset do not function during this period. This state continues until V
(PACK)goes higher than the bq29312 minimum supply voltage.
When V
(BAT)
rises and V
(PACK)
reaches bq29312 minimum supply voltage, the REG output is active providing a3.3 V (typ) supply to the host. When this level is reached the CHG pin changes its state from GND to the levelcontrolled with CHG bit in bq29312 registers. In this state, the CHG output level is driven by a clamp circuit sothat its voltage level changes from 0 V to 1 V. Also, the host controller is active and can turn ON the DSG-FET.
26
www.ti.com
PACK
ZVCHG
PMS
REG
CHG
DSG
BAT
4.7 µF
Battery
DSG-FET CHG-FET Pack+ I(ZVCHG)
I(FASTCHG)
CV
CC
Charger
DC Input
bq29312
I(ZVCHG) = 0 V Percharge Current
I(FASTCHG) = Fast Current
OD
NC
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)The disadvantages is that during 0 V charging, bq29312 is inactive. The device does not protect the battery anddoes not update battery information (now is 0 V charging) to the PC.
There are two advantage of this configuration:1. The voltage between BAT and PACK is lower. Higher precharge current is allowed due to less heat loss isthe FET and no external resistor required.2. The charge FET is turned on during precharging. The precharge current can be fully controlled by thecharger.
Figure 11. Common FET Mode Circuit Diagram
The signal timing during the common FET mode is shown in Figure 12 . The CHG-FET is turned on when thecharger is connected. As V
(BAT)
rises and V
(PACK)
reaches the bq29312 minimum supply voltage, the REG outputbecomes active and the host controller starts to work.
When V
(PACK)
becomes high enough, the host controller turns ON the DSG-FET. The charger enters the fastcharging mode when V
(BAT)
reaches the fast charge level.
27
www.ti.com
0 V Precharge Mode Fast Charge Mode
V(PACK)
REG
PMS
CHG
DSG
Battery
Voltage
Charge
Current
Host =
Inactive Host = Active
Set to ”L” as
PMS = PACK Set to ”L” by Host
Host Sets
DSG-FET to ON
0.7 V
0 V
3.3 V
0 V
0 V
”L” (1 V)
0 V
”L” (1 V)
0 V
Fast Charge Current
0 V and Precharge Current
0 A
Precharge FET
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)
Figure 12. Signal Timing of Pins During 0 V Charging and Precharging (Common FET)
This mode has a dedicated precharge current path using an additional open drain driven FET (PCHG-FET) andsustains the V
(PACK)
level. In this mode, where the PMS input is connected to GND, the bq29312 and hostcombine to provide the precharge function by limiting the fast charge current which is provided by the systemside charger.
Figure 13 shows the bq29312 application circuit in this mode.
28
www.ti.com
PACK
ZVCHG
PMS
REG
CHG
DSG
BAT
PCHG-FET
R(PCHG)
4.7 µF
Battery
DSG-FET CHG-FET Pack+ I(FASTCHG)
CV
CC
Charger
DC Input
bq29312
I(FASTCHG) = Fast Current
OD
Host
SCLK SDATA
ID
VSD
ID = (V(PACK) - V(BAT) - VDS)/R(PCHG)
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)
Figure 13. Precharge FET Mode Circuit Diagram
The PCHG-FET is driven by the OD output and the resister R
(PCHG)
in the precharge path limits the prechargecurrent. When OD = GND then the PCHG-FET is ON. The precharge current is represented by the followingequation:
I
(PCHG)
= ID = ( V
(PACK)
- V
(BAT)
- V
DS
)/R
(PCHG)•A load curve of the PCHG-FET is shown in Figure 14 . When the drain-source voltage (V
DS
) is high enough,the PCHG-FET operates in the linear region and has low resistance. By approximating V
DS
as 0 V, theprecharge current, I
(PCHG)
is expressed as below.•I
(PCHG)
= ( V
(PACK)
- V
(BAT)
)/R
(PCHG)
Figure 14. PCHG-FET ID—VDS Characteristic
During the precharge phase, CHG-FET is turned OFF and PCHG-FET is turned ON. When all the cell voltagesmeasured by the host reach the fast charge threshold, the host controller turns ON CHG-FET and turns OFFPCHG-FET. The signal timing is shown in Figure 15 .
When the charger is connected, CHG-FET, DSG-FET and PCHG-FET are already in the OFF state. When thecharger in connected it applies V
(PACK)
. The bq29312 REG output then becomes active and supplies power to thehost controller. As the host controller starts up, it turns on the OD pin and the precharge current is enabled.
29
www.ti.com
Charge CV
0 V
Host : Active
3.3 V
0 V
OFF
CHG FET = OFF
OFF
0 V
DSG FET = ON
”L” (1 V)
OFF ”L” (1 V)
0 V
Fast Charge Current
0 V and Precharge Current
0 A
0 V and
Precharge Mode Fast Charge
Mode
V(PACK)
REG
CHG
DSG
Battery
Voltage
Charge
Current Charge
Charge Mode
OD PCHG FET = ON
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)In this configuration, attention must be paid to high power consumption in the PCHG-FET and the series resistorR
(PCHG)
. The highest power is consumed when V
BAT
= 0 V, where it is the highest differential between the PACKand BAT pins. For example, the power consumption in 4 series cells with 17.4 V fast charge voltage and R
(PCHG)= 188 Ωis expressed below.•I
PCHG
= (17.4 V – 0.0 V)/188 Ω= 92.6 mA•17.4 V ×92.6 mA = 1.61 W
An optional solution is to combine a thermistor with a resistor to create R
(PCHG)
, therefore, as temperatureincreases, the current reduces.
Once the lowest cell voltage reaches the fast charge level (typ 3.0 V per cell), the host controller turns ONCHG-FET and DSG-FET, and turns OFF PCHG-FET.
It is also appropriate to turn on DSG-FET during precharge in order to supply precharge current efficiently, asshown in Figure 15 .
Figure 15. Signal Timing of Pins During 0 V Charging and Precharging (Precharge FET)
30
www.ti.com
Summary
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
APPLICATION INFORMATION (continued)
The three types of 0-V charge options available with the bq29312 are summarized in Table 4 .
Table 4. Charge Options
CHARGE MODE TYPE HOST CHARGE CAPABILITIES KEY APPLICATION CIRCUIT NOTES
PMS = GND1) 0-V Charge FET Fast charge and precharge ZVCHG: Drives 0-V charge FET (ZVCHG-FET)OD: Not usedPMS = PACK2) Common FET Fast charge and precharge ZVCHG: Not usedOD: Not usedPMS = GND3) Precharge FET Fast charge but no precharge function ZVCHG: Not usedOD: Drives the precharge FET (PCHG-FET)
There a number of tradeoffs between the various 0-V charge modes which are discussed below.•0-V Charge FET (1) vs Common FET (2)
When the charger has both of precharge and charging functions, there are two types of circuit configurationavailable.
1. 0-V Charge FET – The bq29312 is active even during precharge. Therefore, the host can update the batterystatus to the system and protect the battery pack by detecting abnormal conditions.– A high voltage is applied on the 0-V charge FET at 0-V cell voltage. In order to avoid excessive heatgeneration the 0-V charge current must be limited.2. Common FET – During 0-V charge the bq29312 and the host are not active. Therefore, they cannot protectthe cells and cannot update the battery status to the system.– The bq29312 can tolerate high 0-V charge current as heat generation is not excessive.– A dedicated FET for the 0-V charge is not required.•0-V Charge FET (1) vs Precharge FET (3)
The current paths of the 0-V charge FET (1) and Precharge FET (3) modes are the same. If the 0-V charge FET(1) mode is used with chargers without precharge function, the bq29312 consumes extra current of up to 1 mA inorder to turn ON the ZVCHG output.1. If the charger has a precharge function - ZVCHG-FET is turned ON only during 0-V charging. In this case, 1mA increase is not a concern because the charger is connected during the 0-V charging period.2. If the charger does not have precharge function - The ZVCHG-FET must be turned ON during 0-V chargingand also precharging. When the battery reaches an over discharged state, it must turn OFF DSG-FET andCHG-FET and turn ON ZVCHG-FET. The reason for this is the battery must keep the 0-V charge path whilewaiting for a charger to be connected to limit the current.– Consuming 1 mA, while waiting for a charger to be connected in over discharge state, is significant ifcompared to current consumption of other modes.•Precharge FET (3)
If the precharge FET (3) mode is used with a charger with precharge function, care must be taken as limiting the0-V charge current with resistance may cause some issues. The charger may start fast charge immediately, ordetect an abnormal condition.
When the charger is connected, the charger may raise the output voltage to force the precharge current. In orderto assure a supply voltage for the bq29312 during 0-V charging, the resistance of a series resister (R
PCHG
) mustbe high enough. This may result in a very high V
PACK
, and some chargers may detect it as an abnormalcondition.
31
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BQ29312PW NRND TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
BQ29312PWG4 NRND TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
BQ29312PWR NRND TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
BQ29312PWRG4 NRND TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples Not Available
BQ29312RGE OBSOLETE VQFN RGE 24 TBD Call TI Call TI Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ29312PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ29312PWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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