AS1702 - AS1705
1.8W Single-Channel Audio Power Amplifiers
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Datasheet
1 General Description
The AS1702 - AS1705 are single-channel differential audio power-
amplifiers designed to drive 4 and 8Ω loads. The integrated gain cir-
cuitry of these amplifiers and their small size make them ideal for
2.7- to 5V -powered portable audio devices.
The differential input design improves noise rejection and provides
common-mode rejection. A bridge-tied load (BTL) design minimizes
external component count, while providing high-fidelity audio power
amplification.
The devices deliver 1.8W continuous average power per channel to
a 4Ω load with less than 1% total harmonic distortion (plus noise),
while operating from a single 2.7 to 5V supply.
For reduced component designs, the devices are available with dif-
ferent gain levels as shown in Table 1.
Integrated shutdown circuitry disables the bias generator and ampli-
fiers, and reduces quiescent current consumption to less than
100nA. The shutdown input can be set active-high or active-low. All
devices contain click-and-pop suppression circuitry that reduces
audible clicks and pops during power-up and shutdown.
The AS1702 - AS1705 are pin compatible with the LM4895 and the
MAX9718A/B/C/D. The devices are available in a 10-pin MSOP
package and a 10-pin DFN package.
Figure 1. Simplified Block Diagram
2 Key Features
2.7V to 5.5V (VCC) Single-Supply Operation
THD+N: 1.8W into 4Ω at 1% (per Channel)
Differential Input
Adjustable Gain Option (AS1702)
Internal Fixed Gain to Reduce External Component Count
(AS1703, AS1704, AS1705)
<100nA Low-Power Shutdown Mode
Click and Pop Suppression
Pin-Compatible to National Semiconductor LM4895 (AS1705)
and Maxim MAX9718A/B/C/D
Operating Temperature Range: -40 to +85ºC
Package Types
- 10-pin MSOP
- 10-pin DFN
3 Applications
The devices are ideal as audio front-ends for battery powered audio
devices such as MP3 and CD players, mobile phones, PDAs, porta-
ble DVD players, and any other hand-held battery-powered device.
Table 1. Standard Products
Model Gain
AS1702 Adjustable (via external components)
AS1703 AV = 0dB
AS1704 AV = 3dB
AS1705 AV = 6dB
AS1702/AS1703/
AS1704/AS1705
Single Supply
2.7V to 5.5V
RL = 4 or 8Ω
+
–
4
IN+
10
OUT+
2
IN-
1
SHDN
3
SHDM
6
OUT-
9
VCC
7
GND
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AS1702 - AS1705
Datasheet - Pinout
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
Pin Descriptions
Table 2. Pin Descriptions – MSOP-10 and TDFN-10 Package
Pin Name Description
1SHDN
Shutdown Input. The polarity of this pin is dependent on the state of pin SHDM.
2IN-
Inverting Input
3SHDM
Shutdown-Mode Polarity Input. This pin controls the polarity of pin SHDN. Connect this pin high
for an active-high SHDN input. Connect this pin low for an active-low SHDN input (see Table 6 on
page 11).
4IN+
Non-Inverting Input
5BIAS
DC Bias Bypass
6OUT-
Bridge Amplifier Negative Output
7GND
Ground
8N/C
Not Connected. No internal connection.
9VCC
Power Supply
10 OUT+ Bridge Amplifier Positive Output
1
2
3
4
10
9
8
7
SHDN
IN-
SHDM
IN+
OUT+
VCC
N/C
GND
AS1702/
AS1703/
AS1704/
AS1705
5
BIAS 6OUT-
1
2
3
4
10
9
8
7
SHDN
IN-
SHDM
IN+
OUT+
VCC
N/C
GND
AS1702V/
AS1703V/
AS1704V/
AS1705V
5
BIAS 6OUT-
10-pin MSOP Package 10-pin DFN Package
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AS1702 - AS1705
Datashee t - A b s o l u t e M a x i mu m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those list ed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
† Using PCB metal plane and thermally-conductive paste.
Table 3. Absolute Maximum Ratings
Parameter Min Max Units Comments
Electrical Parameters
Supply Voltage (VDD to VSS)-0.3+7V
Supply Voltage (All Other Pins) VSS
- 0.3 VDD
+ 0.3 V
Input Current (latch-up immunity) -50 50 mA Norm: JEDEC 78
Electrostatic Discharge
Electrostatic Discharge HBM 1 kV Norm: MIL 883 E method 3015
Temperature Ranges and Storage Conditions
Continuous Power Dissipation
(TAMB = +70ºC) †600 mW MSOP-10
Continuous Power Dissipation
(TAMB = +25ºC) †1000 mW MSOP-10
Storage Temperature Range -65 +150 ºC
Junction Temperature +150 ºC
Package Body Temperature +260 ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
Humidity non-condensing 585%
Moisture Sensitive Level 1 Represents a max. floor life time of unlimited
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AS1702 - AS1705
Datasheet - Electrical Characteristics
6 Electrical Characteristics
All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control)
methods.
5V Operation
Table 4. Electrical Characteristics – 5V Supply, TAMB = +25ºC (unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Unit
TAMB Operat ing Temperature
Range -40 +85 °C
VCC Supply Voltage TAMB = -40 to +85ºC 2.7 5.5 V
ICC Supply Current 1
1. Quiescent power supply current is specified and tested with no load. Quiescent power supply current depends on the offset voltage when a
practical load is connected to the amplifier .
VIN- = VIN+ = VBIAS;TAMB = -40 to +85ºC 8 10.4 mA
ISHDN Shutdown Supply SHDN = SHDM = GND 0.05 1 µA
VIH SHDN, SHDM Threshold 0.7 x VCC V
VIL 0.3 x VCC
VBIAS Common-Mode Bias
Voltage 2
2. Common-mode bias voltage is the voltage on BIAS and is nominally VCC/2.
VCC/2 - 5% VCC/2 VCC/2 + 5% V
VOS Output Offset Voltage VIN- = VIN+ = VBIAS AV = 0dB (AS1703) ±1 ±10 mVAV = 3dB (AS1704) ±1 ±15
AV = 6dB (AS1705) ±1 ±20
VIC Common-Mode Input
Voltage 3
3. Guaranteed by design.
Inferred from CMRR Test AV = 0dB (AS1703) 0.2 VCC - 0.2
V
AV = 3dB (AS1704) 0.9 VCC - 0.9
AV = 6dB (AS1705) 1.5 VCC - 1.5
External Gain AS1702 1.5 VCC - 1.5
RIN Input Impedance AS1703, AS1704, AS1705 10 15 20 kΩ
CMRR Common-Mode Rejection
Ratio fN = 1kHz 64 dB
PSRR Power Supply Rejection
Ratio VIN- = VIN+ = VBIAS;
VRIPPLE = 200mVp-p; RL
= 8Ω; CBIAS = 1µF
f = 217Hz 79 dB
f = 1kHz 73
POUT Output Power 4
4. Guaranteed by design.
THD+N = 1%;
fIN = 1kHz RL = 8Ω0.8 1.25 W
RL = 4Ω1.8
THD+N Total Harmonic Distortion
plus Noise 5
5. Measurement bandwidth for THD+N is 22Hz to 22kHz.
RL = 4Ω, fIN = 1kHz, POUT = 1.28W,
VCC = 5V, AV = 6dB 0.06 %
RL = 8Ω, fIN = 1kHz, POUT = 0.9W,
VCC = 5V, AV = 6dB 0.03
Gain Accuracy AS1703, AS1704, AS1705 ±1 ±2 %
Thermal Shutdown
Threshold +145 ºC
Thermal Shutdown
Hysteresis 9ºC
tPU Power-up/Enable from
Shutdown Time 125 ms
tSHDN Shutdown Time 3.5 µs
VPOP Turn-Off Transient 6
6. Peak voltage measured at power-on, power-off, into or out of SHDN. Bandwidth defined by A-weighted filters, inputs at AC GND. VCC rise
and fall times ≥ 1ms.
50 mV
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AS1702 - AS1705
Datasheet - Electrical Characteristics
3V Operation
Table 5. Electrical Characteristics – 3V Supply, TAMB = +25ºC (unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Unit
ICC Supply Current 1
1. Quiescent power supply current is specified and tested with no load. Quiescent power supply current depends on the offset voltage when a
practical load is connected to the amplifier. Guaranteed by design.
VIN- = VIN+ = VBIAS;
TAMB = -40 to +85ºC, per amplifier 7.5 mA
ISHDN Shutdown Supply SHDN = SHDM = GND per amplifier 0.05 1 µA
VIH SHDN, SHDM
Threshold 0.7 x VCC V
VIL 0.3 x VCC
VBIAS Common-Mode Bias
Voltage 2
2. Common-mode bias voltage is the voltage on BIAS and is nominally VCC/2.
VCC/2 - 5% VCC/2 VCC/2 + 5% V
VOS Output Offset Voltage VIN- = VIN+ = VBIAS
AV = 0dB (AS1703) ±1 ±10 mVAV = 3dB (AS1704) ±1 ±15
AV = 6dB (AS1705) ±1 ±20
VIC Common-Mode Input
Voltage 3
3. Guaranteed by design.
Inferred from CMRR Test AV = 0dB (AS1703) 0.2 VCC - 0.2
mV
AV = 3dB (AS1704) 0.6 VCC - 0.6
AV = 6dB (AS1705) 1.0 VCC - 1.0
External gain AS1702 1.0 VCC - 1.0
RIN Input Impedance AS1703, AS1704, AS1705 10 15 20 kΩ
CMRR Common-Mode
Rejection Ratio fN = 1kHz 64 dB
PSRR Power Supply Rejection
Ratio VIN- = VIN+ = VBIAS;
VRIPPLE = 200mVp-p; RL =
8Ω; CBIAS = 1µF
f = 217Hz 79 dB
f = 1kHz 73
POUT Output Power 4
4. Guaranteed by design.
RL = 4Ω, THD+N = 1%; fIN = 1kHz 640 mW
RL = 8Ω, THD+N = 1%; fIN = 1kHz 440
THD+N Total Harmonic
Distortion plus Noise 5
5. Measurement bandwidth for THD+N is 22Hz to 22kHz.
RL = 4Ω, fIN = 1kHz, POUT = 460mW, AV = 6dB 0.06 %
RL = 8Ω, fIN = 1kHz, POUT = 330mW, AV = 6dB 0.04
Gain Accuracy AS1703, AS1704, AS1705 ±1 ±2 %
Thermal Shutdown
Threshold +145 ºC
Thermal Shutdown
Hysteresis 9ºC
tPU Power-up/Enable from
Shutdown Time 125 ms
tSHDN Shutdown Time 3.5 µs
VPOP Turn-Off Transient 6
6. Peak voltage measured at power-on, power-off, into or out of SHDN. Bandwidth defined by A-weighted filters, inputs at AC GND. VCC rise
and fall times ≥ 1ms.
50 mV
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AS1702 - AS1705
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
Figure 3. THD + Noise vs. Frequency; Figure 4. THD + Noise vs. Frequency;
VDD = 3V, RL = 4Ω, AV = 2VDD = 3V, RL = 8Ω, Av = 2
Figure 5. THD + Noise vs. Frequency; Figure 6. THD + Noise vs. Frequency;
VDD =5V, RL = 4Ω, Av = 2VDD = 5V, RL = 8Ω, Av = 2
Figure 7. THD + Noise vs. Frequency; Figure 8. THD + Noise vs. Output Power;
VDD = 5V, RL = 4Ω, Av = 4VDD = 5V, RL = 8Ω, Av = 4
0.001
0.01
0.1
1
10
10 100 1000 10000
Frequency (H z)
THD + N (%) e
0.001
0.01
0.1
1
10
10 100 1000 10000
Frequency (H z)
THD + N (%) e
POUT = 50mW
POUT = 250mW
POUT = 100mW
POUT = 250mW
0.001
0.01
0.1
1
10
10 100 1000 10000
Frequency [Hz]
THD + N [%]
0.001
0.01
0.1
1
10
10 100 1000 10000
Frequency (H z)
THD + N (%) e
POUT = 1W
POUT = 250mW POUT = 250mW
POUT = 750mW
0.001
0.01
0.1
1
10
10 100 1000 10000
Frequenzy (H z)
THD + N (%) e
0.001
0.01
0.1
1
10
10 100 1000 10000
Frequency (H z)
THD + N (%) e
POUT = 200mW
POUT = 1W POUT = 200mW
POUT = 800mW
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AS1702 - AS1705
Datasheet - Typical Operating Characteristics
Figure 9. THD + Noise vs. Output Power; Figure 10. THD + Noise vs. Output Power;
VDD = 3V, RL = 4Ω, Av = 2VDD = 3V, RL = 8Ω, Av = 2
Figure 11. THD + Noise vs. Output Power; Figure 12. THD + Noise vs. Output Power;
VDD = 3V, RL = 4Ω, Av = 4VDD = 3V, RL = 8Ω, Av = 4
Figure 13. THD + Noise vs. Output Power; Figure 14. THD + Noise vs. Output Power;
VDD = 5V, RL = 4Ω, Av = 2VDD = 5V, RL = 8Ω, Av = 2
0.01
0.1
1
10
0 0.1 0.2 0.3 0.4 0.5 0.6
O utput Power (W )
THD+N ( %) .
0.01
0.1
1
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
O utput Power (W )
THD+N ( %) .
fIN = 1kHz
fIN = 100Hz
fIN = 1kHz
fIN = 100Hz
0.01
0.1
1
10
0 0.1 0.2 0.3 0.4 0.5 0.6
O utput Power (W )
THD+N ( %) .
0.01
0.1
1
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
O utput Power (W )
THD+N ( %) .
fIN = 1kHz
fIN = 100Hz
fIN = 100Hz
fIN = 1kHz
0.01
0.1
1
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
O utput Power (W )
THD+N ( %) .
0.01
0.1
1
10
0 0.4 0.8 1.2 1.6 2
O ut put Power (W)
THD+N ( %) .
fIN = 1kHz
fIN = 100Hz
fIN = 1kHz
fIN = 100Hz
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AS1702 - AS1705
Datasheet - Typical Operating Characteristics
Figure 15. THD + Noise vs. Output Power; Figure 16. THD + Noise vs. Output Power;
VDD = 5V, RL = 4Ω, Av = 4VDD = 5V, RL = 8Ω, Av = 4
Figure 17. Output Power vs. Load Resistance; Figure 18. Output Power vs. Load Resistance;
VDD = 3V VDD = 5V
Figure 19. Output Power vs. Supply Voltage; Figure 20. Output Power vs. Supply Voltage;
RL = 4ΩRL = 8Ω
0.01
0.1
1
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
O utput Power (W )
THD+N ( %) .
0.01
0.1
1
10
0 0.4 0.8 1.2 1.6 2
O utput Power (W )
THD+N ( %) .
fIN = 1kHz
fIN = 100Hz
fIN = 1kHz
fIN = 100Hz
0
100
200
300
400
500
600
700
800
900
110100
Load Resistance (Ω)
Output Power (W) e
0
0.4
0.8
1.2
1.6
2
2.4
1 10 100
Load Resistance (Ω)
Output Power (W) e
POUT @ THD = 10%
POUT @ THD = 1%
POUT @ THD = 10%
POUT @ THD = 1%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.5 3.5 4.5 5.5
Supply V oltage (V )
Output Power (W) e
0
0.5
1
1.5
2
2.5
3
2.5 3.5 4.5 5.5
Supply Voltage (V)
Output Power (W) e
POUT @ 10% (W)
POUT @ 1% (W)
POUT @ 10% (W)
POUT @ 1% (W)
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AS1702 - AS1705
Datasheet - Typical Operating Characteristics
Figure 21. Power Dissipation vs. Output Power; Figure 22. Power Dissipation vs. Output Power;
VDD = 3V, RL = 4Ω, Av = 2. f = 1kHzVDD = 3V, RL = 8Ω, Av = 2, f = 1kHz
Figure 23. Power Dissipation vs. Output Power; Figure 24. Power Dissipation vs. Output Power;
VDD = 5V, RL = 4Ω, Av = 2. f = 1kHz VDD = 5V, RL = 8Ω, Av = 2. f = 1kHz
Figure 25. Shutdown Hysteresis Voltage; VDD = 3V Figure 26. Shutdown Hysteresis Voltage; VDD = 5V
0
100
200
300
400
500
600
700
0 100 200 300 400 500 600 700
Outp ut Power (mW)
Power Dissipation (mW) e
0
50
100
150
200
250
300
350
0 100 200 300 400 500
Outp ut Power (mW)
Power Dissipation (mW) e
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0 0.3 0.6 0.9 1.2 1.5 1.8
Outp ut Power (W)
Power Dissipation (W) e
0.0
0.2
0.4
0.6
0.8
1.0
0.00.20.40.60.81.01.21.4
Outp ut Power (W)
Power Dissipation (W) e
0
0.5
1
1.5
2
2.5
3
0123
Shutdown V oltage (V )
Common Mode Bias Voltage (V) e
0
0.5
1
1.5
2
2.5
3
0123
Shutdown V oltage (V )
Common Mode Bias Voltage (V) e
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AS1702 - AS1705
Datasheet - Typical Operating Characteristics
Figure 27. Shutdown Current vs. Temperature Figure 28. Shutdown Current vs. Temperature
Figure 29. Power Supply Rejection Ratio vs. Frequency
-0.03
-0.02
-0.01
0.00
0.01
0.02
0.03
-40-200 20406080
Temperature (°C)
Shutdown Current (uA) e
0
2
4
6
8
10
-40-20 0 20406080
Temperature (°C)
Supply Current (mA) e
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
20
30
40
50
60
70
80
90
100
10 100 1000 10000 100000
F r equency ( Hz)
PSRR (dB)
VDD = 5V
VDD = 3V
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AS1702 - AS1705
Datasheet - Detailed Description
8 Detailed Description
The AS1702 - AS1705 are 1.8W high output-current audio amplifiers (configured as BTL amplifiers), and contain integrated low-power shutdown
and click- and pop-suppression circuitry. Two inputs (SHDM and SHDN) allow shutdown mode to be configured as active-high or active-low (see
Shutdown Mode on page 11).
Each device has either adjustable or fixed gains (0dB, 3dB, 6dB) (see Ordering Information on page 19).
Bias
The devices operate from a single 2.7 to 5.5V supply and contain an internally generated, common-mode bias voltage of:
referenced to ground. Bias provides click-and-pop suppression and sets the DC bias level for the audio outputs. Select the value of the bias
bypass capacitor as described in Section BIAS Capacitor on page 15.
Note: Do not connect external loads to BIAS as this can adversely affect overall device performance.
Shutdown Mode
All devices implement a 100nA, low-power shutdown circuit which reduces quiescent current consumption. As shutdown mode commences, the
bias circuitry is automatically disabled, the device outputs go high impedance, and bias is driven to GND.
The SHDM input controls the po larity of SHDN:
Drive SHDM high for an active-low SHDN input.
Drive SHDM low for an active-high SHDN input.
Click-and-Pop Suppression
During power-up, the device common-mode bias voltage (VBIAS (see page 4)) ramps to the DC bias point. When entering shutdown, the device
outputs are driven high impedance to 100kΩ between both outputs minimizing the energy present in the audio band, thus preventing clicks and
pops.
Table 6. Shutdown Mode Selection Configurations
SHDM SHDN Mode
0 0 Shut down Mode Enabled
0 1 Normal Operation Enabled
1 0 Normal Operation Enabled
1 1 Shut down Mode Enabled
2(EQ 1)
VCC
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AS1702 - AS1705
Datasheet - Application Inform ation
9 Application Information
Figure 30. AS1702 Typical Application Diagram
Figure 31. AS1703, AS1704, AS1705 Typical Application Diagram
AV = 2
Bias
Generator
AS1702
Shutdown
Control
+
–
RIN
10kΩ
2.7 to 5.5V
Supply
Inverting
Differential Input
Non-Inverting
Differential Input
10µF
CIN*
10µF
* Optional
CBIAS
0.1µF
RIN
10kΩ
RF
20kΩ
CIN*
10µF
10
OUT+
2
IN-
1
SHDN
3
SHDM
6
OUT-
9
VCC
7
GND
4
IN+
5
BIAS
RF
20kΩ
AS1703/
AS1704/
AS1705
+
–
R2
R2
R1
R1
AV = 1
AV = 1.41
AV = 2
CIN*
10µF
CIN*
10µF
Inverting
Differential Input
Bias
Generator
Shutdown
Control
2.7 to 5.5V
Supply
Non-Inverting
Differential Input
10µF
* Optional
CBIAS
0.1µF
10
OUT+
2
IN-
1
SHDN
3
SHDM
6
OUT-
9
VCC
7
GND
4
IN+
5
BIAS
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AS1702 - AS1705
Datasheet - Application Inform ation
BTL Amplifier
All devices are designed to drive loads differentially in a bridge-tied load (BTL) configuration.
Figure 32. Bridge Tied Load Configuration
The BTL configuration doubles the output voltage (illustrated in Figure 32) compared to a single-ended amplifier under similar conditions. Thus,
the differential gain of the device (AVD) is twice the closed-loop gain of the input amplifier. The effective gain is given by:
Substituting 2 x VOUT(P-P) for VOUT(P-P) into (EQ 3) and (EQ 4) yields four times the output power due to doubling of the output voltage:
Since the BTL outputs are biased at mid-supply, there is no net DC voltage across the load. This eliminates the need for the large, expensive,
performance degrading DC-blocking capacitors required by single-ended amplifiers.
Power Dissipation and Heat Sinking
Normally, the devices dissipate a significant amount of power . The maximum power dissipation is given in Table 3 as Continuous Power Dissipa-
tion, or it can be calculated by:
where TJ(MAX) is +150ºC, TAMB (see Table 3) is the ambient temperature, and ΘJA is the reciprocal of the derating factor in ºC/W as specified
in Table 3. For example, ΘJA of the TQFN package is +59.2ºC/W.
The increased power delivered by a BTL configuration results in an increase in internal power dissipation versus a single-ended configuration.
The maximum internal power dissipation for a given VCC and load is given by:
If the internal power dissipation exceeds the maximum allowed for a given package, power dissipation should be reduced by increasing the
ground plane heat-sinking capabilities and increasing the size of the device traces (see Layout and Grounding Considerations on page 15). Addi-
tionally, reducing VCC, increasing load impedance, and decreasing ambient temperature can reduce device power dissipation.
+1
-1
VOUT(P-P)
VOUT(P-P)
2 x VOUT(P-P)
AVD = 2 x RIN (EQ 2)
RF
VRMS = 2 2 (EQ 3)
VOUT(P-P)
POUT = RL(EQ 4)
VRMS2
PDISSPKF(MAX) =
Θ
JA (EQ 5)
TJ(MAX) -TA
PDISSPKF(MAX) =
π2RL
(EQ 6)
2VCC2
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AS1702 - AS1705
Datasheet - Application Inform ation
The integrated thermal-overload protection circuitry limits the total device power dissipation. Note that if the junction temperature is ≥ +1 45ºC,
the integrated thermal-overload protection circuitry will disable the amplifier output stage. If the junction temperature is reduced by 9°, the ampli-
fiers will be re-enabled.
Note: A pulsing output under continuous thermal overload results as the device heats and cools.
Fixed Differential Gain (AS1703, AS1704, and AS1705)
The AS1703, AS1704, and AS1705 contain different internally-fixed gains (see Ordering Information on page 19). A fixed gain facilitates simpli-
fied designs, decreased footprint size, and elimination of external gain-setting resistors.
The fixed gain values are achieved using resistors R1 and R2 (see Figure 31 on page 12).
Adjustable Differential Gain (AS1702)
Gain-Setting Resistors
The AS1702 uses external feedback resistors, RF and RIN (Figure 33), to set the gain of the device as:
where AV is the desired voltage gain. For example, RIN = 10kΩ, RF = 20kΩ yields a gain of 2V/V, or 6dB.
Note: RF can be either fixed or variable, allowing the gain to be controlled by software (using a AS150x digital potentiometer. For more infor-
mation on the AS1500 family of digital potentiometers, refer to the latest version of the AS150x data sheet, available from the austria-
microsystems website http://www.austriamicrosystems.com.)
Figure 33. Setting the AS1702 Gain
Input Filter
The BTL inputs can be biased at voltages other than mid-supply . However, the integrated common-mode feedback circuit adjusts for inpu t bias,
ensuring the outputs are still biased at mid-supply. Input capacitors are not required if the common-mode input voltage (VIC) is within the range
specified in Table 4 and Table 5.
AV = RIN (EQ 7)
RF
AS1702
+
–
RF
20kΩ
RF
20kΩ
Bias
Generator
Inverting
Differe ntial Input
Non-Inverting
Differe ntial Input
CIN*
10µF
CIN*
10µF
RIN
10kΩ
RIN
10kΩ
* Optional
CBIAS
0.1µF
10
OUT+
2
IN- 6
OUT-
4
IN+
5
BIAS
www.austriamicrosystems.com/Audio/Amps/AS1702-05 Revision 1.48 15 - 20
AS1702 - AS1705
Datasheet - Application Inform ation
Input capacitor CIN (if used), in conjunction with RIN, forms a high-pass filter that removes the DC bias from an incoming signal. The AC coupling
capacitor allows the amplifier to bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the high-pass filter
is given by:
Setting f-3dB too high affects the low-frequency response of the amplifier. Capacitors with dielectrics that have low-voltage coefficients such as
tantalum or aluminum electrolytic should be used, since capacitors with high-voltage coefficients, such as ceramics, can increase distortion at
low frequencies.
BIAS Capacitor
BIAS is the output of the internally generated VCC/2 bias voltage. The BIAS bypass capacitor , CBIAS, improves PSRR and THD+N by reducing
power supply noise and other noise sources at the common-mode bias node, and also generates the click- and pop-less DC bias waveform for
the amplifiers. Bypass BIAS with a 0.1µF capacitor to GND. Larger values of CBIAS (up to 1µF) improve PSRR, but increase tON/tOFF times.
For example, a 1µF CBIAS capacitor increases tON/tOFF by 10 and improves PSRR by 20dB (at 1kHz).
Note: Do not connect external loads to BIAS.
Supply Bypassing
Proper power supply bypassing – connect a 10µF ceramic capacitor (CBIAS) from VCC to GND – will ensure low-noise, low-distortion perfor-
mance of the device. Additional bulk capacitance can be added as required.
Note: Place CBIAS as close to the device as possible.
Layout and Grounding Considerations
Well designed PC board layout is essential for optimizing device performance. Use large traces for the power supply inputs and amplifier outputs
to minimize losses due to parasitic trace resistance and route heat away from the device.
Good grounding improves audio performance and prevents digital switching noise from coupling onto the audio signal.
f-3dB = (EQ 8)
1
2πRINCIN
www.austriamicrosystems.com/Audio/Amps/AS1702-05 Revision 1.48 16 - 20
AS1702 - AS1705
Datasheet - Package Drawings and Markings
10 Package Drawings and Markings
Figure 34. 10-pin DFN Marking
Table 7. Packaging Code YYWWQZZ
Figure 35. 10 -pin MSOP Marking
Table 8. Packaging Code YYWWRZZ
YY WW QZZ
last two digits of the current year manufacturing week plant identifier free choice / traceability code
YY WW RZZ
last two digits of the current year manufacturing week plant identifier free choice / traceability code
www.austriamicrosystems.com/Audio/Amps/AS1702-05 Revision 1.48 19 - 20
AS1702 - AS1705
Datasheet - Ordering Information
11 Ordering Information
The devices are available as the standard products shown in Table 9.
Note: All products are RoHS compliant.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
Table 9. Ordering Information
Odering Code Marking Description Gain Delivery Form Package
AS1702-T AS1702 1.8W Single-Channel Audio Power Amplifiers Adjustable Tape and Reel
10-pin MSOP
AS1703-T AS1703 1.8W Single-Channel Audio Power Amplifiers Av =0dB Tape and Reel
AS1704-T AS1704 1.8W Single-Channel Audio Power Amplifiers Av =3dB Ta pe and Re el
AS1705-T AS1704 1.8W Single-Channel Audio Power Amplifiers Av =6dB Ta pe and Re el
AS1702V-T 1702 1.8W Single-Channel Audio Power Amplifiers Adjustable Tape and Reel
10-pin DFN
AS1703V-T 17 03 1.8W Single-Chann el Au dio Power Amplifiers Av =0dB Tape and Reel
AS1704V-T 1704 1.8W Single-Channel Audio Power Amplifiers Av =3dB Tape and Reel
AS1705V-T 1705 1.8W Single-Channel Audio Power Amplifiers Av =6dB Tape and Reel
www.austriamicrosystems.com/Audio/Amps/AS17002-05 Revision 1.48 20 - 20
AS1702 - AS1705
Datasheet
Copyrights
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All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory , implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
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