Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
1 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date Remark
1.0 Initial issue Nov.20,2004
1.1
1.2
1.3
Add 1. High speed clock cycle time:-6<166MHz> ;-7<133MHz>
2. Product family
3.Order information
Add tWR /tDPL in page 20
Add 60 ball BGA 6.4x10.1mm package
Mar.16,2005
Oct. 31, 2005
Nov. 30, 2006
1.4 Revise AC/DC char. for Fab process technology upgraded Jan. 22, 2009
1.5 Revised the typo of tRAS(max) unit on page 20 Jun. 12, 2009
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
2 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
DESCRIPTION
The CS56A64163 is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by16
bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable device to be useful
for a variety of high bandwidth, high performance memory system applications.
FEATURES
z JEDEC standard 3.3V power supply
z High speed clock cycle time : -6<166MHz> ; -7<133MHz>
z LVTTL compatible with multiplexed address
z Four banks operation
z MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
z All inputs are sampled at the positive going edge of the
system clock
z DQM for masking
z Auto & self refresh
z 64ms refresh period (4K cycle)
Product Family
Part No. Operating Temp Vcc. Range Speed (ns) Package Type
Dice
54 TSOP 2
0~70oC 2.7~3.6 6/7
60 Ball BGA
Dice
54 TSOP 2
CS56A64163
-40~85oC 2.7~3.6 6/7
60 Ball BGA
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
3 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
PIN ASSIGNMENT
54L TSOP 2- 400mil 60 Ball BGA- 6.4x10.1mm
FUNCTIONAL BLOCK DIAGRAM
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
4 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
PIN FUNCTION DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
/CS Chip Select Disables or enables device operation by masking or enabling all inputs
except CLK , CKE and L(U)DQM
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command. Disable input
buffers for power down in standby
A0 ~ A11 Address Row / column address are multiplexed on the same pins. Row address :
RA0~RA11, column address : CA0~CA7
A12, A13 Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS Row Address Strobe
/RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column Address Strobe Latches column address on the positive going edge of the CLK with CAS
low. Enables column access.
/WE
Write Enable Enables write operation and row precharge. Latches data in starting from
/CAS, /WE active.
L(U)DQM
Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks
data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ
Data Output Power / Ground Isolated power supply and ground for the output buffers to provide improved
noise immunity.
NC No Connection This pin is recommended to be left No Connection on the device.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
5 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
SIMPLIFIED TRUTH TABLE
COMMAND CKEn-1 CKEn /CS /RAS /CAS /WE DQM
A13
A12
A10
/AP
A11
A9~A0
Note
Register Mode Register set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry
H
L
L L L H X X
3
L H H H X 3
Refresh
Self
Refresh
Exit L H
H X X X X
X
3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column
Address
Auto Precharge Enable
H X L H L H X V
H
Column
Address
(A0~A7) 4,5
Auto Precharge Disable L 4
Write &
Column
Address
Auto Precharge Enable H X L H L L X V
H
Column
Address
(A0~A7) 4,5
Burst Stop H X L H H L X X 6
Bank Selection V L
Precharge
All Banks
H X L L H L X
X H
X
H X X X
Entry H L
L V V V
X
Clock Suspend or
Active Power Down
Exit L H X X X X X
X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power Down
Mode
Exit L H
L V V V
X
X
DQM H X V X 7
H X X X No Operating Command (NOP)
H X
L H H H
X X
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note: 1. OP Code: Operating Code, A0~A11 & A13~A12: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
6 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
command is meant by “Auto”. Auto/self refresh can be issued only at all banks precharge state.
4. A13~A12: Bank select addresses. If both A13 and A12 are “Low” at read, write, row active and precharge, bank A is
selected. If both A13 is “Low” and A12 is “High” at read, write, row active and precharge, bank B is selected. If both A13 is
“High” and A12 is “Low” at read, write, row active and precharge, bank C is selected. If both A13 and A12 are “High” at
read, write, row active and precharge, bank D is selected If A10/AP is “High” at row precharge, A13 and A12 is ignored
and all banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued. Another bank read/write
command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end
of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
MODE REGISTER TABLE TO PROGRAM MODES
Register Programmed with MRS
Address A13~A12 A11~A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function Reserved Reserved
Write Burst
Length
Test Mode CAS Latency Burst Type Burst Length
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 Reserved 0 1 0 2 0 1 0 4 4
1 1 Reserved 0 1 1 3 0 1 1 8 8
Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved
A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved
0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved
Full Page Length: 256
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
7 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
BURST SEQUENCE (BURST LENGTH = 4)
Initial Adrress
A1 A0
Sequential Interleave
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial
A2 A1 A0
Sequential Interleave
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
8 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
DEVICE OPERATIONS
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode, and
mode register.
The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS . Each
operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined by
commands and all operations are referenced to a positive clock edge.
The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column address
counter.
The mode register is to justify the SDRAM operation and function into desired system conditions. MODE
REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming.
POWER UP & INITIALIZATION SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the
inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh (REF) commands.
5. Issue mode register set (MRS) command to initialize the mode register. RFU (Reserved for future use) should stay “0”
during this cycle.
Note: 1. It is recommended that DQM and CKE keep track VCC to insure that output is High-Z state.
2. The Mode Register Set command can be set before 2 Auto-refresh commands.
CLOCK (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and internal
burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the CLK. CKE is a
high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be
internally masked. During idle state (all banks have been precharged), the Power Down mode (standby) is entered with
CKE = Low and this will make extremely low standby current.
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge
rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE).
With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP).
The precharged bank is selected by combination of AP and A13, A12 when Precharge command is asserted. If AP = High,
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
9 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
all banks are precharged regardless of A13, A12 (PALL). If AP = Low, a bank to be selected by A12, A13 is precharged
(PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
assertion. This auto precharge is entered by AP = High when a read or write command is asserted.
Enable and disable auto precharge function are controlled by A10/AP in read/write command:
A10/AP A12 A13 Operating
0 0 Disable auto precharge, leave A bank active at end of burst.
0 1 Disable auto precharge, leave B bank active at end of burst.
1 0 Disable auto precharge, leave C bank active at end of burst.
0
1 1 Disable auto precharge, leave D bank active at end of burst.
0 0 Enable auto precharge , precharge bank A at end of burst.
0 1 Enable auto precharge , precharge bank B at end of burst.
1 0 Enable auto precharge , precharge bank C at end of burst.
1
1 1 Enable auto precharge , precharge bank D at end of burst.
A10/AP and A13~A12 control bank precharge when
precharge is asserted:
A10/AP A12 A13 Precharge
0 0 0 Bank A
0 0 1 Bank B
0 1 0 Bank C
0 1 1 Bank D
1 X X All Banks
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command.
The Auto-refresh command should also be asserted every 16 µs or a total 4096 refresh commands within a 64 ms
period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh
function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDRAM
enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level state) and
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
10 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should
only be issued after last read data has been appeared on DQ.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior
to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No operation command (NOP)
should be asserted within one tRC period. CKE should be held High within one tRC period after tCKSP.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields;
Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line.
Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS
command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM.
CHIP SELECT ( CS )
CS enables all commands inputs, RAS , CAS , and WE , and address input. When CS is High, command signals
are negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT ( RAS , CAS , and WE )
Unlike a conventional DRAM, RAS , CAS , and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS . Instead, each combination of RAS , CAS , and WE input in conjunction with CS input at a rising
edge of the CLK determines SDRAM operation.
ADDRESS INPUT (A0 to A11)
Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. A total of twenty
address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to reduce
the pin count of the address line. At a Bank Active command (ACTV), twelve Row addresses are initially latched and the
remainders of eight Column addresses are then latched by a Column address strobe command of either a Read
command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A12, A13)
This SDRAM has four banks and each bank is organized as 1 M words by 16-bit.
Bank selection by A13, A12 occurs at Bank Active command (ACTV) followed by read (READ or READA), write
(WRIT or WRITA), and precharge command (PRE).
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
11 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
BANK ACTIVATE
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with
desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD
(min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock cycles required between bank activate and read or write
command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to
reduce chip area; therefore it restricts the activation of four banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum time
required between activating different bank. The number of clock cycles required between different bank activation must
be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by tRAS (min). Every SDRAM bank activate command must
satisfy tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any
bank can be in the active state is determined by tRAS (max) and tRAS
(max) can be calculated similar to tRCD specification.
DATA INPUTS AND OUTPUTS (DQ0 to DQ15)
Input data is latched and written into the memory at the clock following the write command input. Data output is obtained
by the following conditions followed by a read command input:
TRAC: from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.)
TCAC: from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
TAC: from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by the three
conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQML/DQMU)
DQML and DQMU are an active high enable input and has an output disable and input mask function. During burst cycle
and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output will be masked at
the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst
type.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and
by automatic strobe column address. Access time and cycle time of Burst mode is specified as tAC and tCK, respectively.
The internal column address counter operation is determined by a mode register, which defines burst type and burst
count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst mode to the next
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
12 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
stage while the remaining burst count is more than 1, the following combinations will be required:
Current Stage Next Stage Method (Assert the following command)
Burst Read Burst Read Read Command
1st Step Mask Command (Normally 3 clock cycles)
Burst Read Burst Write
2nd Step Write Command after LOWD
Burst Write Burst Write Write Command
Burst Write Burst Read Read Command
Burst Read Precharge Precharge Command
Burst Write Precharge Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an
incremental decoding scheme within a boundary address to be determined by count length; it assigns +1 to the previous
(or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0).
The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column address is even (0), the
next address will be odd (1), or vice-versa.
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation.
The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full
column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by
burst length; it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps
round to least significant address (= 0).
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
13 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
Burst Length
Starting Column
Address A2 A1 A0
Sequential Interleave
X X 0 0 – 1 0 – 1
2
X X 1 1 – 0 1 – 0
X 0 0 0 – 1 – 2 – 3 0 – 1 – 2 – 3
X 0 1 1 – 2 – 3 – 0 1 – 0 – 3 – 2
X 1 0 2 – 3 – 0 – 1 2 – 3 – 0 – 1
4
X 1 1 3 – 0 – 1 – 2 3 – 2 – 1 – 0
0 0 0 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
0 0 1 1 – 2 – 3 – 4 – 5 – 6 – 7 – 0 1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
0 1 0 2 – 3 – 4 – 5 – 6 – 7 – 0 – 1 2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
0 1 1 3 – 4 – 5 – 6 – 7 – 0 – 1 – 2 3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
1 0 0 4 – 5 – 6 – 7 – 0 – 1 – 2 – 3 4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
1 0 1 5 – 6 – 7 – 0 – 1 – 2 – 3 – 4 5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
1 1 0 6 – 7 – 0 – 1 – 2 – 3 – 4 – 5 6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
8
1 1 1 7 – 0 – 1 – 2 – 3 – 4 – 5 – 6 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column
burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps round
to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT), precharge
(PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full column burst
operation except write command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst
mode, its operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be
ignored.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted after
the self-refresh exit.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
14 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
15 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second
command
(same
bank)
First
command
MRS ACTV READ
READA
*4 WRITE WRITE
A
*4 PRE PALL REF SELF BST
MRS tRSC t
RSC t
RSC t
RSC t
RSC t
RSC t
RSC
ACTV t
RCD t
RCD t
RCD t
RCD t
RAS t
RAS 1
READ 1 1 1
*6 1 *6 1 *5 1 *5 1
READA BL+tRP
*1 *2 *3 BL+tRP BL+tRP
*5
BL+tRP
*5
BL+tRP
*3
BL+tRP
*3 *8
WRITE t
WR t
WR 1 1 tDPL *5 tDPL *5 1
WRITEA BL-1+
tDAL *3
BL-1+
tDAL BL-1+
tDAL *5
BL-1+
tDAL *5
BL-1+
tDAL *3
BL-1+
tDAL *3
PRE tRP *3 *4 t
RP 1 1
*5 tRP *3 tRP *3
*7 1
PALL tRP *4 t
RP 1 1 tRP t
RP *7 1
REF tRC t
RC t
RC t
RC t
RC t
RC t
RC
SELFX tRC t
RC t
RC t
RC t
RC t
RC t
RC
Illegal command
Notes:
*1. BL: Burst length; CL: CAS latency
*2. If tRP(min) ≤ CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*3. Assume all banks are in Idle state.
*4. Assume output is in High-Z state.
*5. Assume tRAS(min) is satisfied.
*6. Assume no I/O conflict.
*7. Assume after the last data have been appeared on DQ.
*8. If tRP(min) ≤ (CL-1) × tCK, minimum latency is a sum of (BL + CL-1) × tCK.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
16 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second
command
(other
bank)
First
command
MRS ACTV
READ
*5
READA
*5 *6
WRITE
*5
WRITE
A
*5 *6 PRE PALL REF SELF BST
MRS tRSC t
RSC t
RSC t
RSC t
RSC t
RSC t
RSC
ACTV tRRD *2 1 *7 1 *7 1 *7 1 *7 1 *6 *7 tRAS *7 1
READ 1
*2 *4 1 1 1
*10 1 *10 1 *6 1 *6 1
READA BL+tRP
*1 *2
1 *2 *4 1 *6 1 *6 1 *6 *10 1 *6 *10 1 *6 BL+tRP
*6
BL+tRP
*2
BL+tRP
*2 *9
WRITE 1
*2 *4 1 1 1 1 1 *6 tDPL *6 1
WRITEA BL-1+
tDAL *2
1 *2 *4 1 *6 1 *6 1 *6 1 *6 1 *6 BL-1+
tDAL *6
BL-1+
tDAL *2
BL-1+
tDAL *2
PRE tRP *2 *3 1 *2 *4 1 *7 1 *7 1 *7 1 *7 1 *6 *7 1 *7
tRP *2 tRP *2
*8 1
PALL tRP *3 t
RP 1 1 tRP t
RP *8 1
REF tRC t
RC t
RC t
RC t
RC t
RC t
RC
SELFX tRC t
RC t
RC t
RC t
RC t
RC t
RC
Notes:
*1. If tRP(min) ≤ CL × tCK, minimum latency is a sum of (BL + CL) × tCK.
*2. Assume bank of the object is in Idle state.
*3. Assume output is in High-Z state.
*4. tRRD(min) of other bank (second command will be asserted) is satisfied.
*5. Assume other bank is in active, read or write state.
*6. Assume tRAS(min) is satisfied.
*7. Assume other banks are not in READA/WRITA state.
*8. Assume after the last data have been appeared on DQ.
*9. If tRP(min) ≤ (CL-1) × tCK, minimum latency is a sum of (BL + CL-1) × tCK.
*10. Assume no I/O conflict.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
17 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT
Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 C
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating condition s (Voltage referenced to VSS = 0V, TA = 0 to 70 C °)
PARAMETER SYMBOL MIN TYP MAX UNIT NOTE
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current IIL -5 - 5
A 3
Output leakage current IOL -5 - 5
A 4
Note: 1. VIH(max) = 4.6V AC for pulse width ≤10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤10ns acceptable.
3. Any input 0V ≤VIN ≤VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V ≤VOUT ≤VDD.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
18 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 C
VERSION
PARAMETER SYMBOL TEST CONDITION
-6 -7
UNIT NOTE
Operating Current
(One Bank Active) ICC1 Burst Length = 1, t RC ≥t RC(min), IOL
= 0 mA,, tcc = tcc(min)
100 100 mA 1,2
ICC2P CKE ≤VIL(max), tcc = tcc(min) 2
Precharge Standby Current
in power-down mode ICC2PS CKE & CLK ≤VIL(max), tcc = ∞∞ 1
mA
ICC2N
CKE ≥VIH(min), CS ≤VIH(min), tcc =
tcc(min), Input signals are
changed one time during 2CLK
20
Precharge Standby Current
in non power-down mode
ICC2NS CKE ≥VIH(min), CLK ≤VIL(max), tcc =
∞∞input signals are stable
15
mA
ICC3P CKE ≤VIL(max), tcc = tcc(min) 10
Active Standby Current in
power-down mode ICC3PS CKE & CLK ≤VIL(max), tcc =∞ ∞∞ 10
mA
ICC3N
CKE ≥VIH(min), CS ≥VIH(min), tcc =
tcc(min), Input signals are
changed one time during 2CLK
30
Active Standby Current in
non power-down mode
(One Bank Active)
ICC3NS CLK ≤VIL(max), tcc = ∞
input signals are stable 25
mA
Operating Current
(Burst Mode) ICC4
IOL = 0 mA, Page Burst, All Bank
active, Burst Length = 4, CAS
Latency = 3
150 140 mA 1,2
Refresh Current ICC5 tRC ≥tRC(min), tCC = tcc(min) 180 mA
Self Refresh Current ICC6 CKE ≤0.2V 1 mA
Note: 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
19 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
CAPACITANCE (VDD = 3.3V, TA = 25 C °, f = 1MHZ)
PARAMETER SYMBOL MIN MAX UNIT
Input capacitance (A0 ~ A11, A13 ~ A12) CIN1 2 4 Pf
Input capacitance
(CLK, CKE, CS , RAS , CAS , WE &
L(U)DQM)
CIN2 2 4 Pf
Data input/output capacitance (DQ0 ~ DQ15) COUT 2 5 Pf
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 C ° )
PARAMETER VALUE UNIT
Input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall-time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
20 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER SYMBOL
-6 -7
UNIT NOTE
Row active to row active delay tRRD(min) 12 14 ns 1
/RAS to /CAS delay tRCD(min) 18 20 ns 1
Row precharge time tRP(min) 18 20 ns 1
tRAS(min) 40 42 ns 1
Row active time
tRAS(max) 100 us
Row cycle time @ Auto refresh tRC(min) 60 70 ns 1,3
Write recovery time tWR 10 10 ns
Data-in to Precharge Lead Time tDPL 10 10 ns
CAS latency=3 2 Number of valid Output data
CAS latency=2 1
ea 2
Note: 1. Dividing the minimum time required with clock cycle time and then rounding off to the next higher integer determine the
minimum number of clock cycles.
2. In case of row precharge interrupt, auto precharge and read burst stop.
3. A new command may be given tRFC after self refresh exit.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
21 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
-6 -7
PARAMATER SYMBOL
MIN MAX MIN MAX
UNIT NOTE
CAS latency = 3 6 7 CLK cycle time
CAS latency = 2 tCK
8 - 10 - ns 1
CAS latency = 3 5.5 6 CLK to valid
output delay CAS latency = 2 tAC 6 6
ns 1, 2
CAS latency = 3 2.5
Output data
hold time CAS latency = 2 tOH
2.5 2.5 ns 2
CLK high pulsh width tCH 2.5 2.5 ns 3
CLK low pulsh width tCL 2.5 2.5 ns 3
Input setup time tSI 1.5 1.5 ns 3
Input hold time tHI 1 1 ns 3
CLK to output in Low-Z tLZ 0 0 ns 2
CAS latency = 3 5.5 6 CLK to output
in Hi-Z CAS latency = 2 tHZ 6 6
ns
CKE Setup Time for Power Down Exit tCKSP 1.5 2 ns 4
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns, transient time compensation should be
considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
4. If input signal transition time (tT) is longer than 1 ns; [(tT/2) –0.5] ns should be added to tAC (max), tHZ
(max), and tCKSP (min) spec values, [(tT/2) –0.5] ns should be subtracted from tLZ (min), tHZ (min), and
tOH (min) spec values, and (tT –1.0) ns should be added to tCH (min), tCL (min), tSI (min), and tHI (min)
spec values.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
22 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter Symbol CS56A64163-6T CS56A64163-7T Unit
CKE to Clock Disable LCKE 1 1 cycle
DQM to Output in High-Z LDQZ 2 2 cycle
DQM to Input Data Delay LDQD 0 0 cycle
Last Output to Write Command Delay LOWD 2 2 cycle
Write Command to Input Data Delay LDWD 0 0 cycle
CL = 2 LROH2 2 2 cycle Precharge to Output in High-Z
Delay CL = 3 LROH3 3 3 cycle
CL = 2 LBSH2 2 2 cycle Burst Stop Command to
Output in High-Z Delay CL = 3 LBSH3 3 3 cycle
CAS to CAS Delay (min) LCCD 1 1 cycle
CAS Bank Delay (min) LCBD 1 1 cycle
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
CS56A64163-6T (Unit : number of clock)
tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
Frequency CAS
Latency 58ns 40ns 18ns 12ns 18ns 6ns 6ns 12ns
166 MHz (6.0ns) 3 10 7 3 2 3 1 1 2
143 MHz (7.0ns) 3 9 6 3 2 3 1 1 2
133 MHZ(7.5ns) 3 8 6 3 2 3 1 1 2
125 MHZ(8.0ns ) 2 8 5 3 2 3 1 1 2
100 MHZ(10.0ns ) 2 6 4 2 2 2 1 1 2
CS56A64163-7T (Unit : number of clock)
tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
Frequency CAS
Latency 63ns 45ns 20ns 14ns 20ns 7ns 7ns 14ns
143 MHz (6.0ns) 3 9 7 3 2 3 1 1 2
133 MHz (7.0ns) 3 9 6 3 2 3 1 1 2
125 MHZ(7.5ns 3 8 6 3 2 3 1 1 2
100 MHZ(8.0ns ) 2 7 5 2 2 2 1 1 2
83 MHZ(10.0ns ) 2 6 4 2 2 2 1 1 2
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
23 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--SETUP, HOLD AND DELAY TIME
TIMING DIAGRAM--DELAY TIME FOR POWER DOWN EXIT
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
24 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--PULSE WIDTH
TIMING DIAGRAM--ACCESS TIME
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
25 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
Notes: *1. The latency of CKE (LCKE) is one clock.
*2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
data remain the same data.
*3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM--CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
26 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
TIMING DIAGRAM--DIFFERENT BANK ADDRESS INPUT DELAY
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
27 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--DQMU, DQML - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
TIMING DIAGRAM--PRECHARGE TIMING (APPLIED TO THE SAME BANK)
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
28 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
Note: In case of CL = 2, the LROH is 2 clocks.
In case of CL = 3, the LROH is 3 clocks.
PRECHARGE means ‘PRE’ or ‘PALL’.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
29 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
TIMING DIAGRAM--WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ CL = 2)
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
30 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
TIMING DIAGRAM--READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
31 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
TIMING DIAGRAM--READ WITH AUTO-PRECHARGE
(EXAPLE @ CL = 2, BL = 2 Applied to same bank)
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
32 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--WRITE WITH AUTO-PRECHARGE *1, *2, *3
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
TIMING DIAGRAM--MODE REGISTER SET TIMING
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
33 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
TIMING DIAGRAM--AUTO-REFRESH TIMING
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF).
*2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter.
*3. NOP command should be asserted during tRC period while Auto-refresh mode.
*4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC
from the last REF command.
TIMING DIAGRAM--SELF-REFRESH ENTRY AND EXIT TIMING
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
34 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
35 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
Synchronous DRAM
1M x 16 Bit x 4 Banks CS56A64163
36 Rev. 1.5
Chiplus reserves the right to change product or specification without notice.
