IS31AP4915A 20VP-P CHARGE PUMP CERAMIC SPEAKER DRIVER August 2013 GENERAL DESCRIPTION FEATURES The IS31AP4915A features a mono power amplifier with an integrated charge-pump power supply specifically designed to drive the high capacitance of a ceramic loudspeaker. The IS31AP4915A maximizes battery life by offering high performance efficiency. The IS31AP4915A is ideally suited to deliver the high output-voltage swing required to drive ceramic/piezoelectric speakers. The device utilizes comprehensive click-and-pop suppression and shutdown control. The IS31AP4915A is fully specified over the -40C to +85C extended temperature range and is available in small lead-free 16-pin QFN (4mm x 4mm) packages. Integrated charge-pump power supply - no inductor required Thermal protection Pop reduction circuitry 20VP-P voltage swing into piezoelectric speaker QFN-16, 4mm x 4mm ESD (HBM): 2kV ESD (MM): 200V APPLICATIONS CD/MP3 players Smart phones Cellular phones PDAs Handheld gaming TYPICAL APPLICATION CIRCUIT Figure 1 Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 Typical Application Circuit 1 IS31AP4915A PIN CONFIGURATION Package Pin Configuration (Top View) QFN-16 PIN DESCRIPTION No. Pin Description 1 C1P Charge pump flying capacitor positive terminal. 2 PGND Power ground, connect to ground. 3 C1N Charge pump flying capacitor negative terminal. 4 PVSS Output from charge pump. 5, 13 NC No connection. 6 SVSS Amplifier negative supply, connect to PVSS. 7 OUT+ Positive output signal. 8 SVCC Amplifier positive supply, connect to PVCC. 9 OUT- Negative output signal. 10 FB Feed back. 11, 15 SDB Shutdown, active low logic. 12 IN Audio input signal. 14 SGND Signal ground, connect to ground. 16 PVCC Charge pump supply voltage, connect to positive supply. Thermal Pad Connect to GND. Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 2 IS31AP4915A ORDERING INFORMATION Industrial Range: -40C to +85C Order Part No. Package QTY/Reel IS31AP4915A-QFLS2-TR QFN-16, Lead-free 2500 Copyright (c) 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 3 IS31AP4915A ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA -0.3V ~ +7.0V -0.3V ~ VCC+0.3V 150C -65C ~ +150C -40C ~ +85C Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA=25C, VCC = 2.5V ~ 5.5V (unless otherwise noted). (Note 1) Symbol Parameter Condition Min. SVCC, PVCC Supply voltage VIH High level input voltage VIL Low level input voltage |VOS| 2.5 Supply current ISD Shutdown current Max. Unit 5.5 V 1.75 V 0.5 Output offset voltage ICC Typ. 6 V mV VCC = 3V, VSDB = VCC 6.0 8.0 VCC = 5V, VSDB = VCC 8.5 10.5 VSDB = 0V mA 1 A Max. Unit ELECTRICAL CHARACTERISTICS VCC = 3.6V, TA = 25C (unless otherwise noted). (Note 2) Symbol VOUT THD+N Parameter Output voltage Total harmonic distortion plus noise Condition f = 1kHz THD+N = 10% RL= 1F+10 Min. Typ. VCC = 5.0V 7.8 VCC = 3.6V 5.6 VCC = 2.7V 4.3 RL= 1F+10,VOUT = 1kHz/2VRMS 0.004 RL= 1F+10,VOUT = 1kHz/4VRMS 0.014 VRMS % VNO Noise output voltage 10 VRMS fOSC Charge pump switching frequency 320 kHz tON Start-up time from shutdown 450 s SNR Signal-to-noise ratio 100 dB TOVP Thermal shutdown threshold 160 C THY Thermal shutdown hysteresis 15 C Note 1: Production testing of the device is performed at 25C. Functional operation of the device and parameters specified over other temperature range, are guaranteed by design, characterization and process control. Note 2: Guaranteed by design. Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 4 IS31AP4915A TYPICAL OPERATING CHARACTERISTICS 20 VCC = 3.6V RL = 10+1H 5 1 THD+N(%) THD+N(%) 5 20 VCC = 2.7V RL = 10+1H 0.1 VOUT = 3.0Vrms 1 0.1 VOUT = 4.0Vrms 0.01 0.01 VOUT = 1.25Vrms 0.001 20 50 100 200 VOUT = 2.0Vrms 500 1k 2k 5k 0.001 20 10k 20k 50 100 200 Frequency(Hz) Figure 2 THD+N vs. Frequency 2k 5k THD+N vs. Frequency Figure 3 VCC = 5.0V RL = 10+1H RL = 10+1H f = 1kHz 5 1 1 0.1 VCC = 2.7V 0.1 VOUT = 6.0Vrms VCC = 5.0V 0.01 0.01 VCC = 3.6V VOUT = 3.0Vrms 0.001 20 0.001 50 100 200 500 1k 2k 5k 10k 20k 500m 1 2 3 Figure 4 THD+N vs. Frequency 5 6 7 8 Figure 5 THD+N vs. Output Voltage 70 8 7 Supply Current(mA) Supply Current(mA) 4 Output Voltage(V) Frequency(Hz) 6 5 4 VCC = 5V f = 1kHz 60 50 40 30 20 3 2 2.5 10k 20k 20 THD+N(%) THD+N(%) 1k Frequency(Hz) 20 5 500 10 0 3 3.5 4 4.5 5 5.5 0 1 Supply Current vs. Supply Voltage Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 3 4 5 6 7 Output Voltage(VRMS) Supply Voltage(V) Figure 6 2 Figure 7 Supply Current vs. Output Voltage 5 IS31AP4915A FUNCTIONAL BLOCK DIAGRAM C1N C1P SVSS SVCC PVCC Click-and-pop Suppression UVLO & SD Control IN Charge Pump PVSS OUTFB OUT+ SDB Bias SGND PGND Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 6 IS31AP4915A APPLICATION INFORMATION INPUT-BLOCKING CAPACITORS DECOUPLING CAPACITORS DC input-blocking capacitors are required to be added in series with the audio signal into the input pin of the IS31AP4915A. This capacitor block the DC portion of the audio source and allow the IS31AP4915A inputs to be properly biased to provide maximum performance. The IS31AP4915A require adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1F, placed as close as possible to the device VCC lead works best. Placing this decoupling capacitor close to the IS31AP4915A is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10F or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. These capacitors form a high-pass filter with the input impedance of the IS31AP4915A. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input impedance of the IS31AP4915A. Because the gains of both the IS31AP4915A is fixed, the input impedance remains a constant value. Using the input impedance value from the operating characteristics table, the frequency and/or capacitance can be determined when one of the two values is given. f CIN or CIN 1 2RIN C IN (1) 1 LAYOUT RECOMMENDATIONS The SGND and PGND pins of the IS31AP4915A must be routed separately back to the decoupling capacitor in order to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and THD performance do not meet the specifications. 2f CIN RIN CHARGE PUMP FLYING CAPACITOR AND PVSS CAPACITOR The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 10F is typical. Capacitor values that are smaller than 10F can be used, but the maximum output power is reduced and the device may not operate to specifications Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 7 IS31AP4915A CLASSIFICATION REFLOW PROFILES Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Pb-Free Assembly 150C 200C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3C/second max. Liquidous temperature (TL) 217C Time at liquidous (tL) 60-150 seconds Peak package body temperature (Tp)* Max 260C Time (tp)** within 5C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6C/second max. Time 25C to peak temperature 8 minutes max. Figure 8 Classification Profile Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 8 IS31AP4915A PACKAGE INFORMATION QFN-16 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. - www.issi.com Rev. B, 08/08/2013 9