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UT54ACS109E
Dual J-K Flip-Flops
Septenber 2010
www.aeroflex.com/Logic
FEATURES
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply of 3.0V to 5.5V
• Available QML Q or V processes
• 16-lead flatpack
DESCRIPTION
The UT54ACS109E is a dual J-K positive triggered flip-flop.
A low level at the preset or clear inputs sets or resets the outputs
regardless of the other input levels. When preset and clear are
inactive (high), data at the J and K input meeting the setup time
requirements are transferred to the outputs on the positive-going
edge of the clock pulse. Following the hold time interval, data
at the J and K input can be changed without affecting the levels
at the outputs. The flip-flops can perform as toggle flip-flops
by grounding K and tying J high. They also can perform as D
flip-flops if J and K are tied together.
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
FUNCTION TABLE
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for VOH if the lows at preset and clear are near VIL maximum.
In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.
PINOUTS 16-Lead Flatpack
Top View
LOGIC SYMBOL
INPUTS OUTPUT
PRE CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X H 1H 1
H H ↑L L L H
H H ↑H L Toggle
H H ↑L H No Change
H H ↑H H H L
H H L X X No Change
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J1
K1
CLK1
PRE1
Q1
VSS
Q1 89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
Q1
(6)
(7) Q1
Q2
(10)
(9) Q2
(5)
PRE1
(4)
CLK1
(1)
CLR1 (11)
PRE2 (14)
J2 (12)
CLK2 (13)
K2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
S
C1
R
(2)
J1 J1
(3)
K1 K1
(15)
CLR2
2
LOGIC DIAGRAM
OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
PRE
Q
CLR
Q
K
CLK
J
3
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD + .3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 3.0 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS109E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum dura tion of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
8. Power dissipation specified per switching output.
9. This value is guaranteed based on characterization data, but not tested.
SYMBOL Description CONDITION VDD MIN MAX UNIT
VIL Low-level input voltage 13.0V 0.9 V
5.5V 1.65
VIH High-level input voltage 13.0V 2.1 V
5.5V 3.85
IIN Input leakage current VIN = VDD or VSS 5.5V -1 1μA
VOL Low-level output voltage 3IOL = 100μA3.0V 0.25 V
4.5V 0.25
VOH High-level output voltage 3IOH = -100μA3.0V 2.75 V
4.5V 4.25
IOS Short-circuit output current 2 ,4 VO = VDD and VSS 3.0V -100 100 mA
5.5V -200 200
IOL Low level output current9VIN = VDD or VSS
VOL = 0.4V
3.0V 6mA
5.5V 8
IOH High level output current9VIN = VDD or VSS
VOH = VDD-0.4V
3.0V -6 mA
5.5V -8
Ptotal Power dissipatio n 2, 8 CL = 50pF 5.5V
3.0V
2.9
0.8 mW/
MHz
IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 μA
CIN Input capacitance 5ƒ = 1MHz 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz 0V 15 pF
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AC ELECTRICAL CHARACTERIST ICS FOR THE UT54 ACS109 E 2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)
SYMBOL PARAMETER VDD MINIMUM MAXIMUM UNIT
tPLH1 CLK to Q, Q CL = 30pF 3.0V & 3.6V 423 ns
4.5V & 5.5V 419
CL = 50pF 3.0V & 3.6V 427 ns
4.5V & 5.5V 423
tPHL1 CLK to Q, Q CL = 30pF 3.0V & 3.6V 527 ns
4.5V & 5.5V 523
CL = 50pF 3.0V & 3.6V 531 ns
4.5V & 5.5V 527
tPLH2 PRE to Q CL = 30pF 3.0V & 3.6V 116 ns
4.5V & 5.5V 112
CL = 50pF 3.0V & 3.6V 120 ns
4.5V & 5.5V 116
tPHL2 PRE to Q CL = 30pF 3.0V & 3.6V 119 ns
4.5V & 5.5V 115
CL = 50pF 3.0V & 3.6V 123 ns
4.5V & 5.5V 119
tPLH3 CLR to Q CL = 30pF 3.0V & 3.6V 216 ns
4.5V & 5.5V 212
CL = 50pF 3.0V & 3.6V 220 ns
4.5V & 5.5V 216
tPHL3 CLR to Q CL = 30pF 3.0V & 3.6V 219 ns
4.5V & 5.5V 215
CL = 50pF 3.0V & 3.6V 223 ns
4.5V & 5.5V 219
fMAX4 Maximum clock frequency CL = 50pF 3.0V, 4.5V, and
5.5V 62 MHz
tSU1 PRE or CLR inactive setup time
before CLK↑CL = 50pF 3.0V, 4.5V, and
5.5V 5 ns
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Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
4. Historically maximum frequency "fMAX" was based off minimum pulse width (tW), fMAX = 1/2tW. In practice, the achievable fMAX is dictated by the CLK to Q
propagation delays listed in the AC electrical table. For a more complete description on calculating the applicable fMAX reference, the application note titled
“Frequency vs Load Capacitance for the MSI Product Family" is located at www.aeroflex.com/
tSU2 Data setup time before CLK ↑ CL = 50pF 3.0V, 4.5V, and
5.5V 5ns
tH3Data hold time after CLK ↑ CL = 50pF 3.0V, 4.5V, and
5.5V 3ns
tWMinimum pulse width
PRE or CLR low
CLK high
CLK low
CL = 50pF 3.0V, 4.5V, and
5.5V 8ns
Packaging
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Ordering Information UT54ACS109E
I/O Type:
ACS = CMOS compatible I/O level
Part Number:
109E = Dual J-K Flip-Flops
Package Type:
U = 16-lead ceramic bottom-brazed dual-in-line Flatpack
Screening: (Note 3)
C = HiRel Temperature Range (-55
o
C to +125
o
C)
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
UT54 *** ****
-
***
Notes:
1. Lead finish (A, C, or X) must be spe cified.
2. If an "X" is specified when ordering, then the part m a rking will match the lead finish and will be either "A" (solde r) or "C" (gold).
3. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices have 48 hours of burn-in and are test at -55
o
C,
room temperatur e, and 125
o
C. Radiation characterisitics are neither tested nor guaranteed and may not be specified.
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UT54ACS109E: SMD
Drawing Number:
96540 = UT54ACS109E
Device Type:
02 = 1 rad(Si)/sec
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
5962 ***** ** * * **
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
03 = 50 to 300 rads(Si)/sec
Class Designator:
Q = QML Class Q
V = QML Class V
Notes:
1. Lead fini sh (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For protot ype inquiries, contact
factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID toler a nce guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
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