PI74SSTU32864NBE - Pericom Semiconductor

1PS8636B 07/26/04

Features

• PI74 SSTU32864 is designed for low-voltage operation,

VDD = 1.8V

• Supports Low Power Standby Operation

• All Inputs are SSTL_18 Compatible, except RST, C0, C1,

which are LVCMOS.

• Output drivers are optimized to drive DDR-II DIMM loads

• Designed for DDR Memory

• Packaging (Pb-free & Green available):

-96 Ball LFBGA (NB)

Block Diagram 1:2 Mode (Positive Logic)

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2 Congurable

Registered Buffer

TO OTHER CHANNELS

RST

QCKEA

QCKEB*

QODTA

Q1A

Q1B*

QCSB*

QCSA

QODTB*

VREF

DCKE

DODT

DCS

CSR

Note: Disabled in 1:1 configuration

Description

Pericom Semiconductor’s PI74SSTU32864 logic circuit is produced

using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2

congurable registered buffer is designed for 1.7V to 1.9V VDD

operation.

All clock and data inputs are compatible with the JEDEC standard

for SSTL_18. The control inputs are LVCMOS. All outputs are

1.8V LVCMOS drivers that have been optimized to drive the

DDR-II DIMM load.

The SSTU32864 operates from a differential clock (CK and CK).

Data is registered at the crossing of CK going high, and CK going

low.

The C0 input controls the pinout conguration of the 1:2 pinout

from A conguration (when LOW) to B conguration (when

HIGH). The C1 input controls the pinout conguration for 25-Bit

1:1 (when LOW) to 14-Bit 1:2 (when HIGH).

The device supports low-power standby operation. When the reset

input (RST) is low, the differential input receivers are disabled and

undriven (oating) data, clock and reference voltage (VREF) inputs

are allowed. In addition , when RST is low, all registers are reset,

and all outputs are forced low. The LVCMOS RST and Cn inputs

must always be held at a valid logic high or low level.

To ensure dened outputs from the register before a stable clock has

been supplied, RST must be held in the low state during power up.

In the DDR-II RDIMM application, RST is specied to be completely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

reset, the register will be cleared and the outputs will be driven

low quickly, relative to the time to disable the differential input

receivers. However, when coming out of reset, the register will

become active quickly, relative to the time to enable the differential

input receivers.

As long as the data inputs are low, and the clock is stable during

the time from the low-to-high transition of RST until the input

receivers are fully enabled, the design of the SSTU32864 must

ensure that the outputs remain low, thus ensuring no glitches on

the output.

The device monitors both DCS and CSR inputs and will gate the

Qn outputs from changing states when both DCS and CSR inputs

are high. If either DCS or CSR input is low, the Qn outputs will

function normally. The RST input has priority over the DCS and CSR

control will force the outputs low. If the DCS control functionality

is not desired, then the CSR input can be hardwired to ground,

in which case, the set-up time requirement for DCS would be the

same as for the other D data inputs.

2PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Pin Conguration 1:2 Register (C0 = 0, C1 = 1)

1 2 3 4 5 6

ADCKE NC VREF VDD QCKEA QCKEB

BD2 NC GND GND Q2A Q2B

CD3 NC VDD VDD Q3A QODTB

DDODT NC GND GND QODTA Q4B

ED5 NC VDD VDD Q5A Q5B

FD6 NC GND GND Q6A Q6B

GNC RST VDD VDD C1 C0

HCK DCS GND GND QCSA QCSB

JCK CSR VDD VDD ZOH ZOL

KD8 NC GND GND Q8A Q8B

LD9 NC VDD VDD Q9A Q9B

MD10 NC GND GND Q10A Q10B

ND11 NC VDD VDD Q11A Q11B

PD12 NC GND GND Q12A Q12B

RD13 NC VDD VDD Q13A Q13B

TD14 NC VREF VDD Q14A Q14B

Pin Conguration 1:1 Register (C0 = 0, C1 = 0)

1 2 3 4 5 6

ADCKE NC VREF VDD QCKE NC

BD2 D15 GND GND Q2 Q15

CD3 D16 VDD VDD Q3 Q15

DDODT NC GND GND QODT NC

ED5 D17 VDD VDD Q5 Q17

FD6 D18 GND GND Q6 Q18

GNC RST VDD VDD C1 C0

HCK DCS GND GND QCS NC

JCK CSR VDD VDD ZOH ZOL

KD8 D19 GND GND Q8 Q19

LD9 D20 VDD VDD Q9 Q20

MD10 D21 GND GND Q10 Q21

ND11 D22 VDD VDD Q11 Q22

PD12 D23 GND GND Q12 Q23

RD13 D24 VDD VDD Q13 Q24

TD14 D25 VREF VDD Q14 Q25

3PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Pin Conguration 1:2 Register (C0 = 1, C1 = 1)

1 2 3 4 5 6

AD1 NC VREF VDD Q1A QB

BD2 NC GND GND Q2A Q2B

CD3 NC VDD VDD Q3A Q3B

DD4 NC GND GND Q4A Q4B

ED5 NC VDD VDD Q5A Q5B

FD6 NC GND GND Q6A Q6B

GNC RST VDD VDD C1 C0

HCK DCS GND GND QCSA QCSB

JCK CSR VDD VDD ZOH ZOL

KD8 NC GND GND Q8A Q8B

LD9 NC VDD VDD Q9A Q9B

MD10 NC GND GND Q10A Q10B

NDODT NC VDD VDD QODTA QODTB

PD12 NC GND GND Q12A Q12B

RD13 NC VDD VDD Q13A Q13B

TDCKE NC VREF VDD QCKEA QCKEB

NB 96-ball LFBGA (MO-205CC) Top View

4PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Terminal Functions

Name Description Characteristics

GND Ground Ground Input

VDD Power Supply 1.8V nominal

VREF Input Reference Voltage 0.9V nominal

ZOH Reserved for future use Input

ZOL Reserved for future use Input

CK Positive master clock input Differential Clock input

CK Negative master clock input Differential Clock input

C0, C1 Conguration control inputs LVCMOS inputs

RST Asynchronous reset input - resets registers and disables VREF data and clock differen-

tial - input receivers LVCMOS inputs

CSR, DCS Chip select inputs disables D1-D24 outputs switching when both inputs are high SSTL_18 input

D1, D25 Data input - clocked in on the crossing of the rising edge of CK and the falling edge

of CK SSTL_18 input

DODT The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input

DCKE The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input

Q1-Q25 Data outputs that are suspended by the DCS and CSR control 1.8V CMOS

QCS Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS

QODT Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS

QCKE Data output that will not be suspended by the DCS and CSR controll 1.8V CMOS

Function Table (each ip op)

Inputs Outputs

RST DCS CSR CK CK Dn, DODT,

DCKE Qn QCS QODT,

QCKE

H L L ↑ ↓ L L L L

H L L ↑ ↓ H H L H

H L L L or H L or H X Q0 Q0 Q0

H L H ↑ ↓ L L L L

H L H ↑ ↓ H H L H

H L H L or H L or H X Q0 Q0 Q0

H H L ↑ ↓ L L H L

H H L ↑ ↓ H H H H

H H L L or H L or H X Q0 Q0 Q0

H H H ↑ ↓ L Q0 H L

H H H ↑ ↓ H Q0 H H

H H H L or H L or H X Q0 Q0 Q0

L X or oating X or oating X or oating X or oating X or oating L L L

5PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Notes:

1. The RST and Cn inputs of the device must be held at valid levels (not oating) to ensure proper device operation. The differential inputs must

not be oating, unless RST is low.

Notes:

1. Stresses greater than those listed under MAXIMUM

RAINGS may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions above those indi-

cated in the operational sections of this specication is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be ex-

ceeded if the input and output clamp-current ratings are

observed.

3. This value is limited to 2.5V maximum

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ................................................... –65°C to +150°C

Supply Voltage Range, VDD .............................................–0.5V to 2.5V

Input Voltage Range,VI : (See Notes 2 and 3): ................–0.5V to 2.5V

Output Voltage Range, VO (See Notes 2 and 3).... –0.5V to VDD + 0.5V

Input Clamp current, IIK (VI < 0 or VI = VDD ) ......................... –50mA

Output Clamp current, IOK (VO < 0 or VO > VDD).................... ±50mA

Continous Output Current, IO (VO = 0 to VDD) ........................ ±50mA

Continous Current through each VDD or GND......................... ±100mA

Recommended Operating Conditions(1)

Parameters Descrition Min. Nom. Max. Units

VDD Supply Voltage 1.7 1.9

VREF Reference Voltage 0.49 x VDD 0.50 x VDD 0.51 x VDD

VTT Termination Voltage VREF -40mA VREF VREF -40mA

VIInput Voltage 0 VDD

VIH AC High - Level Input Voltage

Data

Inputs

VREF 250mV

VIL AC Low- Level Input Voltage VREF -250mV

VIH DC High - Level Input Voltage VREF 125mV

VIL DC Low- Level Input Voltage VREF -125mV

VIH High Level Input Voltage RST, CN 0.65 x VDD

VIL Low Level Input Voltage 0.35 x VDD

VICR Common-mode input Voltage CK, CK 0.675 1.125

VID Differential Input Voltage 600 mV

IOH High-Level Output Current -8 mA

IOL Low-Level Output Current -8

TAOperating Free-air Temperature 0 70 ºC

6PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Notes

1. This parameter is not necessarily production tested.

2. Data and VREF inputs must be a low minimum time of tact max, after RST is taken high.

3. Data and clock inputs must be held at valid levels (not oating) a minimum time of tinact max after RST is taken low.

Timing Requirements Over Recommended Operating Free Air Temperature range (See Figure 1)

Parameter Description Min. Max Units

fclock Clock frequency 270 MHz

tWPulse Duration, CK, CK, High or low 1

tact(1) Differential inputs active time(1) 10

tinact(1) Differential inputs inactive time(2) 15

tsu Setup time

DCS before CK↑, CK↓, CSR high 0.7

DCS before CK↑, CK↓, CSR low 0.5

CSR DODT, CKE anddata before CK↑, CK↓ 0.5

th Hold Time DCS, CSR DODT, CKE adn data before CK↑, CK↓ 0.5

Notes:

1. The vendor must supply this value for full device description.

Electrical Characteristics Over Recommended Operating Free Air Temperature range

Parameters Description Test Conditions VDD Min. Nom. Max. Units

VOH IOH = -6 mA 1.7V 1.2 V

VOL IOL = 6 mA 1.7V 0.5

IIAll inputs VI = VDD or GND ±5

µA

IDD

Static Stand-by RST = GND

IO = 0

1.9V 100

Static Operating RST = VDD, VI = VIH(AC) or VIL(AC) 40 mA

IDDD

Dynamic Operating

Clock only

RST = VDD, VI = VIH(AC), or

VIL(AC) CK and CK switching 50%

duty cycle

1.8V

µA/

clock

MHz

Dynamic Operating - per

each data input, 1:1 mode

RST = VDD, VI = VIH(AC), or

VIL(AC) CK and CK switching 50%

duty cycle. One data input switch-

ing at half clock frequency, 50%

duty cycle

18 µA/

clock

MHz

data

input

Dynamic Operating - per

each data input, 1:2 mode

RST = VDD, VI = VIH(AC), or

VIL(AC) CK and CK switching 50%

duty cycle. One data input switch-

ing at half clock frequency, 50%

duty cycle

Data inputsp VI = VREF ±250mV 2.5 3.5

CK and CK VICR = 0.9V, VID = 600mV 2 3

RST VI = VDD or GND 2.5

7PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Notes:

1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

Output Edge Rates Over Recommended Operating Free Air Temperature range (See Figure 2)

Parameters VDD = 1.8V ± 0.1V Units

Min. Max.

dV/dt_r 1 4

V/nsdV/dt_f 1 4

dV/dt(1) 1

Note:

1. Includes 350ps test load transmission-line delay.

2. This parameter is not necessarily production tested.

3. For reference only. Final values to be determined.

Switching Characteristics Over Recommended Operating Free Air Temperature range (See Figure 1)

Parameters From

(Input)

(Output)

VDD = 1.8V ± 0.1V Units

Min. Max.

fmax 270 MHz

tpdm CK and CK Q 1.41(3) 2.15(3)

tpdmss

(simultaneous switching)(1, 2) CK and CK Q 2.35(3)

tRPHL RST Q 0 3

8PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Voltage and Current Waveforms

Input Active and Inactive Times

Voltage Waveforms - Pulse Duration

Voltage Waveforms - Setup and Hold Times

Test Circuit and Switching Waveforms

Figure 1. Parameter Measurement Information (VDD = 1.8V ± 0.1V)

Load Circuit

Voltage Waveforms - Propagation Delay Times

Output

VICR

tPLH tPHL

VICR VID

VOH

VTT

VOL

LVCMOS

RST

Input

DD(2)

VDD

VDD/2

tinact

10%

90%

tact

VDD/2

LVCMOS

RESET

Input

Output

tRPHL

VDD/2

VOH

VIH

VIL

VTT

VOL

Input

VICR VICR

VID

Input

tsu

VIL

VICR

VREF

VID

VIH

TL= 350ps, 50-ohm

R = 1000-ohm�

VDD

CL= 30pF

(see note 1)

DUT

RL= 100-ohm

Test Point

CK Inputs

TL= 50-ohm

R = 1000-ohm�

Out

Notes:

1. CL includes probe and jig capacitance

2. IDD tested with clock and data inputs held at VDD or GND and IO = 0mA

3. All input pulses are supplied by generators having the following characteristics: Pulse Repertition Rate ≥ 10 MHz, ZO = 50Ω, input slew

rate = 1V/ns ± 20% (unless otherwise specied).

4. The outputs are measured one at a time with one transition per measurement.

5. VREF = VDD /2

6. VIH = VREF +250mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.

7. VIL = VREF -250mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.

8. VID = 600mV

9. tPLH and tPHL are the same as tpdm.

9PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

R = 50-ohm�

VDD

CL= 10pF

(see note 1)

DUT

Test Point

Out

Output

80%

20%

dt_f

VOL

VOH

dv_f

RL = 50-ohm�

CL= 10pF

(see note 1)

DUT

Test Point

Out

Output

80%

20%

VOL

VOH

dv_r

Load Circuit -High -to- Low Slew Rate Measurement

Load Circuit - Low -to- High Slew Rate Measurement

Voltage Waveforms - High -to- Low Slew Rate Measurement

Voltage Waveforms - Low -to- High Slew Rate Measurement

Figure 2. Output Slew-Rate Measurement Information (VDD = 1.8V ± 0.1V)

Notes:

1. CL includes probe and jig capacitance

2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, input slew rate = 1 V/ns ± 20%

(unless otherwise specied).

10 PS8636B 07/26/04

PI74SSTU32864

25-Bit 1:1 or 14-Bit 1:2

Congurable Buffer

Packaging Mechanical: 96-ball LFBGA (NB)

Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

Ordering Information

Notes:

1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

2. Number of Transistors = TBD

Ordering Code Package Code Package Type

PI74SSTU32864NB NB 96-Ball LFBGA

PI74SSTU32864NBE NB Pb-free & Green, 96-Ball LFBGA