X28HC64P12 - INTERSIL - Product.Network

FN8109.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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X28HC64

64K, 8K x 8 Bit

5 Volt, Byte Alterable EEPROM

FEATURES

• 70ns access time

• Simple byte and page write

—Single 5V supply

—No external high voltages or VPP control circuits

—Self-timed

—No erase before write

—No complex programming algorithms

—No overerase problem

• Low power CMOS

—40mA active current max.

—200µA standby current max.

• Fast write cy c le ti mes

—64-byte page write operation

—Byte or page write cycle: 2ms typical

—Complete memory rewrite: 0.25 sec. typical

—Effectiv e by te wr it e cy cl e time: 32µs typical

• Software data protection

• End of write detection

—DATA polling

—Toggle bit

• High reliability

—Endurance: 1 million cycles

—Data retention: 100 years

• JEDEC approved byte-wide pin out

• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X28HC64 is an 8K x 8 EEPROM, fabricated with

Intersil’s proprietary, high performance, floating gate

CMOS technology. Like all Intersil programmable non-

volatile memories, the X28HC64 is a 5V only device. It

features the JEDEC approved pinout for byte-wide

memories, compatible with industry standard RAMs.

The X28HC64 supports a 64-byte page write operation,

effectively providing a 32µs/byte write cycle, and

enabling the entire memo ry to be typica lly written in 0 . 25

seconds. The X28HC64 also features DATA Polling and

Toggle Bit Polling, two methods providing early end of

write detection. In addition, the X28HC64 includes a

user-optional software data protection mode that further

enhances Intersil’s hardware write protect capability.

Intersil EEPROMs are designed and tested for appli-

cations requiring extended endurance. Inherent data

retention is greater than 10 0 years.

PIN CONFIGURATIONS

A12

I/O0

I/O1

I/O2

VSS

VCC

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

X28HC64

Plastic DIP

Flat Pack

CERDIP

SOIC

I/O0

A11

A10

I/O7

I/O6

4 3 2 1 32 31 30

14 15 16 17 18 19 20

LCC

PLCC

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

(Top View)

A12

VCC

A11

I/O0

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

I/O7

A10

A12

VCC

X28HC64

I/O0 10

A0 14

VSS

A1 8

A3 6

A5 2

A12

VCC

I/O1 13

I/O2 15

I/O3

A6 3

A71

I/O4

I/O5

I/O7

A10

A11

I/O6

(BOTTOM

VIEW)

PGA

X28HC64

TSOP

Bottom View

Data Sheet June 7, 2006

2FN8109.1

June 7, 2006

Ordering Information

PART NUMBER PART MARKING TEMPERATURE

RANGE (°C) ACCESS TIME

(ns) PACKAGE PKG. DWG. #

X28HC64EM-70 X28HC64EM-70 -55 to 125 70 32 Ld LCC (458 mil)

X28HC64J-70* X28HC64J-70 0 to 70 32 Ld PLCC N32.45x55

X28HC64JI-70* X28HC64JI-70 -40 to 85 32 Ld PLCC N32.45x55

X28HC64JIZ-70* (Note) X28HC64JI-70 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55

X28HC64JZ-70* (Note) X28HC64J-70 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55

X28HC64KM-70 X28HC64KM-70 -55 to 125 28 Ld PGA G28.550x650A

X28HC64P-70 X28HC64P-70 0 to 70 28 Ld PDIP E28.6

X28HC64PZ-70 (Note) X28HC64P-70 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6

X28HC64S-70* X28HC64S-70 0 to 70 28 Ld SOIC (300 mil) M28.3

X28HC64SI-70* X28HC64SI-70 -40 to 85 28 Ld SOIC (300 mil) M28.3

X28HC64SM-70* X28HC64SM-70 -55 to 125 28 Ld SOIC (300 mil) M28.3

X28HC64SZ-70 (Note) X28HC64S-70 Z 0 to 70 28 Ld SOIC (300 mil) (Pb-free) M28.3

X28HC64J-90* X28HC64J-90 0 to 70 90 32 Ld PLCC N32.45x55

X28HC64JI-90* X28HC64JI-90 -40 to 85 32 Ld PLCC N32.45x55

X28HC64JIZ-90* (Note) X28HC64JI-90 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55

X28HC64KM-90 X28HC64KM-90 -55 to 125 28 Ld PGA G28.550x650A

X28HC64KMB-90 C X28HC64KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A

X28HC64P-90 X28HC64P-90 0 to 70 28 Ld PDIP E28.6

X28HC64PI-90 X28HC64PI-90 -40 to 85 28 Ld PDIP E28.6

X28HC64PIZ-90 (Note) X28HC64PI-90 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6

X28HC64PZ-90 (Note) X28HC64P-90 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6

X28HC64S-90* X28HC64S-90 0 to 70 28 Ld SOIC (300 mil) M28.3

X28HC64

3FN8109.1

June 7, 2006

X28HC64D-12 X28HC64D-12 0 to 70 120 28 Ld CERDIP

X28HC64DI-12 X28HC64DI-12 -40 to 85 28 Ld CERDIP

X28HC64DM-12 X28HC64DM-12 -55 to 125 28 Ld CERDIP

X28HC64DMB-12 C X28HC64DMB-12 MIL-STD-883 28 Ld CERDIP

X28HC64FM-12 X28HC64FM-12 -55 to 125 28 Ld FLATPACK (440 mil)

X28HC64J-12* X28HC64J-12 0 to 70 32 Ld PLCC N32.45x55

X28HC64JI-12* X28HC64JI-12 -40 to 85 32 Ld PLCC N32.45x55

X28HC64JIZ-12* (Note) X28HC64JI-12 Z -40 to 85 32 Ld PLCC (Pb-free) N32.45x55

X28HC64JZ-12* (Note) X28HC64J-12 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55

X28HC64KMB-12 C X28HC64KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A

X28HC64P-12 X28HC64P-12 0 to 70 28 Ld PDIP E28.6

X28HC64PI-12 X28HC64PI-12 -40 to 85 28 Ld PDIP E28.6

X28HC64PIZ-12 (Note) X28HC64PI-12 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6

X28HC64PZ-12 (Note) X28HC64P-12 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6

X28HC64S-12* X28HC64S-12 0 to 70 28 Ld SOIC (300 mil) M28.3

X28HC64SI-12* X28HC64SI-12 -40 to 85 28 Ld SOIC (300 mil) M28.3

X28HC64SIZ-12* (Note) X28HC64SI-12 Z -40 to 85 28 Ld SOIC (300 mil) (Pb-free) M28.3

X28HC64SZ-12 (Note) X28HC64S-12 Z 0 to 70 28 Ld SOIC (300 mil) (Pb-free) M28.3

X28HC64DM-15 X28HC64DM-15 -55 to 125 150 28 Ld CERDIP

X28HC64J-15T1 X28HC64J-15 0 to 70 32 Ld PLCC Tape and Reel N32.45x55

X28HC64JI-15 X28HC64JI-15 -40 to 85 32 Ld PLCC N32.45x55

X28HC64JM-15 X28HC64JM-15 -55 to 125 32 Ld PLCC N32.45x55

X28HC64JZ-15* (Note) X28HC64J-15 Z 0 to 70 32 Ld PLCC (Pb-free) N32.45x55

X28HC64KMB-15 C X28HC64KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A

X28HC64P-15 X28HC64P-15 0 to 70 28 Ld PDIP E28.6

X28HC64PIZ-15 (Note) X28HC64PI-15 Z -40 to 85 28 Ld PDIP** (Pb-free) E28.6

X28HC64PZ-15 (Note) X28HC64P-15 Z 0 to 70 28 Ld PDIP** (Pb-free) E28.6

X28HC64S-15 X28HC64S-15 0 to 70 28 Ld SOIC (300 mil) M28.3

X28HC64SI-15 X28HC64SI-15 -40 to 85 28 Ld SOIC (300 mil) M28.3

*Add "T1" suffix for tape and reel.

**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Ordering Information (Continued)

PART NUMBER PART MARKING TEMPERATURE

RANGE (°C) ACCESS TIME

(ns) PACKAGE PKG. DWG. #

X28HC64

4FN8109.1

June 7, 2006

PIN DESCRIPTIONS

Addresses (A0-A12)

The Address inputs select an 8-bit memory location

during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all

read/write operations. When CE is HIGH, power con-

sumption is reduced.

Output Enable (OE)

The Output Enable input controls the data output bu ff-

ers and is used to in itiate read o perations.

Data In/Data Out (I/O0-I/O7)

Data is written to or read from the X28HC64 through

the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to

the X28HC64.

PIN NAMES

BLOCK DIAGRAM

Symbol Description

A0-A12 Address Inputs

I/O0-I/O7Data Input/Output

WE Write Enable

CE Chip Enable

OE Output Enable

VCC +5V

VSS Ground

NC No Connect

X Buffers

Latches and

Decoder

I/O Buffers

and Latches

Y Buffers

Latches

Decoder

Control

Logic and

Timing

65,536-Bit

EEPROM

Array

I/O0–I/O7

Data Inputs/Outputs

VCC

VSS

A0–A12

Address

Inputs

and

X28HC64

5FN8109.1

June 7, 2006

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE

LOW. The read operation is terminated by either CE or

OE returning HIGH. This two line control architecture

eliminates bus contention in a system environment.

The data bus will be in a high impedance state when

either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE

are LOW and OE is HIGH. The X28HC64 supports

both a CE and WE controlled write cycle. That is, the

address is latched by the falling edge of either CE or

WE, whichever occurs last. Similarly, the data is

latched internally by the rising edge of either CE or

WE, whichever occurs first. A byte write operation,

once initiated, will automatically continue to comple-

tion, typically within 2ms.

Page Write Operation

The page write feature of the X28HC64 allows the

entire memory to be written in 0.25 seconds. Page write

allows two to sixty-four bytes of data to be consecutively

written to the X28HC64 prior to the commencement of

the internal programming cycle. The host can fetch dat a

from another device within the system during a page

write operation (change the source address), but the

page address (A6 through A12) for each subsequent

valid write cycle to the part during this operation must

be the same as the initial page address.

The page write mode can be initiated during any write

operation. Following the initial byte write cycle, the

host can write an additional one to sixty-three bytes in

the same manner. Each successive byte load cycle,

started by the WE HIGH to LOW tran sition, must begin

within 100µs of the falling edge of the preceding WE. If

a subsequent WE HIGH to LOW transition is not

detected within 100µs, the inter nal automatic program-

ming cycle will commence. There is no page write win-

dow limitation. Effectively the page write window is

infinitely wide, so long as th e host continu es to acces s

the device within the b yte load cycle time of 100µs.

Write Operation Status Bits

The X28HC64 provides the user two write operation

status bits. These can be used to optimize a system

write cycle time. The status bits are mapped onto the

I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

DATA Polling (I/O7)

The X28HC64 features DATA Polling as a method to

indicate to the host system that the byte write or page

write cycle has completed. DATA Polling allows a sim-

ple bit test operation to determine the status of the

X28HC64, eliminating additional interrupt inputs or

external hardware. During the internal programming

cycle, any attempt to read the last byte writte n will pro-

duce the complement of that data on I/O7 (i.e. write

data = 0xxx xxxx, read data = 1xxx xxxx). Once the

programming cycle is complete, I/O7 will reflect true dat a.

Toggle Bit (I/O6)

The X28HC64 also p rovides anothe r method for dete r-

mining when the internal write cycle is complete. Dur-

ing the internal programming cycle I/O6 will toggle

from HIGH to LOW and LOW to HIGH on subsequent

attempts to read the device. When the internal cycle is

complete the toggling will cease and the device will be

accessible for additiona l read or write operations.

5TBDP 43210I/O

Reserved

Toggle Bit

DATA Polling

X28HC64

6FN8109.1

June 7, 2006

DATA POLLING I/O7

Figure 2. DATA Polling Bus Sequence

Figure 3. DATA Polling Software Flow DATA Polling can effectively reduce the time for writing

to the X28HC64. The timing diagram in Figure 2 illus-

trates the sequence of events on the bus. The soft-

ware flow diagram in Figure 3 illustrates one method

of implementing the routine.

I/O7X28HC64

Ready

Last

Write

HIGH Z VOL

VIH

A0–A12 An An An An An An

VOH

Write Data

Save Last Data

and Address

Read Last

Address

IO7

Compare? No

Yes

Writes

Complete? No

Yes

Ready

X28HC64

7FN8109.1

June 7, 2006

THE TOGGLE BIT I/O6

Figure 4. Toggle Bit Bus Sequence

Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the chore of saving and

fetching the last address and data in order to implement

DATA Polling. This can be especially helpful in an array

comprised of multiple X28HC64 memories that is fre-

quently upd ated. Tog gle Bit Polling can also provide a

method for status checking in multiprocessor applica-

tions. The timing diagram in Figure 4 illustrates the

sequence of events on the bus. The software flow dia-

gram in Figure 5 illustrates a method for polling the

Toggle Bit.

X28HC64

Last

Write

I/O6HIGH Z

VOH VOL Ready

* Beginning and ending state of I/O6 will vary.

Compare No

Yes

Ok?

Compare

Accum with

Addr N

Load Accum

From Addr N

Last Write

Ready

Yes

X28HC64

8FN8109.1

June 7, 2006

HARDWARE DATA PROTECTION

The X28HC64 provides two hardware features that

protect nonvolatile data from inadvertent writes.

– Default V CC Sense—All write function s a re i nhibi te d

when VCC is 3V typically.

– W rite In hibit—Holding either OE LOW, WE HIGH, or

CE HIGH will prevent an inadvertent write cycle dur-

ing power-up and power-down, ma intaining data

integrity.

SOFTWARE DATA PROTECTION

The X28HC64 offers a software controlled data protec-

tion feature. The X2 8HC64 is shipped from Inte rsil with

the software data protection NOT ENABLED; that is,

the device will be in the standard operating mode. In

this mode data should be protected during power-up/-

down operations through the use of external circuits.

The host would then have open read and write access

of the device once VCC was stable.

The X28HC64 can be automatically protected during

power-up and power-down without the need for exter-

nal circuits by employing the software data protection

feature. The inte rnal software data protection circuit is

enabled after the first write operation utilizing the soft-

ware algorithm. This circuit is nonvolatile and will

remain set for the life of the device, unless the reset

command is issued.

Once the soft ware protection is enabled, the X28 HC64

is also protected from inadvertent and accidental

writes in the powered-up state. That is, the software

algorithm must be issued prior to writing additional

data to the device.

SOFTWARE ALGORITHM

Selecting the software data protection mode requires

the host system to precede data write operations by a

series of three write operations to three specific

addresses. Refer to Figure 6 and 7 for the sequence.

The three-byte sequence opens the page write window,

enabling the host to write from one to sixty-four bytes

of data. Once the page load cycle has been com-

pleted, the device will automatically be returned to the

data pro tected state.

X28HC64

9FN8109.1

June 7, 2006

SOFTWARE DATA PROTECTION

Figure 6. Timing Sequence—Byte or Page Write

Figure 7. Write Sequence for Software

Data Protection Regardless of whet her the de vice has previou sly be e n

protected or not, once the software data protection

algorithm is used, the X28HC64 will automatically dis-

able further writes unless another command is issued

to deactivate it. If no further commands are issued the

X28HC64 will be write protected during power-down

and after an y subsequent power- up.

Note: Once initiated, the se quence of write operations

should not be interrup ted.

(VCC)

Write

Protected

VCC

Data

ADDR AAA

1555 55

0AAA A0

1555

≤tBLC MAX

Writes

Byte

Page

tWC

Write Last

Write Data XX

to Any

Write Data A0

to Address

1555

Write Data 55

to Address

0AAA

Write Data AA

to Address

1555

After tWC

Re-Enters Data

Protected State

Byte to

Last Address

Address Optional

Byte/Page

Load Operation

Byte/Page

Load Enabled

X28HC64

10 FN8109.1

June 7, 2006

RESETTING SOFTWARE DATA PROTECTION

Figure 8. Reset Softwa re Data Protection Timing Sequence

Figure 9. Software Sequence to Deactivate Software

Data Protection In the event the user wants to deactivate the software

data protection feature for testing or reprogramming in

an EEPROM programmer, the following six step algo-

rithm will reset the internal protection circuit. After tWC,

the X28HC64 will be in standard operating mode.

Note: Once initiated, the sequence of write operations

should not be interrup ted.

Standard

Operating

Mode

VCC

Data

ADDR AAA

1555 55

0AAA 80

1555 ≥tWC

1555 55

0AAA 20

1555

Write Data 55

to Address

0AAA

Write Data 55

to Address

0AAA

Write Data 80

to Address

1555

Write Data AA

Address

1555

Write Data 20

to Address

1555

Write Data AA

to Address

1555

X28HC64

11 FN8109.1

June 7, 2006

SYSTEM CONSIDERATIONS

Because the X28HC64 is frequently used in large

memory arrays, it is provided with a two-line control

architecture for both read and write operations. Proper

usage can provide the lowest possible power dissipa-

tion, and eliminate the possibility of contention where

multiple I/O pins share the same bus.

To gain the most benefit, it is recommended that CE

be decoded from the address bus, and be used as the

primary device selection input. Both OE and WE would

then be common among all devices in the array. For a

read operation, this assures that all deselected

devices are in their standby mode, and that only the

selected device(s) is/a re outputtin g data on the bus.

Because the X28HC64 has two power modes,

standby and active, proper decoupling of the memory

array is of prime concern. Enabling CE will cause tran-

sient current spikes. The magnitude of these spikes is

dependent on th e output capa citive loading of the I/Os.

Therefore, the larger the array sharing a common bus,

the larger the transient spikes. The voltage peaks

associated with the current transients can be sup-

pressed by the proper selection and placement of

decoupling capacitors. As a minimum, it is recom-

mended that a 0.1µF high frequency ce ramic capacitor

be used between VCC and VSS at each device.

Depending on the size of the array, the value of the

capacitor may have to be large r.

In addition, it is recommended that a 4.7µF electrolytic

bulk capacitor be placed between VCC and VSS for

each eight devices employed in the array. This bulk

capacitor is employed to overcome the voltage droop

caused by the inductive effects of the PC board traces.

Normalized ICC(RD) by Temperature

Over Frequency Normalized ICC(RD) @ 25% Over

the VCC Range and Frequency

1.4

1.2

0.8

0.4

0.6

0.2

1.0

01020

- 55°C

+ 25°C

Frequency (MHz)

+ 125°C

5.5 VCC

ICCRD

Normalized (mA)

1.4

1.2

0.8

0.4

0.6

0.2

1.0

01020

Frequency (MHz)

4.5 VCC

5.0 VCC

5.5 VCC

ICCRD

Normalized (mA)

X28HC64

12 FN8109.1

June 7, 2006

ABSOLUTE MAXIMUM RATINGS

Temperature und er bias

X28HC64 .........................................-10°C to +85°C

X28HC64I, X28HC64M..................-65°C to +135°C

S torage temperature..........................-65°C to +150°C

Voltage on any pin with

respect to VSS ......................................... -1V to +7V

D.C. output current...............................................5mA

Lead temperatur e

(soldering, 10 seconds).................................. 300°C

COMMENT

Stresses ab ove those listed under “Absolu te Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those indi-

cated in the operational sections of this specification) is

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability .

RECOMMENDED OPERATING CONDITIONS

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Notes: (1) T ypical values are for TA = 25°C and nominal supply voltage

(2) VIL min. and VIH max. are for reference only and are not tested.

Temperature Min. Max.

Commercial 0°C +70°C

Industrial -40°C +85°C

Military -55°C +125°C

Supply Voltage Limits

X28HC64 5V ±10%

Symbol Parameter

Limits

Unit Test ConditionsMin. Typ.(1) Max.

ICC VCC current (active)

(TTL inputs) 15 40 mA CE = OE = VIL, WE = VIH, All I/O’s = open,

address inputs = TTL levels @ f = 10 MHz

ISB1 VCC current (standby)

(TTL inputs) 12mACE = VIH, OE = VIL All I/O’s = open,

other inputs = VIH

ISB2 VCC current (standby)

(CMOS inputs) 100 200 µA CE = VCC - 0.3V, OE = GND, All I/O’s = open,

other inputs = VCC - 0.3V

ILI Input leakage current ±10 µA VIN = VSS to VCC

ILO Output leakage current ±10 µA VOUT = VSS to VCC, CE = VIH

VlL(2) Input LOW voltage -1 0.8 V

VIH(2) Input HIGH voltage 2 VCC + 1 V

VOL Output LOW voltage 0.4 V IOL = 5mA

VOH Output HIGH voltage 2.4 V IOH = -5mA

X28HC64

13 FN8109.1

June 7, 2006

ENDURANCE AND DATA RETENTION

POWER-UP TIMING

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

A.C. CONDITIONS OF TEST MODE SELECTION

Note: (3) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUITS SYMBOL TABLE

Parameter Min. Max. Unit

Minimum endurance 100,000 Cycles

Data retention 100 Years

Symbol Parameter Typ.(1) Unit

tPUR(3) Power-up to read operation 100 µs

tPUW(3) Power-up to write operation 5 ms

Symbol Parameter Max. Unit Test Conditions

CI/O(3) Input/output capacitance 10 pF VI/O = 0V

CIN(3) Input capacitance 6 pF VIN = 0V

Input pulse levels 0V to 3V

Input rise and fall times 5ns

Input and output timing levels 1.5V

CE OE WE Mode I/O Power

L L H Read DOUT Active

LHL Write D

IN Active

H X X Standby and

write inhibit High Z Standby

X L X Write inhibit — —

X X H Write inhibit — —

1.92kΩ

30pF

Output

1.37kΩ

WAVEFORM INPUTS OUTPUTS

Must be

steady Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

X28HC64

14 FN8109.1

June 7, 2006

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Read Cycle Limits

Read Cycle

Note: (4) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measu red from the point

when CE or OE return HIGH (whichever occurs first) to the time when the output s are no longer driven.

Symbol Parameter

X28HC64-70 X28HC64-90 X28HC64-12

Unit

-55°C to +125°C -55°C to +125°C -55°C to +125°C

Min. Max. Min. Max. Min. Max.

tRC Read cycle time 70 90 120 ns

tCE Chip enable access time 70 90 120 ns

tAA Address access time 70 90 120 ns

tOE Output enable access time 35 40 50 ns

tLZ(4) CE LOW to active output 0 0 0 ns

tOLZ(4) OE LOW to active output 0 0 0 ns

tHZ(4) CE HIGH to high Z output 30 30 30 ns

tOHZ(4) OE HIGH to high Z output 30 30 30 ns

tOH Output hold from address change 0 0 0 ns

tCE

tRC

Address

Data Valid

tOE

tLZ

tOLZ

tOH

tAA

tHZ

tOHZ

Data I/O

VIH

HIGH Z Data Valid

X28HC64

15 FN8109.1

June 7, 2006

WRITE CYCLE LIMITS

WE Controlled Write Cycle

Notes: (5) tWC is the minimum cycle time to be allowed from the system per spective unless polling techn iques are used. It is the maximum time

the device requires to automatically complete the internal write operation.

(6) tWPH and tDW are periodically sampled and not 100% tested.

Symbol Parameter Min. Typ.(1) Max. Unit

tWC(5) Write cycle time 2 5 ms

tAS Address setup time 0 ns

tAH Address hold time 50 ns

tCS Write setup time 0 ns

tCH Write hold time 0 ns

tCW CE pulse width 50 ns

tOES OE High setup time 0 ns

tOEH OE High hold time 0 ns

tWP WE pulse width 50 ns

tWPH(6) WE HIGH recovery 50 ns

tDV(6) Data valid 1µs

tDS Data setup 50 ns

tDH Data hold 0 ns

tDW(6) Delay to next write 10 µs

tBLC Byte load cycle 0.15 100 µs

Address

tAS

tWC

tAH

tOES

tDS tDH

tOEH

Data In

Data Out HIGH Z

tCS tCH

tWP

tDV

Data Valid

X28HC64

16 FN8109.1

June 7, 2006

CE CONTROLLED WRITE CYCLE

Page Write Cycle

Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH

to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a

polling operation.

(8) The timings shown above are unique to page write operations. Individual byte load op erations within the page write must conform to

either the CE or WE controlled write cycle timing.

Address

tAS

tOEH

tWC

tAH

tOES

tCS

tDS tDH

tCH

Data In

Data Out HIGH Z

Data Valid

tCW

tDV

OE(7)

Last Byte

Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2

tWP

tWPH

tBLC

tWC

Address*(8)

I/O

*For each successive write within the page write operation, A6–A12 should be the same or

writes to an unknown address could occur.

X28HC64

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FN8109.1

June 7, 2006

DATA Polling Timing Diagram(9)

Toggle Bit Timing Diagram(9)

Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.

Address An

DIN = X DOUT = X

tWC

tOEH tOES

AnAn

I/O7

tDW

DOUT = X

I/O*6

tOES

tDW

tWC

tOEH

HIGH Z *

* I/O6 beginning and ending state will vary, depending upon actual tWC.

X28HC64