8EBV89316 Installation Guide - Windows®
Prepare Hardware
1. Choose suitable power adapter from selection provided
in the evaluation kit
2. Attach adapter to power supply and plug in to mains
supply but do not plug into the board yet
3. Plug USB cable into computer but do not plug into
board yet
4. Check jumper and DIP switch settings match the
8EBV89316 hardware configuration shown on the next
page
8EBV89316 Hardware Configuration
7
9
8
12
13 14 15 16
17
17
17
3
18
5
20
6
1
11
19
10
4
2
8EBV89316 Hardware Configuration
[1] JP9 jumper. Leave at factory set position for normal
operation (linking center and right pins)
[2] JP6 and JP7 jumpers. Leave at factory set position
for normal operation (linking center and lower pins)
[3] LVCMOS Output clock
[4] IDT8V89316 chip
[5] Switch SW5: The function of this switch is described
in Table 1
[6] Crystal oscillator Master Clock
[7] +5 V DC power supply
[8] +3.3 V power supply for test purpose
[9] +5 V power supply for test purpose
[10] Crystal oscillator for APLL
[11] OSCI: master clock input
[12] Output clock 4 (differential)
[13] Output clock 3 (differential)
[14] Output clock 2 (differential)
[15] Output clock 1 (differential)
[16] Input clock to APLL (differential)
[17] Input clock 1, 2 and 3
[18] USB communication port
[19] DPLL lock indicator
[20] Reset button: Press to reset all devices on the
board. Restart the management API following a
reset to reconnect the host computer to the board.
Note: Evaluation board GUI expects a fixed I2C address
of 0x51. SW5-7 and SW5-8 should be set to 0 (off) for
normal operation.
Switch
Function
SW5-1
Not used
SW5-2
Not used
SW5-3
Must be set on for normal operation
Off: “0”
On: “1”
SW5-4
Not used
SW5-5
Not used
SW5-6
Not used
SW5-7
I2C_AD1
Set off for normal operation
Off: “0”
On: “1”
SW5-8
I2C_AD2
Set off for normal operation
Off: “0”
On: “1”
Table 1: Switch SW5 Functions
Install 8EBV89316 Software
1. Unzip the 8EBV89316 and 8EBV89317 combined GUI zip file and
copy contents to a new folder on the Windows®-based computer
(for example C:\Users\...\Desktop\PLL _GUI_Files)
2. If Java® is not already installed on the computer, install it from
http://www.oracle.com/technetwork/java/javase/downloads/jre8-downloads-2133155.html
3. If Visual Studio® C++ Redistributable Package is not already
installed on the computer, install it from
http://www.microsoft.com/en-ca/download/details.aspx?id=5555
4. Click on http://www.ftdichip.com/Drivers/D2XX.htm
5. Click on “set executable” in table, this launches the following
executable:
http://www.ftdichip.com/Drivers/CDM/CDM%20v2.10.00%20WHQL%20Certified.exe
6. For manual installation using Windows® device manager, follow
procedure in [1] on the “Useful Information and Links” page at the
end of this guide
Start Hardware and Connect to Management API
1. Plug USB cable into board
–Red LED LD8 lights next to USB socket on board
–Windows® drivers load for new hardware
2. Plug power supply into socket marked J55
–Red LEDs LD5 and LD6 light
3. Run winpllmgmt.exe from the folder created in step 1 – either
from a DOS window or by double-clicking the file in Explorer
4. A DOS window appears a shown on the next page. Leave
this window open. CTRL-C stops the process and returns to
the command prompt.
5. To reconnect the board to the Management API after a
manual board reset, run winpllmgmt.exe again as in step 3
above.
Connect to Management API
GUI Start Screen
•Run PllGui.jar from the folder created in step 1 – either from a DOS
window or by clicking the file in Explorer. The window below
appears.
Useful information and links
•The computer is now connected to the Evaluation board
and the GUI is ready for use. Details of the GUI
operation are found in the “Ethernet PLL Configuration
GUI User Manual” included with the GUI zip file
•FTDI chip Windows® 7 application note an-119:
http://www.ftdichip.com/Support/Documents/AppNotes/AN_119_FTDI_Drivers_Installation_Guid
e_for_Windows7.pdf
Note that USB 2.0 connection using USB 3.0 ports in Windows 7 is not currently supported
•USB view (for verifying the FTDI USB port location)
–http://www.ftdichip.com/Support/Utilities/usbview.zip
Windows and Visual Studio are registered trademarks of Microsoft Corporation in the United States and/or other countries.
Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective
owners.
USB View for Typical USB Tree
PAGE 11
Schematics
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
8V89316
12.8MHz
TCXO/OCXO
Power Supply
USB- I2C
module
Jtag
LED Status
uController
IN1
IN3
OUT1
OUT7
Recovery Clock Sources
XTAL Interface
......
......
IN_APLL
Disclaimer: IDT is providing this schematic for reference purposes only.
Although the schematic was taken from a known working design, it is
being provided "as is" without any express or implied warranty of any kind.
Title
Size Document Number Rev
Date: Sheet of
Block Diagram 0.0
SCHEMATIC, 8V89316EVB REV A
A
15Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
Block Diagram 0.0
SCHEMATIC, 8V89316EVB REV A
A
15Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
Block Diagram 0.0
SCHEMATIC, 8V89316EVB REV A
A
15Friday, June 14, 2013
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SCHEMATIC, 8V89316 EVB REV A
Place close to the
DUT pins CAP1~3
Place the bypass caps close to the
DUT power/ground pins
TDI
TMS
TCK
TDO
TRST
OSCI
IN1
IN2
IN3
IN_APLL_POS
IN_APLL_NEG
INT_REQ
OUT7
OUT5_POS
OUT5_NEG
OUT6_NEG
OUT6_POS
XTAL_IN
XTAL_OUT
I2C_SDA
I2C_AD1
I2C_AD2
DPLL_LOCK
TDI
TDO
TRST
TMS
TCK
I2C_SCL
RST
I2C_AD2
I2C_AD1
XTAL_IN
XTAL_OUT
I2C_SDA
I2C_SCL
IN_APLL_POS
OUT1_NEG
OUT1_POS
OUT3_NEG
OUT3_POS
OUT2_NEG
OUT2_POS
OUT4_NEG
OUT4_POS
VSSD
VSSD
VDDDO
VSSDO
VSSA
VDDD
VSSD
VDDD
VSSAO
VDDAO
VSSD
VSSAO
GND
VCC3V3_2
VDDA
VDDDO
VSSDO
VSSA
VDDA
VDDA
VSSA
VSSA
VDDA1 VDDD
VDDA2
VSSA
VSSA
VDDD
VSSD
VSSA
GND
VDDAO
VSSAOVDDAO
VSSAO
VDDAO
VSSAO
VDDAO
VSSAO
VDDA2
VDDA1
OUT7
OSCI
RST
IN1
IN2
IN3
IN_APLL_POS
IN_APLL_NEG
DPLL_LOCK
I2C_SDA
I2C_SCLXTAL_OUT
XTAL_IN
OUT2_POS
OUT3_POS
OUT1_POS
OUT4_NEG
OUT2_NEG
OUT3_NEG
OUT1_NEG
OUT4_POS
Title
Size Document Number Rev
Date: Sheet of
8V89316 0.0Custom
25Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
8V89316 0.0Custom
25Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
8V89316 0.0Custom
25Friday, June 14, 2013
C78
0.1u
TP4
TP8
C79
0.1u
C76
0.1u
J1
CON20A
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
C11
1nF
C70
0.1u
C31
0.1u
TP5
C89
0.1u
C73
0.1u
C136
0.1u
TP29
TP6TP32
C103
0.1u
C6
0.1u
C137
0.1u
TP30
C74
0.1u
C20
0.1u C175
0.1u
U13
IDT8V89316
RST
H13
NC_B5
B5
NC_A5
A5
IN_APLL2_POS
N6
IN_APLL2_NEG
P6
IN1
H14
OSCI
A11
IN2
J13
IN3
J14
NC_C3
C3
NC_B1
B1
NC_M12
M12
OUT2_POS N2
OUT2_NEG P2
XTAL_OUT
N10 XTAL_IN
P10
OUT6_POS B3
OUT6_NEG A3
ISET_APLL
P13
NC_C1
C1
APLL_LF1
N12
VSSAO
B4
VSSAO D1
VSSAO
D2
OUT5_POS E2
OUT5_NEG E1
VSSAO D4
NC_M13
M13 NC_M14
M14
OUT4_NEG J1
CAP3 L14
NC_A1 A1
INT_REQ C13
OUT1_NEG P4
OUT1_POS N4
OUT3_NEG L1
OUT3_POS L2
CAP2 L12
CAP1 L10
I2C_SCL K13
I2C_AD2 L9
I2C_AD1 L8
I2C_SDA K14
VSSA
J9
IC3 G8
OUT4_POS J2
OUT7 F13
IC2 D9
IC1 E9
TDO B8
VC0 A9
VC4 A13
APLL_LF0 P12
VSSAO B2
VSSAO E3
VSSAO
E4
VSSAO E5
VSSAO
F2
VSSAO
F3
VSSAO F4
VSSAO
F6
VSSAO
G1
VSSAO
G3
VSSAO
G4
VSSAO
G5
VSSD
G6
VSSAO
H2
VSSAO
H4
VSSAO
H6 VSSAO
J4
VSSAO
K1 VSSAO
K2
VSSAO
K3
VSSAO
N1
VSSAO
H5
DPLL_LOCK J11
VSSAO
J6
VSSAO
J8
VSSAO
K5
VSSAO
K7
VSSD
K8
VSSAO
K10
VSSAO
L4
VSSAO
L5
VSSAO
L6
VSSAO
L7
VSSA L11
VSSA L13
VSSAO
M4
VSSAO
M6
VSSAO
M8
VSSAO
M9
VSSAO
M10
VSSAO
M11
VSSAO
N3
VSSAO
N5
VSSA
N9
VSSA
N11
VSSAO
N13
VSSA
N14
VSSAO
P3
VSSA E12
VSSA B12
VSSA C10
VSSA E10
VSSA
D11
VSSAO
B9
VSSA
B11
VSSD
D7
VSSD
E7
VSSDO C8
VSSDO B13
VSSDO F14
VSSAO
M3
VSSD
F7 VSSD
F9 VSSD
G10 VSSD
H7 VSSD
H9
VDDAO C2
VDDAO D5
VDDAO F5
VDDA P11
VDDA P14
VDDA P9
NC_A4 A4
NC_C4 C4
NC_D3 D3
VDDDO F12
VDDAO
M1
VDDAO F1
VDDAO G2
VDDA J10
VDDD K9
VDDAO H1
VDDAO H3
VDDAO J3
VDDAO J7
VDDAO K6
VDDAO P1
VDDAO J5
VDDAO K4
VDDAO L3
VDDAO M5
VDDAO M7
VDDAO P5
VDDA C12
VDDA D12
VDDA
C9
VDDA D10
VDDA
C11 VDDA
E11
VDDD
D8
VDDD
E8
VDDD F10
VDDD F8
VDDD G7
VDDD G9
VDDD H10
VDDD H8
VDDDO B14
VDDAO A2
VDDDO C7
TRST A14
TMS A12
TCK B10
TDI A8
VSSAO
M2
TP7
C84
0.1u
TP33
C69
0.1u
C104
10u
C87
0.1u
TP31
C82
0.1u
TP19
C71
0.1u
C68
0.1u
C164
10u
C4
0.1u
C85
0.1u
C105
0.1u
RP1
5.1K*8
1
2
3
4
5
6
7
8
9
C88
0.1u
C80
0.1u
R73
100
C83
0.1u
C75
0.1u
C77
0.1u
SW5 SW_DIP_8
1
216
15
3
4
5
6
7
8
14
13
12
11
10
9
C72
0.1u
JP8
I2C Test Point
C81
0.1u
C86
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IN2
IN3
IN1 OUT7
OUT2_P
OUT2_N
SMA's for input can be either END LAUNCH
or STRAIGHT depends on which way save
space. TBD during layout
No Stub
Close to SMA
if long trace
Series termination resistors close to output driver
No Stub
Close to SMA
if long trace
OUT4_P
OUT4N
Close to IC pins
IN_APLL_P
IN_APLL_N
No Stub
Close to SMA
if long trace
OUT1_P
OUT1_N
No Stub
Close to SMA
if long trace
OUT3_P
OUT3_N
SPARE At OUTPUT SMA's
OUT4
nOUT4
OUT3
nOUT3
OUT2
nOUT2
OUT1
nOUT1
OUT7
OUT7
OUT2_N
OUT2_P
OUT2_POS
OUT2_NEG
OUT4_P
OUT4_POS
OUT4_NEG
IN_APLL_NEG
IN_APLL_POS
OUT3_NEG
OUT1_N
OUT1_P
OUT1_POS
OUT1_NEG
OUT3_N
OUT3_P
OUT3_POS
OUT4_N
VCC3V3_2
VCC3V3_2
VCC3V3_2
VCC3V3_2
VCC3V3_2
GNDGND
VCC3V3_2
GND
VCC3V3_2
VCC3V3_2
VCC3V3_2
GND
VCC3V3_2
GND
IN2
IN1
IN3
OUT2_POS
OUT2_NEG
OUT7
OUT4_POS
OUT4_NEG
IN_APLL_POS
IN_APLL_NEG
OUT1_POS
OUT1_NEG
OUT3_POS
OUT3_NEG
Title
Size Document Number Rev
Date: Sheet of
8V89316_IO_Termination 0.0
SCHEMATIC, 8V89316 EVB REV A
Custom
35Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
8V89316_IO_Termination 0.0
SCHEMATIC, 8V89316 EVB REV A
Custom
35Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
8V89316_IO_Termination 0.0
SCHEMATIC, 8V89316 EVB REV A
Custom
35Friday, June 14, 2013
J15
R128
NP
R72
SP
C34 0.1u
J66
J13
C50
0.1u
J69
R110
133
R166
NP R170
NP
R85
150
C25 0.1u
R279
SP
R48
SP
C44
0.1u
R273
SP
C43 0.1u
J40
C40 0.1u
R111
133
R142
NP
R88
100
J8
J67
C51
0.1u
R171
NP
R86
150
R102
SP
R280
150
R53
150
C26 0.1u
R76
NP
R274
150
TP9
J70
C61 0.1u
R70
SP
R112
82
R89
100
TP22
R146
NP
C45
0.1u
R172
NP
R103
SP
J41
R87
SP
R92
100
R54
150
R39
SP
J10
J31
R275
150
R26
33
J16
R281
150
R113
82
R159
NP
R44
SP
R64
SP
R173
NP
C41 0.1u
R93
100
J33
R167
NP
R141
NP
C46
0.1u
R36
SP
R161
NP R174
NP
R90
100
R71
NP
R51
SP
R168
NP
R65
SP
C42 0.1u
J4
R115
SP
TP2
R91
100
R165
NP R169
NP
R84
SP
R140
SP
TP3
R47
SP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Indicator
12.8MHz, TCXO or OCXO ( Place close to the DUT)
25MHz XTAL Interface (Place close to the DUT and Put xtals on same layer as BGA pads, shorter trace length, no stubs)
USB to I2C
1) Clocks and frequently switched signals should not be routed close to the crystals.
2) Digital signals should not be routed directly under the crystal or XTALn_IN/OUT pins.
3) Keep the crystal bond pads and trace width to the XTALn_IN/OUT pins as small as possible.
4) All metal layers in the PCB are recommended to be removed under the XTALn_OUT ball, crystal pad and associated trace.
5) It is recommended to protect crystal traces with ground traces and guard rings.
T0_LOCK
RST
SCL2
SDA2
TCXO
OCXO
OCXO_Power
OCXO_Power
XTAL_OUT
XTAL_IN
SCL2
SCL1
SDA1
I2C_SDA
I2C_SCL
SDA2
SCL1
3V3_USB
3V3_USB
XTIN
VCC2232VCC2232
3V3_USB
XTOUT
SDA1
VCC2232
I2C_SCL
I2C_SDA
OCXO_Power
OCXO_Power
3V3_USB
SCL1
XTAL_IN
XTAL_OUT
OCXO_Power
VCC_OCXO
VCC3V3_2
VCC2232_3V
VCC3V3_2
VCC3V3_2
VCC3V3_2
VCC3V3_2
VCC3V3_2
VCC3V3_2
RST
OSCI
T0_LOCK
I2C_SDA
I2C_SCL
XTAL_OUT
XTAL_IN
Title
Size Document Number Rev
Date: Sheet of
8V89316_Control 0.0
SCHEMATIC, 8V89316 EVB REV A
Custom
45Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
8V89316_Control 0.0
SCHEMATIC, 8V89316 EVB REV A
Custom
45Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
8V89316_Control 0.0
SCHEMATIC, 8V89316 EVB REV A
Custom
45Friday, June 14, 2013
TP1
R189
0
1 2
L8
BLM18BB221SN1
R10
0
C169
33PF
R191
SP
C17
0.1u
R152
1K
R154
470
R8
0
C171 0.1u
R158
10K
12
LD1
C165
10u
R9
100
JP6
Header_3Pin
C9
0.1u
U6 M5626LF 12.8MHz
DNC
1GND 2
OUT 3
VCC
4
U2
2910 Stratum 3E OCXO
INPUT_SUPPLY
3
NC2
2NC5 5
RF_OUTPUT 4
NC1
1NC6 6
GND 7
JP9
XO/SMA option
C167
0.1u
C170
33PF
J68
Aardvark I2C/SPI Host Adapter
1 2
3 4
5 6
7 8
9 10
C10
0.1u
R24
SP
R13
SP
R153
470
1 2
J3
USB PORT
VBUS 1
D- 2
D+ 3
GND 4
5
5
6
6
C13
0.1u
JP7
Header_3Pin
R77
27
1 2
R79
1K
C47
10u
R11
100
R6 SP
C8
0.1u
R5
SP
R187
4.7K
LD8
RED LED
12
U1
12M8_ TCXO
DNC1
1
NC2
2
DNC3
3NC6 6
NC7 7
Tri-state_Enable 8
GND 4
OUT 5
VCC
9
DNC10
10
SW2
SW_PUSHBUTTON
C166
0.01u
R3
0
C12
0.1u
R78
27
1 2
U3
ft2232_chip
EESK
1
EEDATA
2
VCC 3
RESET#
4
RSTOUT#
5
3V3OUT
6
USBDP
7
USBDM
8
GND
9
SI/WUA 10
GPIOH3 11
GPIOH2 12
GPIOH1 13
VCCIOA 14
GPIOH0 15
GPIOL3 16
GPIOL2 17
GND
18
GPIOL1 19
GPIOL0 20
TMS/CS 21
TDO/DI 22
TDI/DO 23
TCK/SK 24
GND
25
SI/WUB 26
UNUSED11 27
UNUSED10 28
UNUSED9 29
UNUSED8 30
VCCIOB 31
UNUSED7 32
UNUSED6 33
GND
34
UNUSED5 35
UNUSED4 36
UNUSED3 37
UNUSED2 38
UNUSED1 39
UNUSED0 40
PWREN# 41
VCC 42
XTIN
43
XTOUT
44
AGND
45 AVCC 46
TEST
47
EECS
48
Y3
6MHz
12
R74
10K
C48
0.1u
R188
4.7K
U4
RTX5032
NC1
1
NC2
2
NC3
3
RF OUT 6
VC FILTER 7
NC8 8
GND
4
NC5
5
VCC 9
NC10 10
U7C
74HC14/SO
56
14
7
C3
0.1u
R1
SP
R7
SP
C147
0.1u
C138
0.1u
X40025.000000 MHz
L9
BLM18BB221SN1
J2
U7D
74HC14/SO
9 8
14
7
R157
10K
12
R190
SP
R14
0
C2
0.1u
U7F
74HC14/SO
13 12
14
7
C15
0.1u
C7
10u
R2
SP
R156
10K
1 2
C39
1u
R80
1.5K
12
LD9
Green LED
12
C168
0.1u
C1
10u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC5V
8V89316 Analog Power
8V89316 Analog OUTPUT Power
8V89316 Digital Power
(Place caps close to and accross power and ground pins)
VCC_OCXO
GND 8V89316 Digital Output Power
(VCC3V3_1 is used for the 8V89316 DUT and VCC3V3_2 is for the rest of the board circuits.
We are not suggesting a dedicated LDO for the 8V89316 with this reference design, this is just convenient for the test.)
5V VCC3V3_1
VCC5
VCC_OCXO
VCC3V3_2
VDDA
VDDD
VDDDO
VCC3V3_1VCC3V3_1
VDDAO
VSSDO
VDDDO
VSSA
VDDA
VCC5
VCC3V3_1
VSSD
VDDD
VSSAO
VDDAO
VCC_OCXO
VCC3V3_2
VDDA1 VDDA2VDDA VDDA
Title
Size Document Number Rev
Date: Sheet of
Power/GND 0.0
SCHEMATIC, 8V89316 EVB REV A
C
55Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
Power/GND 0.0
SCHEMATIC, 8V89316 EVB REV A
C
55Friday, June 14, 2013
Title
Size Document Number Rev
Date: Sheet of
Power/GND 0.0
SCHEMATIC, 8V89316 EVB REV A
C
55Friday, June 14, 2013
C125
0.1u
JP14
C118
SP
R193
SP
L17
BLM18BB221SN1
C91
47u
LD6
D4
CGRA4004-G
R125 0
R124
0
C108
0.1u
R136
SP
C178
0.1u
C95
10u
JP13
C130
0.1u
L2
BLM18BB221SN1
C98
0.1u
JP12
C115
0.1u
U11
VREG_LT1764AEQ_3.3
VIN
2VOUT 4
GND
3
SENSE 5
SHDN
1
C174
47u
D2
CGRA4004-G
R195
470
C179
0.1u
C114
0.1u
L14
C129
SP
R129
470
J57
R194
SP
C99
0.1u
C160
0.1u
C100
0.1u
JP1
C116
0.1u
C94
47u
LD5
J58
C126
0.01u
C133
0.1u
C145
10u
C90
0.1u
C180
SP
C150
10u
C172
47u
R196
SP
J55
POWER_SOCKET
1
2
3
J54
C97
SPARE
C96
0.1u
L7
BLM18BB221SN1
C127
0.1u
U10
VREG_LT1764AEQ_3.3
VIN
2VOUT 4
GND
3
SENSE 5
SHDN
1
C153
10u
D1
CGRA4004-G
C93
470uF
C141
0.1u
C92
SP
C176
10u
R197
SP
C122
0.1u
C134
0.1u
R139
SP
JP5
R192 0
C144
0.1u
C142
0.1u
C140
0.1u
C173
0.1u
JP2
C177
0.1u
C128
0.01u
C102
0.1u C148
10u