8EBV89316 Installation Guide - Windows(R) Prepare Hardware 1. Choose suitable power adapter from selection provided in the evaluation kit 2. Attach adapter to power supply and plug in to mains supply but do not plug into the board yet 3. Plug USB cable into computer but do not plug into board yet 4. Check jumper and DIP switch settings match the 8EBV89316 hardware configuration shown on the next page 8EBV89316 Hardware Configuration 1 7 6 2 19 5 11 18 20 9 4 12 3 10 17 17 8 13 14 15 16 17 8EBV89316 Hardware Configuration [1] JP9 jumper. Leave at factory set position for normal operation (linking center and right pins) [2] JP6 and JP7 jumpers. Leave at factory set position for normal operation (linking center and lower pins) [3] LVCMOS Output clock [4] IDT8V89316 chip [5] Switch SW5: The function of this switch is described in Table 1 [6] Crystal oscillator Master Clock [7] +5 V DC power supply [8] +3.3 V power supply for test purpose [9] +5 V power supply for test purpose [10] Crystal oscillator for APLL [11] OSCI: master clock input [12] Output clock 4 (differential) [13] Output clock 3 (differential) [14] Output clock 2 (differential) [15] Output clock 1 (differential) [16] Input clock to APLL (differential) [17] Input clock 1, 2 and 3 [18] USB communication port [19] DPLL lock indicator [20] Reset button: Press to reset all devices on the board. Restart the management API following a reset to reconnect the host computer to the board. Table 1: Switch SW5 Functions Switch Function SW5-1 Not used SW5-2 Not used SW5-3 Must be set on for normal operation SW5-4 Not used SW5-5 Not used SW5-6 Not used SW5-7 I2C_AD1 Set off for normal operation Off: "0" On: "1" SW5-8 I2C_AD2 Set off for normal operation Off: "0" On: "1" Off: "0" On: "1" Note: Evaluation board GUI expects a fixed I2C address of 0x51. SW5-7 and SW5-8 should be set to 0 (off) for normal operation. Install 8EBV89316 Software 1. Unzip the 8EBV89316 and 8EBV89317 combined GUI zip file and copy contents to a new folder on the Windows(R)-based computer (for example C:\Users\...\Desktop\PLL _GUI_Files) 2. If Java(R) is not already installed on the computer, install it from http://www.oracle.com/technetwork/java/javase/downloads/jre8-downloads-2133155.html 3. If Visual Studio(R) C++ Redistributable Package is not already installed on the computer, install it from http://www.microsoft.com/en-ca/download/details.aspx?id=5555 4. Click on http://www.ftdichip.com/Drivers/D2XX.htm 5. Click on "set executable" in table, this launches the following executable: http://www.ftdichip.com/Drivers/CDM/CDM%20v2.10.00%20WHQL%20Certified.exe 6. For manual installation using Windows(R) device manager, follow procedure in [1] on the "Useful Information and Links" page at the end of this guide Start Hardware and Connect to Management API 1. Plug USB cable into board - Red LED LD8 lights next to USB socket on board - Windows(R) drivers load for new hardware 2. Plug power supply into socket marked J55 - Red LEDs LD5 and LD6 light 3. Run winpllmgmt.exe from the folder created in step 1 - either from a DOS window or by double-clicking the file in Explorer 4. A DOS window appears a shown on the next page. Leave this window open. CTRL-C stops the process and returns to the command prompt. 5. To reconnect the board to the Management API after a manual board reset, run winpllmgmt.exe again as in step 3 above. Connect to Management API GUI Start Screen * Run PllGui.jar from the folder created in step 1 - either from a DOS window or by clicking the file in Explorer. The window below appears. Useful information and links * The computer is now connected to the Evaluation board and the GUI is ready for use. Details of the GUI operation are found in the "Ethernet PLL Configuration GUI User Manual" included with the GUI zip file * FTDI chip Windows(R) 7 application note an-119: http://www.ftdichip.com/Support/Documents/AppNotes/AN_119_FTDI_Drivers_Installation_Guid e_for_Windows7.pdf Note that USB 2.0 connection using USB 3.0 ports in Windows 7 is not currently supported * USB view (for verifying the FTDI USB port location) - http://www.ftdichip.com/Support/Utilities/usbview.zip Windows and Visual Studio are registered trademarks of Microsoft Corporation in the United States and/or other countries. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. USB View for Typical USB Tree Schematics PAGE 11 5 4 3 2 1 Disclaimer: IDT is providing this schematic for reference purposes only. Although the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty of any kind. D D Power Supply XTAL Interface 12.8MHz TCXO/OCXO LED Status IN1 IN3 OUT1 ...... Recovery Clock Sources C ...... C 8V89316 IN_APLL OUT7 Jtag B B USB- I2C module uController A A Title SCHEMATIC, 8V89316EVB REV A Size A Date: 5 4 3 Document Number Block Diagram Friday, June 14, 2013 2 Rev 0.0 Sheet 1 of 1 5 5 4 3 VDDA2 VDDA1 2 1 VDDD J1 C31 0.1u C86 0.1u C20 0.1u C105 0.1u C103 0.1u C137 0.1u VSSA C136 0.1u C175 0.1u C88 0.1u 1 3 5 7 9 11 13 15 17 19 TDI TMS TCK C87 0.1u VSSD TDO TRST 2 4 6 8 10 12 14 16 18 20 D D CON20A VDDD VDDA2 VDDA1 C84 0.1u VSSA OSCI C85 0.1u OSCI E11 C11 D11 B11 A11 L11 L13 C104 10u VSSA VDDA VDDA VSSA VSSA OSCI OUT7 OUT6_POS OUT6_NEG OUT5_POS OUT5_NEG RST RST H13 RST VDDDO VDDDO VSSDO VSSDO C11 1nF OUT4_POS OUT4_NEG VDDAO VDDAO VDDAO VSSD C VCC3V3_2 IN1 IN2 IN3 R73 100 SW5 IN1 IN2 IN3 H14 J13 J14 OUT3_POS OUT3_NEG VDDAO VDDAO VDDAO 16 15 14 13 12 11 10 9 I2C_AD1 I2C_AD2 IN_APLL_POS IN_APLL_NEG IN_APLL_POS IN_APLL_NEG RP1 GND B5 A5 N6 P6 C3 B1 C1 D8 D7 M12 N12 P13 E8 E7 TP29 TP30 TP31 9 8 7 6 5 4 3 2 1 VDDD C68 0.1u VSSD VDDD 5.1K*8 C69 0.1u VSSD B IN1 IN2 IN3 SW_DIP_8 1 2 3 4 5 6 7 8 XTAL_OUT XTAL_IN XTAL_OUT XTAL_IN XTAL_IN XTAL_OUT P10 N10 OUT2_POS OUT2_NEG VDDAO VDDAO VDDAO NC_B5 NC_A5 IN_APLL2_POS IN_APLL2_NEG OUT1_POS OUT1_NEG VDDAO VDDAO VDDAO NC_C3 NC_B1 NC_C1 VDDD VSSD NC_M12 APLL_LF1 ISET_APLL VDDD VSSD VDDDO VSSDO NC_A1 APLL_LF0 VC4 VC0 XTAL_IN XTAL_OUT INT_REQ I2C_SDA I2C_AD1 I2C_AD2 I2C_SCL VDDAO C70 C164 10u M14 M13 M1 M3 0.1u NC_M14 NC_M13 VDDAO VSSAO TDO TRST TMS TCK TDI VSSAO IDT8V89316 A OUT7 B3 A3 OUT6_POS OUT6_NEG E2 E1 OUT5_POS OUT5_NEG OUT7 VDDDO B14 F12 F14 B13 J2 J1 H3 J3 H1 C6 0.1u OUT4_POS OUT4_NEG L2 L1 J5 K4 L3 OUT3_POS OUT3_NEG N2 P2 J7 K6 P1 OUT2_POS OUT2_NEG N4 P4 M5 M7 P5 OUT1_POS OUT1_NEG C4 0.1u VSSDO OUT4_POS OUT4_NEG VDDAO C71 0.1u OUT3_POS OUT3_NEG VDDAO VSSAO C73 0.1u OUT2_POS OUT2_NEG C74 0.1u VSSAO Place the bypass caps close to the DUT power/ground pins VDDAO C75 0.1u OUT1_POS OUT1_NEG C C72 0.1u C76 0.1u VSSAO VDDAO C77 0.1u C7 C8 C78 0.1u VSSAO VDDDO C79 0.1u A1 P12 A13 A9 VSSDO TP8 C13 K14 L8 L9 K13 INT_REQ I2C_SDA I2C_AD1 I2C_AD2 I2C_SCL B8 A14 A12 B10 A8 TDO TRST TMS TCK TDI JP8 I2C_SDA I2C_SDA I2C_SCL B I2C Test Point I2C_SCL GND E9 D9 G8 DPLL_LOCK VDDA VDDA VSSA VSSA J11 C9 D10 C10 E10 C80 0.1u DPLL_LOCK C81 0.1u DPLL_LOCK VSSA VDDA C82 0.1u E5 B2 D1 F4 C83 0.1u VSSA VSSA VSSA VSSA VSSA VSSAO VSSAO VSSAO VSSAO C12 D12 B12 E12 N9 N11 N14 J9 VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO F13 VDDA VDDA VDDA VSSA VSSA VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO VSSAO G3 G4 G5 M2 H2 H4 F6 IC1 IC2 IC3 VSSD VSSAO VSSD VSSAO VSSD VSSD VSSD VSSD VSSD J4 H6 K2 K1 H5 K3 F3 E4 B4 D2 J6 J8 K5 K7 K10 L4 L5 L6 L7 M4 M6 M8 M9 M10 M11 N1 N3 N5 N13 P3 B9 VSSD K8 F2 G6 G1 H9 H7 G10 F9 F7 Place close to the DUT pins CAP1~3 VSSA VSSA L10 L12 L14 CAP1 CAP2 CAP3 F1 G2 K9 F8 G7 G9 H10 H8 F10 VDDAO VDDAO VDDD VDDD VDDD VDDD VDDD VDDD VDDD J10 P11 P14 P9 A2 C2 D5 F5 VDDA VDDA VDDA VDDA VDDAO VDDAO VDDAO VDDAO A4 C4 D3 VSSAO VSSAO VDDA NC_A4 NC_C4 NC_D3 VSSA U13 D4 E3 C89 0.1u TP19 A VSSA IN_APLL_POS VSSAO TP33 TP32 TP4 TP5 TP6 TP7 Title SCHEMATIC, 8V89316 EVB REV A Size Document Number Custom Date: 5 4 3 2 Rev 0.0 8V89316 Sheet Friday, June 14, 2013 1 2 of 5 5 4 3 2 1 VCC3V3_2 Series termination resistors close to output driver R92 100 IN1 C44 TP22 R26 OUT7 OUT7 TP2 OUT7 J4 33 J8 SPARE At OUTPUT SMA's IN1 VCC3V3_2 0.1u D TP3 R128 NP IN2 R39 R91 100 R161 NP R166 NP R169 NP R168 NP R170 NP R171 NP R173 NP R172 NP R174 NP GND VCC3V3_2 VCC3V3_2 C46 J13 R76 NP TP9 OUT7 R88 100 IN3 R44 R167 NP 0.1u SP IN3 R146 NP R165 NP OUT1 OUT4 R90 100 R159 NP nOUT1 C45 nOUT4 IN2 J10 R142 NP OUT2 R71 NP SP nOUT2 R93 100 OUT3 VCC3V3_2 nOUT3 R36 D 0.1u R141 NP R89 100 SP GND VCC3V3_2 VCC3V3_2 Close to SMA if long trace Close to SMA if long trace R72 SP C J66 R273 SP C25 0.1u R140 SP OUT4_P OUT4_P R279 SP C41 OUT3_P OUT4_POS Close to IC pins OUT4_NEG OUT4_POS R70 SP OUT4_NEG C26 OUT3_POS OUT3_NEG OUT4_N R274 150 R87 SP OUT3_NEG VCC3V3_2 VCC3V3_2 R48 SP C34 R51 SP VCC3V3_2 C40 C43 0.1u OUT1_P OUT1_POS OUT1_NEG J40 OUT1_P OUT1_POS R64 SP No Stub 0.1u OUT2_N OUT1_NEG C61 No Stub 0.1u OUT1_N J16 OUT2_N IN_APLL_P R110 133 B R84 SP J15 OUT2_POS OUT2_NEG R65 SP OUT2_P 0.1u OUT2_P OUT2_NEG R281 150 Close to SMA if long trace R47 SP J31 No Stub 0.1u J70 OUT3_N R280 150 J67 Close to SMA if long trace OUT2_POS C42 OUT3_N OUT4N R275 150 J69 OUT3_POS No Stub 0.1u IN_APLL_N R111 133 R53 150 C50 IN_APLL_POS 0.1u C51 R115 SP C OUT3_P 0.1u R54 150 J41 OUT1_N R85 150 R86 150 IN_APLL_POS B J33 R102 SP R103 SP IN_APLL_NEG 0.1u R112 82 GND IN_APLL_NEG R113 82 GND GND A A SMA's for input can be either END LAUNCH or STRAIGHT depends on which way save space. TBD during layout Title SCHEMATIC, 8V89316 EVB REV A Size Document Number Custom 8V89316_IO_Termination Date: 5 4 3 2 Friday, June 14, 2013 1 Rev 0.0 Sheet 3 of 5 5 4 1 OCXO_Power 4 M5626LF 12.8MHz DNC GND VCC OUT 2 J2 C48 0.1u U1 12M8_ TCXO OCXO_Power 9 10 C2 0.1u VCC DNC10 OCXO_Power OUT GND 5 4 C17 9 8 7 6 0025.000000 MHz JP9 R2 SP XO/SMA option OCXO_Power R9 100 0.1u R8 0 OSCI R5 SP 0.1u R152 1K R11 100 LD8 RED LED 5 NC6 1 NC1 GND 6 6 7 5 D- 6 D+ GND C 1 2 R188 4.7K C168 0.1u VCC2232_3V 3V3_USB 3 3V3_USB 4 USB PORT 2910 Stratum 3E OCXO C147 0.1u R77 27 U3 6 8 1 R78 27 7 2 R80 1.5K 5 1 43 XTIN 3V3OUT USBDM USBDP XTIN SI/WUA Y3 6MHz UNUSED0 UNUSED1 UNUSED2 UNUSED3 UNUSED4 UNUSED5 UNUSED6 UNUSED7 2 44 XTOUT C39 1u 4 SW2 33PF R74 10K C170 XTOUT RESET# 2 VCC2232 C169 TCK/SK TDI/DO TDO/DI TMS/CS GPIOL0 GPIOL1 GPIOL2 GPIOL3 GPIOH0 GPIOH1 GPIOH2 GPIOH3 RSTOUT# 1 VCC3V3_2 R156 10K 33PF 48 1 1 B R187 4.7K 14 31 NC2 VCCIOA VCCIOB VBUS 2 1 J3 SP 3 42 C10 0.1u OCXO 5 46 C9 0.1u 4 VCC VCC NC5 2 INPUT_SUPPLY RF_OUTPUT 1 3 C8 0.1u 2 OCXO_Power C7 10u VCC3V3_2 C166 0.01u R153 470 2 R7 R6 SP C C138 0.1u VCC2232 U2 TP1 C165 10u 2 C12 0.1u VCC_OCXO L9 BLM18BB221SN1 C167 0.1u R189 0 AVCC C171 1 L8 BLM18BB221SN1 X4 XTAL_IN 5 VCC3V3_2 D TCXO 0.1u NC5 NC1 VCC NC2 NC8 NC3 VC FILTER GND RF OUT XTAL_OUT XTAL_IN XTAL_OUT 2 NC10 1 2 3 4 XTAL_OUT XTAL_IN SP C15 10 U4 RTX5032 R3 0 Clocks and frequently switched signals should not be routed close to the crystals. Digital signals should not be routed directly under the crystal or XTALn_IN/OUT pins. Keep the crystal bond pads and trace width to the XTALn_IN/OUT pins as small as possible. All metal layers in the PCB are recommended to be removed under the XTALn_OUT ball, crystal pad and associated trace. It is recommended to protect crystal traces with ground traces and guard rings. R1 1 2 3 C3 0.1u R24 SP 1) 2) 3) 4) 5) 1 C1 10u DNC1 Tri-state_Enable NC2 NC7 DNC3 NC6 D 25MHz XTAL Interface (Place close to the DUT and Put xtals on same layer as BGA pads, shorter trace length, no stubs) 3 8 7 6 C47 10u 1 2 VCC3V3_2 SW_PUSHBUTTON UNUSED8 UNUSED9 UNUSED10 UNUSED11 EECS EESK EEDATA SI/WUB 24 23 22 21 20 19 17 16 R190 R191 SCL1 SDA1 R154 470 2 40 39 38 37 36 35 33 32 1 LD9 Green LED 3V3_USB R157 10K R13 USB to I2C SP R14 30 29 28 27 26 I2C_SCL I2C_SDA 3V3_USB 15 13 12 11 10 I2C_SCL I2C_SDA SP SP 1 U6 2 2 12.8MHz, TCXO or OCXO ( Place close to the DUT) 3 0 2 1 B JP6 SCL1 I2C_SCL SCL2 R158 10K VCC3V3_2 5 ft2232_chip 7 74HC14/SO 41 U7F JP7 14 PWREN# 9 18 25 34 TEST AGND 6 RST 45 14 U7C RST GND GND GND GND Header_3Pin 47 SDA1 I2C_SDA SDA2 R10 SCL1 0 13 12 7 74HC14/SO Header_3Pin VCC3V3_2 Indicator VCC3V3_2 C13 0.1u J68 14 LD1 1 3 5 7 9 SCL2 SDA2 U7D R79 T0_LOCK 9 T0_LOCK 7 8 74HC14/SO 2 4 6 8 10 1K Aardvark I2C/SPI Host Adapter A A Title SCHEMATIC, 8V89316 EVB REV A Size Custom Date: 5 4 3 2 Document Number 8V89316_Control Friday, June 14, 2013 1 Rev 0.0 Sheet 4 of 5 5 4 3 U11 VREG_LT1764AEQ_3.3 2 1 SHDN C180 R124 VCC5 C176 10u SP C178 0.1u SENSE R192 JP2 0 R129 5 C179 0.1u C174 47u C177 0.1u 1 (VCC3V3_1 is used for the 8V89316 DUT and VCC3V3_2 is for the rest of the board circuits. We are not suggesting a dedicated LDO for the 8V89316 with this reference design, this is just convenient for the test.) VCC3V3_2 4 3 VCC5 VCC5V VOUT GND VIN 2 VCC3V3_2 R139 SP LD5 470 0 C90 0.1u D1 J54 C91 47u CGRA4004-G U10 VREG_LT1764AEQ_3.3 2 5V 1 POWER_SOCKET D2 C92 C95 10u SP C96 0.1u VIN SHDN VOUT GND J55 1 2 3 R125 VCC3V3_1 JP1 0 D VCC3V3_1 4 R195 SENSE 5 C97 SPARE 3 D C93 470uF C94 47u C100 0.1u R136 SP LD6 (Place caps close to and accross power and ground pins) VDDA 470 VCC3V3_1 L2 JP5 C118 C129 8V89316 Analog Power VDDA C98 BLM18BB221SN1 0.1u CGRA4004-G C102 C116 0.1u 0.1u 0.1u R193 SP VCC_OCXO VCC_OCXO C99 SP C148 10u SP VSSA VCC_OCXO J58 C173 0.1u D4 CGRA4004-G C172 47u VDDD JP12 L7 BLM18BB221SN1 VDDD C115 0.1u C125 0.1u 8V89316 Digital Power C114 C108 0.1u C150 10u 0.1u R194 SP J57 VSSD VDDDO C JP13 GND L17 BLM18BB221SN1 C141 0.1u C142 0.1u C 8V89316 Digital Output Power VDDDO C144 0.1u C160 0.1u C145 10u R196 SP VSSDO JP14 L14 VDDAO VDDAO C133 0.1u C134 0.1u C140 0.1u C122 C153 10u 0.1u R197 SP 8V89316 Analog OUTPUT Power VSSAO VDDA1 VDDA C127 0.1u C126 0.01u VDDA2 VDDA C130 0.1u C128 0.01u B B A A Title SCHEMATIC, 8V89316 EVB REV A Size C Date: 5 4 3 2 Document Number Rev 0.0 Power/GND Sheet Friday, June 14, 2013 1 5 of 5