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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
Rev 2, 05-Sep-13
ACT8897
Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors
FEATURES
• Optimized for Samsung S5PC100, S5PC110 and
S5PV210 Processors
• Three Step-Down DC/DC Converters
• Four Low-Dropout Linear Regulators
• I2CTM Serial Interface
• Advanced Enable/Disable Sequencing Controller
• Minimal External Components
• Tiny 4×4mm TQFN44-32 Package
− 0.75mm Package Height
− Pb-Free and RoHS Compliant
GENERAL DESCRIPTION
The ACT8897 is a complete, cost effective, highly-
efficient ActivePMUTM power management solution,
optimized for the unique power, voltage-
sequencing, and control requirements of the
Samsung S5PC100, S5PC110 and S5PV210
processors.
This device features three step-down DC/DC
converters and four low-noise, low-dropout linear
regulators.
The three DC/DC converters utilize a high-
efficiency, fixed-frequency (2MHz), current-mode
PWM control architecture that requires a minimum
number of external components. Two DC/DCs are
capable of supplying up to 1100mA of output
current, while the third supports up to 1200mA. All
four low-dropout linear regulators are high-
performance, low-noise, regulators that supply up to
150mA, 150mA, 250mA, and 250mA, respectively.
The ACT8897 is available in a compact, Pb-Free
and RoHS-compliant TQFN44-32 package.
TYPICAL APPLICATION DIAGRAM
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
TABLE OF CONTENTS
General Information ..................................................................................................................................... p. 01
Functional Block Diagram ............................................................................................................................ p. 03
Ordering Information .................................................................................................................................... p. 04
Pin Configuration ......................................................................................................................................... p. 04
Pin Descriptions ........................................................................................................................................... p. 05
Absolute Maximum Ratings ......................................................................................................................... p. 07
I2C Interface Electrical Characteristics ........................................................................................................ p. 08
Global Register Map .................................................................................................................................... p. 09
Register and Bit Descriptions ...................................................................................................................... p. 10
System Control Electrical Characteristics .................................................................................................... p. 13
Step-Down DC/DC Electrical Characteristics .............................................................................................. p. 14
Low-Noise LDO Electrical Characteristics ................................................................................................... p. 15
Typical Performance Characteristics ........................................................................................................... p. 16
System control information .......................................................................................................................... p. 21
Interfacing with the Samsung S5PV210 .......................................................................................... p. 21
Control Signals ................................................................................................................................. p. 22
Push-Button Control ......................................................................................................................... p. 23
Control Sequences ........................................................................................................................... p. 23
Functional Description ................................................................................................................................. p. 26
I2C Interface ..................................................................................................................................... p. 26
Voltage Monitor and Interrupt ........................................................................................................... p. 26
Thermal Shutdown ........................................................................................................................... p. 26
Step-Down DC/DC Regulators .................................................................................................................... p. 27
General Description .......................................................................................................................... p. 27
100% Duty Cycle Operation ............................................................................................................. p. 27
Synchronous Rectification ................................................................................................................ p. 27
Soft-Start .......................................................................................................................................... p. 27
Compensation .................................................................................................................................. p. 27
Configuration Options ....................................................................................................................... p. 27
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 28
PCB Layout Considerations ............................................................................................................. p. 28
Low-Noise, Low-Dropout Linear Regulators ................................................................................................ p. 29
General Description .......................................................................................................................... p. 29
Output Current Limit ......................................................................................................................... p. 29
Compensation .................................................................................................................................. p. 29
Configuration Options ....................................................................................................................... p. 29
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 29
PCB Layout Considerations ............................................................................................................. p. 29
TQFN44-32 Package Outline and Dimensions ........................................................................................... p. 31
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
FUNCTIONAL BLOCK DIAGRAM
REG6
LDO
REG7
LDO
ACT8897
SDA
VP2
GP2
SW2
OUT2
OUT2
VP1
GP1
SW1
OUT1
OUT1
To Battery
OUT7
OUT6
REG5
LDO OUT5
OUT7
OUT6
OUT5
System
Control
nIRQ
REG4
LDO OUT4
OUT4
INL45
REFBP
Reference
VP3
GP3
SW3
OUT3
OUT3
GA
EP
To Battery
To Battery
To Battery
nPBSTAT
PWRHLD
PWREN
SCL
VSEL
OUT1
OUT1
nPBIN
PUSH BUTTON
Serial
Interface
nRSTO
OUT1
INL67 To Battery
To Battery
VDDREF
VDDREF
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
PIN CONFIGURATION
TOP VIEW
Thin - QFN (TQFN44-32)
ORDERING INFORMATION
PART NUMBER VOUT1 VOUT2/VSTBY2
VOUT3/VSTBY3 V
OUT4 V
OUT5 V
OUT6 V
OUT7 PACKAGE PINS
TEMPERATURE
RANGE
ACT8897Q4I1PQ-T 3.3V 1.3V/1.2V 1.35V/1.2V 1.2V 1.2V 1.2V 3.3V TQFN44-32 32 -40°C to +85°C
ACT8897Q4I11C-T 3.3V 1.1V/1.1V 1.25V/1.25V 1.1V 1.1V 1.1V 3.3V TQFN44-32 32 -40°C to +85°C
ACT8897Q4I106-T 1.8V 1.1V/1.1V 1.25V/1.25V 1.1V 1.1V 1.1V 3.3V TQFN44-32 32 -40°C to +85°C
: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity is 12,000 units.
: To select VSTBYx as a output regulation voltage of REGx, drive VSEL to a logic high. The VSTBYx can be set by software via I2C
interface, refer to appropriate sections of this datasheet for VSTBYx setting.
: ACT8897Q4I1PQ-T is optimized for S5PC100, ACT8897Q4I11C-T and ACT8897Q4I106-T are optimized for S5PC110 and
S5PV210.
REFBP
nPBIN
PWRHLD
VP3
SW3
GP3
nPBSTAT
nIRQ
nRSTO
VP2
SW2
GP2
SW1
VP1
NC2
GP1
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 OUT1
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
2 GA
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1,GP2 and GP3
together at a single point as close to the IC as possible.
3 OUT4
Output Voltage for REG4. Capable of delivering up to 150mA of output current. Connect a 1.5µF
ceramic capacitor from OUT4 to GA. The output is discharged to GA with 1.5k resistor when
disabled.
4 OUT5
Output Voltage for REG5. Capable of delivering up to 150mA of output current. Connect a 1.5µF
ceramic capacitor from OUT5 to GA. The output is discharged to GA with 1.5k resistor when
disabled.
5 INL45
Power Input for REG4 and REG5. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
6 INL67
Power Input for REG6 and REG7. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
7 OUT6
Output Voltage for REG6. Capable of delivering up to 250mA of output current. Connect a 2.2µF
ceramic capacitor from OUT6 to GA. The output is discharged to GA with 1.5k resistor when
disabled.
8 OUT7
Output Voltage for REG7. Capable of delivering up to 250mA of output current. Connect a 2.2µF
ceramic capacitor from OUT7 to GA. The output is discharged to GA with 1.5k resistor when
disabled.
9 nPBIN
Master Enable Input. Drive nPBIN to GA through a 50k resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section
for more information. nPBIN is internally pulled up to VVDDREF through a 35k resistor.
10 PWRHLD Power Hold Input. Refer to the Control Sequences section for more information.
11 nRSTO Active Low Reset Output. See the nRSTO Output section for more information.
12 nIRQ
Open-Drain Interrupt Output. nIRQ asserts any time an unmasked fault condition exists or an
interrupt occurs. See the nIRQ Output section for more information.
13 nPBSTAT
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.
14 GP3
Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to
the IC as possible.
15 SW3 Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
16 VP3
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17 PWREN Power Enable Input. Refer to the Control Sequences section for more information.
18 NC1 Connect NC1 to GA.
19 OUT3
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
20 VSEL
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Programming
section for more information.
21 SCL Clock Input for I2C Serial Interface.
22 SDA Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
PIN DESCRIPTIONS CONT’D
PIN NAME DESCRIPTION
25 NC2 Not Connected. Not internally connected.
26 VP2
Power Input for REG2 and System Control. Bypass to GP2 with a high quality ceramic capacitor
placed as close to the IC as possible.
27 SW2 Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
28 GP2
Power Ground for REG2. Connect GA, GP1,GP2 and GP3 together at a single point as close to
the IC as possible.
29 GP1
Power Ground for REG1. Connect GA, GP1,GP2 and GP3 together at a single point as close to
the IC as possible.
30 SW1 Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
31 VP1
Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close to
the IC as possible.
32 REFBP
Reference Bypass. Connect a 0.047F ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
EP EP Exposed Pad. Must be soldered to ground on PCB.
24 OUT2 Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
23 VDDREF
Power supply for the internal reference. Connect this pin directly to the system power supply.
Bypass VDDREF to GA with a 1µF capacitor placed as close to the IC as possible. Star
connection with VP1, VP2 and VP3 preferred.
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
ABSOLUTE MAXIMUM RATINGS
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
PARAMETER VALUE UNIT
VP1 to GP1, VP2 to GP2, VP3 to GP3 -0.3 to + 6 V
INL, VDDREF to GA -0.3 to + 6 V
nPBIN, SCL, SDA, REFBP, PWRHLD, PWREN, VSEL to GA -0.3 to (VVDDREF + 0.3) V
nRSTO, nIRQ, nPBSTAT to GA -0.3 to + 6 V
SW1, OUT1 to GP1 -0.3 to (VVP1 + 0.3) V
SW2, OUT2 to GP2 -0.3 to (VVP2 + 0.3) V
SW3, OUT3 to GP3 -0.3 to (VVP3 + 0.3) V
OUT4, OUT5, OUT6, OUT7 to GA -0.3 to (VINL + 0.3) V
GP1, GP2, GP3 to GA -0.3 to + 0.3 V
Junction to Ambient Thermal Resistance (JA) 27.5 °C/W
Operating Ambient Temperature -40 to 85 °C
Maximum Junction Temperature 125 °C
Storage Temperature -65 to 150 °C
Lead Temperature (Soldering, 10 sec) 300 °C
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
Figure 1:
I2C Compatible Serial Bus Timing
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
I2C INTERFACE ELECTRICAL CHARACTERISTICS
SDA
SCL
tST tSU
tHD tSP
tSCL
Start
condition
Stop
condition
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SCL, SDA Input Low VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC 0.35 V
SCL, SDA Input High VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC 1.55 V
SDA Leakage Current 1 µA
SDA Output Low IOL = 5mA 0.35 V
SCL Clock Period, tSCL 1.5 µs
SDA Data Setup Time, tSU 100 ns
SDA Data Hold Time, tHD 300 ns
Start Setup Time, tST For Start Condition 100 ns
Stop Setup Time, tSP For Stop Condition 100 ns
SCL Leakage Current
1 2 µA
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
GLOBAL REGISTER MAP
OUTPUT ADDRESS BITS
D7 D6 D5 D4 D3 D2 D1 D0
SYS 0x00 NAME TRST nSYSMODE nSYSLEVMSK nSYSSTAT SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]
DEFAULT 0 1 0 R 0 1 1 1
SYS 0x01 NAME Reserved Reserved Reserved Reserved SCRATCH SCRATCH SCRATCH SCRATCH
DEFAULT 0 0 0 0 0 0 0 0
REG1 0x20 NAME Reserved Reserved VSET1[5] VSET1[4] VSET1[3] VSET1[2] VSET1[1] VSET1[0]
DEFAULT 0 0 1 0 0 1 0 0
REG1 0x21 NAME Reserved Reserved VSET2[5] VSET2[4] VSET2[3] VSET2[2] VSET2[1] VSET2[0]
DEFAULT 0 0 1 1 1 0 0 1
REG1 0x22 NAME ON PHASE MODE DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 0 0 0 0 0 0 R
REG2 0x30 NAME Reserved Reserved VSET1[5] VSET1[4] VSET1[3] VSET1[2] VSET1[1] VSET1[0]
DEFAULT 0 0 0 1 1 0 0 0
REG2 0x31 NAME Reserved Reserved VSET2[5] VSET2[4] VSET2[3] VSET2[2] VSET2[1] VSET2[0]
DEFAULT 0 0 0 1 1 0 0 0
REG2 0x32 NAME ON PHASE MODE DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 0 0 0 1 1 0 R
REG3 0x40 NAME Reserved Reserved VSET1[5] VSET1[4] VSET1[3] VSET1[2] VSET1[1] VSET1[0]
DEFAULT 0 0 0 1 1 0 0 0
REG3 0x41 NAME Reserved Reserved VSET2[5] VSET2[4] VSET2[3] VSET2[2] VSET2[1] VSET2[0]
DEFAULT 0 0 0 1 1 0 0 0
REG3 0x42 NAME ON PWRSTAT MODE DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 0 0 0 1 1 0 R
REG4 0x50 NAME Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0]
DEFAULT 0 0 0 1 1 0 0 0
REG4 0x51 NAME ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 1 0 0 1 1 0 R
REG5 0x54 NAME Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0]
DEFAULT 0 0 0 1 1 0 0 0
REG5 0x55 NAME ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 1 0 0 0 0 0 R
REG6 0x60 NAME Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0]
DEFAULT 0 0 1 1 1 0 0 1
REG6 0x61 NAME ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 1 0 0 0 0 0 R
REG7 0x64 NAME Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0]
DEFAULT 0 0 1 1 1 0 0 1
REG7 0x65 NAME ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK
DEFAULT 0 1 0 0 0 0 0 R
: Default values of ACT8897Q4I11C-T.
2: Regulator turn-on delay bits. Automatically cleared to default values when the input power is removed or falls below the system
UVLO.
ACT8897
Rev 2, 05-Sep-13
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I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
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REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION
SYS 0x00 [7] TRST R/W
Reset Timer Setting. Defines the reset time-out threshold. Reset
time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
SYS 0x00 [6] nSYSMODE R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVDDREF falls
below the programmed SYSLEV threshold, 0: automatic
shutdown when VVDDREF falls below the programmed SYSLEV
threshold.
SYS 0x00 [5] nSYSLEVMSK R/W
System Voltage Level Interrupt Mask. Disabled interrupt by
default, set to 1 to enable this interrupt. See the Programmable
System Voltage Monitor section for more information
SYS 0x00 [4] nSYSSTAT R
System Voltage Status. Value is 1 when VVDDREF is lower than the
SYSLEV voltage threshold, value is 0 when VVDDREF is higher
than the system voltage detection threshold.
SYS 0x00 [3:0] SYSLEV R/W
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System V oltage Monitor
section for more information.
SYS 0x01 [7:4] - R/W Reserved.
SYS 0x01 [3:0] SCRATCH R/W
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
upon system shutdown.
REG1 0x20 [7:6] - R Reserved.
REG1 0x20 [5:0] VSET1 R/W
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information.
REG1 0x21 [7:6] - R Reserved.
REG1 0x21 [5:0] VSET2 R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Program ming section for more
information.
REG1 0x22 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1 0x22 [6] PHASE R/W
Regulator Phase Control. Set bit to 1 for regulator to operate
180° out of phase with the oscillator, clear bit to 0 for regulator to
operate in phase with the oscillator.
REG1 0x22 [5] MODE R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1 0x22 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1 0x22 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG1 0x22 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2 0x30 [7:6] - R
Reserved.
REG2 0x30 [5:0] VSET1 R/W
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information.
REG2 0x31 [7:6] - R Reserved.
REG2 0x31 [5:0] VSET2 R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Program ming section for more
information.
ACT8897
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I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
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REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION
REG2 0x32 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG2 0x32 [6] PHASE R/W
Regulator Phase Control. Set bit to 1 for regulator to operate
180° out of phase with the oscillator, clear bit to 0 for regulator
to operate in phase with the oscillator.
REG2 0x32 [5] MODE R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-
savings mode under light-load conditions.
REG2 0x32 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG2 0x32 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG2 0x32 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3 0x40 [7:6] - R Reserved.
REG3 0x40 [5:0] VSET1 R/W
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Progra m ming section for more
information.
REG3 0x41 [7:6] - R Reserved.
REG3 0x41 [5:0] VSET2 R/W
Secondary Output Voltage Selection. Valid when VSEL is
driven high. See the Output Voltage Program ming section for
more information.
REG3 0x42 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG3 0x42 [6] PWRSTAT R/W Configures regulator behavior with respect to the nPBIN input.
Set bit to 0 to enable regulator when nPBIN is asserted.
REG3 0x42 [5] MODE R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transition to power-
savings mode under light-load conditions.
REG3 0x42 [4:2] DELAY R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG3 0x42 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG3 0x42 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4 0x50 [7:6] - R Reserved.
REG4 0x50 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG4 0x51 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG4 0x51 [6] DIS R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5k when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG4 0x51 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG4 0x51 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG4 0x51 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG4 0x51 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
ACT8897
Rev 2, 05-Sep-13
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
Innovative PowerTM
Active-Semi Proprietary―For Authorized Recipients and Customers
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION
REG5 0x54 [7:6] - R Reserved.
REG5 0x54 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG5 0x55 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG5 0x55 [6] DIS R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5k when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG5 0x55 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG5 0x55 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG5 0x55 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG5 0x55 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG6 0x60 [7:6] - R Reserved.
REG6 0x60 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG6 0x61 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG6 0x61 [6] DIS R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5k when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG6 0x61 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG6 0x61 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG6 0x61 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG6 0x61 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7 0x64 [7:6] - R Reserved.
REG7 0x64 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG7 0x65 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG7 0x65 [6] DIS R/W
Output Discharge Control. When activated, discharges LDO
output to GA through 1.5k when in shutdown. Set bit to 1 to
enable output voltage discharge in shutdown, clear bit to 0 to
disable this function.
REG7 0x65 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG7 0x65 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG7 0x65 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG7 0x65 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
ACT8897
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SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Voltage Range 2.7 5.5 V
UVLO Threshold Voltage VVDDREF Rising 2.2 2.45 2.65 V
UVLO Hysteresis VVDDREF Falling 200 mV
Supply Current
REG1 and REG5 Enabled. REG2, REG3,
REG4, REG6 and REG7 Disabled 190
REG1, REG2, REG3, REG4 and REG5
Enabled. REG6 and REG7 Disabled 340
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 Enabled 420
Shutdown Supply Current All Regulators Disabled 1.5 3.0 µA
Oscillator Frequency 1.8 2 2.2 MHz
Logic High Input Voltage1 1.4 V
Logic Low Input Voltage 0.4 V
Leakage Current VnIRQ = VnRSTO = 4.2V 1 µA
Low Level Output Voltage2 I
SINK = 5mA 0.35 V
nRSTO Delay 260 ms
Thermal Shutdown Temperature Temperature rising 160 °C
Thermal Shutdown Hysteresis 20 °C
µA
: PWRHLD, PWREN, VSEL are logic inputs.
2: nPBSTAT, nIRQ, nRSTO are open drain outputs.
3: Typical value shown. Actual value may vary from 227.9ms to 291.2ms.
ACT8897
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STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Operating Voltage Range 2.7 5.5 V
UVLO Threshold Input Voltage Rising 2.5 2.6 2.7 V
UVLO Hysteresis Input Voltage Falling 100 mV
Quiescent Supply Current Regulator Enabled 65 90 µA
Shutdown Current VVP = 5.5V, Regulator Disabled 0 1 µA
Output Voltage Accuracy V
VOUT 1.2V, IOUT = 10mA -1% VNOM
1%
VOUT < 1.2V, IOUT = 10mA -2% VNOM
2%
Line Regulation VVP = Max(VNOM
1
+1, 3.2V) to 5.5V 0.15 %/V
Load Regulation IOUT = 10mA to IMAX2 0.0017 %/mA
Power Good Threshold VOUT Rising 93 %VNOM
Power Good Hysteresis VOUT Falling 2 %VNOM
Oscillator Frequency VOUT 20% of VNOM 1.8 2 2.2 MHz
VOUT = 0V 500 kHz
Soft-Start Period 400 µs
Minimum On-Time 75 ns
REG1
Maximum Output Current 1.1 A
Current Limit 1.55 1.80 2.05 A
PMOS On-Resistance ISW1 = -100mA 0.16
NMOS On-Resistance ISW1 = 100mA 0.16
SW1 Leakage Current VVP1 = 5.5V, VSW1 = 0 or 5.5V 0 1 µA
REG2
Maximum Output Current 1.1 A
Current Limit 1.55 1.80 2.05 A
PMOS On-Resistance ISW2 = -100mA 0.16
NMOS On-Resistance ISW2 = 100mA 0.16
SW2 Leakage Current VVP2 = 5.5V, VSW2 = 0 or 5.5V 0 1 µA
REG3
Maximum Output Current 1.2 A
Current Limit 1.55 1.80 2.05 A
PMOS On-Resistance ISW3 = -100mA 0.16
NMOS On-Resistance ISW3 = 100mA 0.16
SW3 Leakage Current VVP3 = 5.5V, VSW3 = 0 or 5.5V 0 1 µA
ACT8897
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LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT4 = COUT5 = 1.5µF, COUT6 = COUT7 = 2.2µF, LOWIQ[ ] = [0], TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating Voltage Range 2.5 5.5 V
Output Voltage Accuracy VOUT 1.2V, TA = 25°C, IOUT = 10mA -1% VNOM
2% V
VOUT < 1.2V, TA = 25°C, IOUT = 10mA -2% VNOM
4%
Line Regulation
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [0] 0.05
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [1] 0.5
Load Regulation IOUT = 1mA to IMAX2 0.08 V/A
Power Supply Rejection Ratio f = 1kHz, IOUT = 20mA, VOUT =1.2V 75 dB
f = 10kHz, IOUT = 20mA, VOUT =1.2V 65
Supply Current per Output
Regulator Enabled, LOWIQ[ ] = [0] 37 60
µA Regulator Enabled, LOWIQ[ ] = [1] 31 52
Regulator Disabled 0 1
Soft-Start Period VOUT = 2.9V 140 µs
Power Good Threshold VOUT Rising 89 %
Power Good Hysteresis VOUT Falling 3 %
Output Noise IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V 50 µVRMS
Discharge Resistance LDO Disabled, DIS[ ] = 1 1.5 k
REG4
Dropout Voltage IOUT = 80mA, VOUT > 3.1V 90 180 mV
Maximum Output Current 150 mA
Current Limit VOUT = 95% of regulation voltage 200 mA
Stable COUT4 Range 1.5 20 µF
REG5
Dropout Voltage IOUT = 80mA, VOUT > 3.1V 140 280 mV
Maximum Output Current 150 mA
Current Limit VOUT = 95% of regulation voltage 200 mA
Stable COUT5 Range 1.5 20 µF
REG6
Dropout Voltage IOUT = 120mA, VOUT > 3.1V 90 180 mV
Maximum Output Current 250 mA
Current Limit VOUT = 95% of regulation voltage 300 mA
Stable COUT6 Range 2.2 20 µF
REG7
Dropout Voltage IOUT = 120mA, VOUT > 3.1V 140 280 mV
Maximum Output Current 250 mA
Current Limit VOUT = 95% of regulation voltage 300 mA
Stable COUT7 Range 2.2 20 µF
mV/V
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher)
: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 30% (typ)
ACT8897
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TYPICAL PERFORMANCE CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
Temperature (°C)
-40 -20 0 20 40 60 80 100 120
ACT8897-001
VREF vs. Temperature
VREF (%)
ACT8897-002
Frequency vs. Temperature
Frequency (%)
Temperature (°C)
-40 -20 0 20 40 60 80 85
ACT8897-004
PWRHLD holding OUT1 & OUT5 after
nPBIN is released
CH1
CH1: VnPBIN, 2V/div
CH2: VOUT5, 1V/div
CH3: VOUT1, 2V/div
CH4: VPWRHLD, 2V/div
TIME: 100ms/div
CH2
CH3
CH4
Typical Oscillator Frequency=2MHz
Typical VREF=1.2V
0.84
0.42
0
-0.42
-0.84
2.5
2
1.5
1
0.5
0
-0.5
-1
ACT8897-003
PWREN Sequence
CH1
CH2
CH3
CH4
CH1: VPWREN, 5V/div
CH2: VOUT2, 1V/div
CH3: VOUT3, 1V/div
CH4: VOUT4, 1V/div
CH5: VOUT6, 1V/div
CH6: VOUT7, 2V/div
TIME: 4ms/div
CH5
CH6
nPBIN Startup Sequence
ACT8897-005
CH1: VnPBIN, 5V/div
CH2: VOUT5, 1V/div
CH3: VOUT2, 1V/div
CH4: VOUT1, 2V/div
CH5: VOUT6, 1V/div
CH6: VOUT7, 2V/div
TIME: 4ms/div
CH1
CH2
CH3
CH4
CH5
CH6
nPBIN Startup Sequence
ACT8897-006
CH1
CH2
CH3
CH4
CH1: VnPBIN, 5V/div
CH2: VOUT5, 1V/div
CH3: VOUT2, 1V/div
CH4: VOUT3, 1V/div
CH5: VOUT4, 1V/div
TIME: 2ms/div
CH5
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ACT8897-007
Push-Button Response (First Power-Up)
(TA = 25°C, unless otherwise specified.)
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
CH1
CH2
CH3
Manual Reset Response
CH1
CH2
CH3
ACT8897-008
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
CH3: VnRSTO, 2V/div
TIME: 100ms/div
nPBIN Resistor = 50k CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
CH3:VnRSTO , 2V/div
TIME: 100ms/div
nPBIN Resistor = 0
ACT8897-009
REG1 Efficiency vs. Output Current
Efficiency (%)
Output Current (mA)
1 10 100 1000
100
80
60
40
20
0
VOUT = 3.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
ACT8897-010
REG2 Efficiency vs. Output Current
100
80
60
40
20
0
Efficiency (%)
Output Current (mA)
1 10 100 1000
VOUT = 1.2V
VIN = 4.2V
VIN = 3.6V
VIN = 5.0V
ACT8897-011
REG3 Efficiency vs. Output Current
100
80
60
40
20
0
Efficiency (%)
Output Current (mA)
1 10 100 1000
VOUT = 1.35V VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
ACT8897
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(TA = 25°C, unless otherwise specified.)
Temperature (°C)
-40 -20 0 20 40 60 80 100 120
ACT8897-014
REG3 Output Voltage vs. Temperature
Output Voltage (V)
1.360
1.356
1.352
1.348
1.344
1.340
Temperature (°C)
-40 -20 0 20 40 60 80 100 120
ACT8897-012
REG1 Output Voltage vs. Temperature
Output Voltage (V)
VOUT3 = 1.35V
ILOAD = 100mA
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
Temperature (°C)
-40 -20 0 20 40 60 80 100 120
ACT8897-013
REG2 Output Voltage vs. Temperature
Output Voltage (V)
VOUT2 = 1.3V
ILOAD = 100mA
1.310
1.306
1.302
1.298
1.294
1.290
VOUT1 = 3.3V
ILOAD = 100mA
3.310
3.306
3.302
3.298
3.294
3.290
ACT8897-015
REG1, 2, 3 MOSFET Resistance
RDSON (m)
Input Voltage (V)
3.0 3.5 4.0 4.5 5.0 5.5
300
250
200
150
100
50
0
350
ILOAD = 100mA
PMOS NMOS
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Output Voltage vs. Output Current
(TA = 25°C, unless otherwise specified.)
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
ACT8897-016
3.10
2.90
2.70
2.50
2.30
2.10
3.30
3.50
3.70
Output Voltage (V)
Output Current (mA)
0 50 100 150 200 250 300
ACT8897-017
1.30
1.10
0.90
0.70
0.50
0.30
1.50
1.70
1.90
Output Voltage (V)
Output Current (mA)
0 50 100 150 200 250 300
REG6
Output Voltage vs. Output Current
REG7
Output Current (mA)
0 20 40 60 80 100 120 140 160
ACT8897-019
Dropout Voltage vs. Output Current
Dropout Voltage (mV)
160
100
80
60
40
20
0
140
120
VIN = 3.3V
REG4
ACT8897-020
Dropout Voltage vs. Output Current
Dropout Voltage (mV)
250
200
150
100
50
0
VIN = 3.3V
REG5
Output Current (mA)
0 20 40 60 80 100 120 140 160
Output Current (mA)
0 50 100 150 200 250 300
ACT8897-021
Dropout Voltage vs. Output Current
Dropout Voltage (mV)
180
100
80
60
40
20
0
160
140
120
REG6
VIN = 3.3V
Output Voltage vs. Output Current
ACT8897-018
1.300
1.260
1.220
1.180
1.140
1.100
Output Voltage (V)
Output Current (mA)
0 20 40 60 80
100 160 140
120
REG4, REG5
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ESR ()
ACT8897-024
Region of Stable COUT ESR vs. Output Current
1
0.1
0.01
Output Current (mA)
0 50 100 250 200 150
Stable ESR
Temperature (°C)
-40 -20 0 20 40 60 80 100 120
ACT8897-023
Output Voltage vs. Temperature
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
4.00
Output Voltage (V)
REG4, REG5, REG6
REG7
(TA = 25°C, unless otherwise specified.)
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
ACT8897-025
LDO Output Voltage Noise
CH1
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
Output Current (mA)
0 50 100 150 200 250 300
ACT8897-022
Dropout Voltage vs. Output Current
VIN = 3.3V
REG7
300
250
200
150
100
50
0
ACT8897
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The ACT8897 is optimized for use in applications
using the S5PC100, S5PC110 and S5PV210
processors, supporting both the power domains as
well as the signal interface for these processors.
The following paragraphs describe how to design
ACT8897 with S5PV210 Processor, but the design
guidelines are directly applicable to S5PC100 and
S5PC110 as well.
While the ACT8897 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8897 pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
the ACT8897 pin names and the Samsung
processor pin names are provided. When this is
done, the S5PV210 pin names are located after the
ACT8897 pin names, and are italicized and located
inside parentheses. For example, PWREN
(XPWRRGTON) refers to the logic signal applied to
the ACT8897's PWREN input, identifying that it is
driven from the S5PV210's XPWRRGTON output.
Likewise, OUT1 (VDD_IO) refers to ACT8897's
OUT1 pin, identifying that it is connected to the
S5PV210's VDD_IO power domain.
SYSTEM CONTROL INFORMATION
Interfacing with the Samsung S5PC100, S5PC110 and S5PV210 Processors
Table 2:
ACT8897 and Samsung S5PV210 Power Domains
POWER DOMAIN ACT8897 CHANNEL TYPE DEFAULT VOLTAGE CURRENT CAPABILITY
VDD_IO REG1 DC/DC 3.3V 1100mA
VDD_INT REG2 DC/DC 1.1V 1100mA
VDD_ARM REG3 DC/DC 1.25V/1.25V 1200mA
VDD_xPLL REG4 LDO 1.1V 150mA
VDD_Alive REG5 LDO 1.1V 150mA
VDD_UOTG_D REG6 LDO 1.1V 250mA
VDD_UOTG_A REG7 LDO 3.3V 250mA
Table 3:
ACT8897 and Samsung S5PV210 Power Modes
POWER
MODE CONTROL STATE POWER DOMAIN STATE QUIESCENT
CURRENT
ALL ON PWRHLD is asserted, PWREN is asserted REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all on 420µA
NORMAL
PWRHLD is asserted, PWREN is asserted,
REG6 and REG7 are disabled after system
boots up.
REG1, REG2, REG3, REG4 and
REG5 are on. REG6 and REG7 are off 340µA
SLEEP PWRHLD is asserted, PWREN is de-asserted,
REG6 and REG7 are disabled default.
REG1 and REG5 are on. REG2, REG3,
REG4, REG6 and REG7 are off 190µA
ALL OFF PWRHLD is de-asserted, PWREN is
de-asserted
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all off <18µA
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Table 5:
Control Pins
PIN NAME OUTPUT
nPBIN REG1, REG2, REG3, REG4, REG5, REG6, REG7
PWRHLD REG1, REG5
PWREN REG2, REG3, REG4, REG6, REG7
Control Signals
Enable Inputs
The ACT8897 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input. Refer to Table 5 for a
description of which channels are controlled by
each input.
nPBIN Multi-Function Input
ACT8897 features the nPBIN multi-function pin,
which combines system enable/disable control with
a hardware reset function. Select either of the two
pin functions by asserting this pin, either through a
direct connection to GA, or through a 50k resistor
to GA, as shown in Figure 2.
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5k).
When this occurs, nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset timeout period expires.
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT1) through a 10k or greater resistor.
Figure 2:
nPBIN Input
ACT8897 DIRECTION SAMSUNG S5PV210
PWREN XPWRRGTON
SCL Xi2cSCL[0]
SDA Xi2cSDA[0]
VSEL DVS_GPIO
nRSTO XnRESET
nIRQ XEINT0
nPBSTAT XEINT1
PWRHLD Power hold GPIO
Table 4:
ACT8897 and Samsung S5PV210 Signal Interface
1: Optional connection for DVS control.
2, : Typical connections shown, actual connections may vary.
: Optional connection for power hold control.
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nRSTO Output
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset timeout period expires after
OUT5 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset timeout
period expires.
Connect a 10k or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT1).
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10k or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8897's functions support interrupt-
generation as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Push-Button Control
The ACT8897 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWREN or PWRHLD) before nPBIN is de-asserted.
If the microprocessor is unable to complete its
power-up routine successfully before the user lets
the push-button go off, the ACT8897 automatically
shuts the system down. This provides protection
against accidental or momentary assertions of the
push-button. If desired, longer “push-and-hold”
times can be easily implemented by simply adding
an additional time delay before asserting PWREN
or PWRHLD.
Control Sequences
The ACT8897 features a variety of control
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of the
Samsung S5PV210 processor.
Enabling/Disabling Sequence
A typical enable sequence initiates as a result of
asserting nPBIN, and begins by enabling REG5.
When REG5 reaches its power-OK threshold,
nRSTO is asserted low, resetting the
microprocessor. REG2, REG3 and REG4 are
enabled after REG5 reaches its power-OK
threshold for 8ms. When REG2 reaches its power-
OK threshold for 8ms, REG1 and REG6 are
enabled. When REG2 reaches its power-OK
threshold for 16ms, REG7 is enabled. If REG5 is
above its power-OK threshold when the reset timer
expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence.
During the boot sequence, the microprocessor must
assert PWRHLD, holding REG1 and REG5, and
assert PWREN(XPWRRGTON), holding REG2,
REG3, REG4, REG6 and REG7 to ensure that the
system remains powered after nPBIN is released.
REG6 and REG7 can also be enabled/disabled via
I2C after microprocessor completes its boot
sequence.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as either PWRHLD or PWREN are
asserted high. If the processor does not assert
PWRHLD or PWREN(XPWRRGTON) before the
user releases the push-button, the boot-up
sequence is terminated and all regulators are
disabled. This provides protection against "false-
enable", when the pushbutton is accidentally
depressed, and also ensures that the system
remains enabled only if the processor successfully
completes the boot-up sequence. To disable REG6
(or REG7) via I2C after the power-up, the software
needs to set register bit REG6.ON[ ] (or REG7.ON[
]) to “1” first, then set it back to “0” to turn off the
regulator.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before the processor finally de-asserts PWRHLD,
which disables REG1 and REG5 after push-button
is released. Since the processor loses power of
VDD_IO and VDD_Alive, it automatically de-asserts
PWREN (XPWRRGTON), and hence shuts the
system down by disabling REG2, REG3, REG4,
REG6 and REG7.
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SLEEP Mode Sequence
The ACT8897 supports Samsung S5PC100,
S5PC110 and S5PV210 processors’ SLEEP mode
operation. Once a successful power-up routine has
been completed, SLEEP mode may be initiated
through a variety of software-controlled
mechanisms.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts the nPBIN input,
which asserts the nPBSTAT output, which
interrupts the processor. In response to this
interrupt the processor should de-assert
PWREN(XPWRRGTON), disabling REG2, REG3,
REG4, REG6 and REG7. PWRHLD should remain
asserted during SLEEP mode so that REG1 and
REG5 remain enabled.
Waking up from SLEEP mode is typically initiated
when the user presses the push-button again,
which enables REG2, REG3, REG4, REG6 and
REG7 and asserts nPBSTAT. Processors should
respond by asserting PWREN(XPWRRGTON),
which holds REG2, REG3, REG4, REG6 and REG7
so that normal operation may resume. An external
interrupt , for instance a RTC interrupt, can also
initiate a wake up sequence. When an external
interrupt is sent to the processor, the processor
should response by getting itself ready to wake up
from SLEEP mode first, then assert
PWREN(XPWRRGTON), which enables REG2,
REG3, REG4, REG6 and REG7 so that the normal
operation may resume.
Figure 3:
Enable/Disable Sequence
ACT8897
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Figure 4:
Sleep Mode and Wake up Sequence (from Push Button)
Figure 5:
Sleep Mode and Wake up Sequence (from External Interrupt)
ACT8897
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I2C Interface
The ACT8897 features an I2C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8897, and I2C read-byte commands are used to
read the ACT8897’s internal registers. The ACT8897
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a read-
operation or a write-operation, [1011011x].
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
Voltage Monitor and Interrupt
Programmable System Voltage Monitor
The ACT8897 features a programmable system-
voltage monitor, which monitors the voltage at
VDDREF and compares it to a programmable
threshold voltage. The programmable voltage
threshold is programmed by SYSLEV[3:0], as shown
in Table 6.
SYSLEV[ ] is set to 3.0V by default. There is a
200mV rising hysteresis on SYSLEV[ ] threshold
such that VVDDREF needs to be 3.2V(typ) or higher in
order to power up the IC.
The nSYSSTAT[-] bit reflects the output of an
internal voltage comparator that monitors VDDREF
relative to the SYSLEV[-] voltage threshold, the
value of nSYSTAT[-] = 1 when VVDDREF is lower than
the SYSLEV[-] voltage threshold, and nSYSTAT[-] =
0 when VVDDREF is higher than the SYSLEV[-] voltage
threshold. Note that the SYSLEV[-] voltage threshold
is defined for falling voltages, and that the
comparator produces about 200mV of hysteresis at
VDDREF. As a result, once VVDDREF falls below the
SYSLEV threshold, its voltage must increase by
more than about 200mV to clear that condition.
After the IC is powered up, the ACT8897 responds in
one of two ways when the voltage at VDDREF falls
below the SYSLEV[-] voltage threshold:
1) If nSYSMODE[-] = 1 (default case), when system
volt a g e lev e l i nter r u p t is u n m asked
(nSYSLEVMSK[ ]=1) and VVDDREF falls below the
programmable threshold, the ACT8897 asserts
nIRQ, providing a software “under-voltage alarm”.
The response to this interrupt is controlled by the
CPU, but will typically initiate a controlled shutdown
sequence either or alert the user that the battery is
low. In this case the interrupt is cleared when
VVDDREF rises up again above the SYSLEV rising
threshold and nSYSSTAT[-] is read via I2C.
2) If nSYSMODE[-] = 0, when VVDDREF falls below the
programmable threshold the ACT8897 shuts down,
immediately disabling all regulators. This option is
useful for implementing a programmable “under-
voltage lockout” function that forces the system off
when the battery voltage falls below the SYSLEV
threshold voltage. Since this option does not support
a controlled shutdown sequence, it is generally used
as a "fail-safe" to shut the system down when the
battery voltage is too low.
Table 6:
SYSLEV Falling Threshold
Thermal Shutdown
The ACT8897 integrates thermal shutdown
protection circuitry to prevent damage resulting from
excessive thermal stress, as may be encountered
under fault conditions. This circuitry disables all
regulators if the ACT8897 die temperature exceeds
160°C, and prevents the regulators from being
enabled until the IC temperature drops by 20°C (typ).
SYSLEV[3:0] SYSLEV Falling Threshold
(Hysteresis = 200mV)
0000 2.3
0001 2.4
0010 2.5
0011 2.6
0100 2.7
0101 2.8
0110 2.9
0111 3.0
1000 3.1
1001 3.2
1010 3.3
1011 3.4
1100 3.5
1101 3.6
1110 3.7
1111 3.8
FUNCTIONAL DESCRIPTION
ACT8897
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General Description
The ACT8897 features three synchronous, fixed-
frequency, current-mode PWM step down converters
that achieve peak efficiencies of up to 97%. REG1
and REG2 are capable of supplying up to 1100mA of
output current, while REG3 supports up to 1200mA.
These regulators operate with a fixed frequency of
2MHz, minimizing noise in sensitive applications and
allowing the use of small external components.
100% Duty Cycle Operation
Each regulator is capable of operating at up to 100%
duty cycle. During 100% duty-cycle operation, the
high-side power MOSFET is held on continuously,
providing a direct connection from the input to the
output (through the inductor), ensuring the lowest
possible dropout voltage in battery powered
applications.
Synchronous Rectification
REG1, REG2, and REG3 each feature integrated n-
channel synchronous rectifiers, maximizing efficiency
and minimizing the total solution size and cost by
eliminating the need for external rectifiers.
Soft-Start
When enabled, each output voltages tracks an
internal 400s soft-start ramp, minimizing input
current during startup and allowing each regulator to
power up in a smooth, monotonic manner that is
independent of output load conditions.
Compensation
Each buck regulator utilizes current-mode control and
a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over its full
operating range. No compensation design is
required; simply follow a few simple guidelines
described below when choosing external
components.
Input Capacitor Selection
The input capacitor reduces peak currents and noise
induced upon the voltage source. A 4.7F ceramic
capacitor is recommended for each regulator in most
applications.
Output Capacitor Selection
For most applications, 22F ceramic output
capacitors are recommended for REG1, REG2 and
REG3.
Despite the advantages of ceramic capacitors, care
must be taken during the design process to ensure
stable operation over the full operating voltage and
temperature range. Ceramic capacitors are available
in a variety of dielectrics, each of which exhibits
different characteristics that can greatly affect
performance over their temperature and voltage
ranges.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
Inductor Selection
REG1, REG2, and REG3 utilize current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. These devices were optimized for
operation with 2.2H inductors, although inductors in
the 1.5H to 3.3H range can be used. Choose an
inductor with a low DC-resistance, and avoid inductor
saturation by choosing inductors with DC ratings that
exceed the maximum output current by at least 30%.
Configuration Options
Output Voltage Programming
By default, each regulator powers up and regulates to
its default output voltage. Output voltage is selectable
by setting VSEL pin that when VSEL is low, output
voltage is programmed by VSET1[-] bits, and when
VSEL is high, output voltage is programmed by
VSET2[-] bits. However, once the system is enabled,
each regulator's output voltage may be independently
programmed to a different value, typically in order to
minimize the power consumption of the
microprocessor during some operating modes.
Program the output voltages via the I2C serial
interface by writing to the regulator's VSET1[-]
register if VSEL is low or VSET2[-] register if VSEL is
high as shown in Table 8.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit. The regulator accept rising or
falling edge of ON[ ] bit as on/off signal. To enable
the regulator, clear ON[ ] to 0 first then set to 1. To
disable the regulator, set ON[ ] to 1 first then clear it
to 0.
STEP-DOWN DC/DC REGULATORS
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REG1, REG2, REG3 Turn-on Delay
Each of REG1, REG2 and REG3 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 7.
Table 7:
REGx/DELAY[ ] Turn-On Delay
Operating Mode
By default, REG1, REG2, and REG3 each operate in
fixed-frequency PWM mode at medium to heavy
loads, while automatically transitioning to a
proprietary power-saving mode at light loads in order
to maximize standby battery life. In applications
where low noise is critical, force fixed-frequency
PWM operation across the entire load current range,
at the expense of light-load efficiency, by setting the
MODE[ ] bit to 1.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the power-
OK threshold, typically 7% below the programmed
regulation voltage, that regulator's OK[ ] bit will be 0.
If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8897
will interrupt the processor if that DC/DC's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
the OK[ ] bit has been read via I2C.
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can
result in instability or regulation errors.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator's power
loop should be connected at a single point in a star-
ground configuration, and this point should be
connected to the backside ground plane with multiple
via. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using
multiple via to achieve low electrical and thermal
resistance.
REGx/VSET[2:0] 000 001 010 011 100 101 110 111
000 0.600 0.800 1.000 1.200 1.600 2.000 2.400 3.200
001 0.625 0.825 1.025 1.250 1.650 2.050 2.500 3.300
010 0.650 0.850 1.050 1.300 1.700 2.100 2.600 3.400
011 0.675 0.875 1.075 1.350 1.750 2.150 2.700 3.500
100 0.700 0.900 1.100 1.400 1.800 2.200 2.800 3.600
101 0.725 0.925 1.125 1.450 1.850 2.250 2.900 3.700
110 0.750 0.950 1.150 1.500 1.900 2.300 3.000 3.800
111 0.775 0.975 1.175 1.550 1.950 2.350 3.100 3.900
REGx/VSET[5:3]
Table 8:
REGx/VSET[ ] Output Voltage Setting
DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY
0 0 0 0 ms
0 0 1 2 ms
0 1 0 4 ms
0 1 1 8 ms
1 0 0 16 ms
1 0 1 32 ms
1 1 0 64 ms
1 1 1 128 ms
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General Description
REG4, REG5, REG6, and REG7 are low-noise,
low-dropout linear regulators (LDOs) that supply up
to 150mA, 150mA, 250mA, and 250mA,
respectively. Each LDO has been optimized to
achieve low noise and high-PSRR, achieving more
than 65dB PSRR at frequencies up to 10kHz.
Output Current Limit
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Input Capacitor Selection
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1F. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Output Capacitor Selection
Each LDO requires a small ceramic output
capacitor for stability. Capacitance value is 1.5F
for REG4 and REG5, 2.2F for REG6 and REG7.
For best performance, each output capacitor should
be connected directly between the output and GA
pins, as close to the output as possible, and with a
short, direct connection. High quality ceramic
capacitors such as X7R and X5R dielectric types
are strongly recommended.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 8.
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit. The regulator accept rising
or falling edge of ON[ ] bit as on/off signal. To
enable the regulator, clear ON[ ] to 0 first then set to
1. To disable the regulator, set ON[ ] to 1 first then
clear it to 0.
REG4, REG5, REG6, REG7 Turn-on Delay
Each of REG4, REG5, REG6 and REG7 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 7.
Output Discharge
Each of the ACT8897’s LDOs features an optional
output discharge function, which discharges the
output to ground through a 1.5k resistance when
the LDO is disabled. This feature may be enabled
or disabled by setting DIS[-] via; set DIS[-] to 1 to
enable this function, clear DIS[-] to 0 to disable it.
Low-Power Mode
Each of ACT8897's LDOs features a LOWIQ[-] bit
which, when set to 1, reduces the LDO's quiescent
current by about 16%, saving power and extending
battery lifetime.
OK[ ] and Output Fault Interrupt
Each LDO features a power-OK status bit that can
be read by the system microprocessor via the
interface. If an output voltage is lower than the
power-OK threshold, typically 11% below the
programmed regulation voltage, the value of that
regulator's OK[-] bit will be 0.
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8897
will interrupt the processor if that LDO's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
the OK[-] bit has been read via I2C.
PCB Layout Considerations
PCB Layout Considerations The ACT8897’s LDOs
provide good DC, AC, and noise performance over
a wide range of operating conditions, and are
relatively insensitive to layout considerations. When
designing a PCB, however, careful layout is
necessary to prevent other circuitry from degrading
LDO performance.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
ACT8897
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nodes of the DC/DCs.
REFBP is a filtered reference noise, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
ACT8897
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Innovative PowerTM
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TQFN44-32 PACKAGE OUTLINE AND DIMENSIONS
A3
D
E
e
b
L
E/2
D2
E2
D/2
A
A1
R
SYMBOL
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN MAX MIN MAX
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.200 0.008
b 0.150 0.250 0.006 0.010
D 4.000 TYP 0.158 TYP
E 4.000 TYP
D2 2.550 2.800 0.100 0.110
E2 2.550 2.800 0.100 0.110
e 0.400 TYP 0.016 TYP
L 0.250 0.450 0.010 0.018
R 0.250 0.010
0.158 TYP
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for th eir applicatio ns. Active-Se mi products are not inten ded or aut horized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. F or more info rmation on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
