A5989 Bipolar Stepper and High-Current DC Motor Driver FEATURES AND BENEFITS DESCRIPTION * * * * * * * * * * * The A5989 is designed to operate at voltages up to 40V while driving one bipolar stepper motor at currents up to 1.6A, and one DC motor at currents up to 3.2A. The A5989 includes a fixed off-time pulse-width modulation (PWM) regulator for current control. The stepper motor driver features dual 2-bit nonlinear DACs (digital-to-analog converters) that enable control in full, half, and quarter steps. The DC motor is controlled using standard PHASE and ENABLE signals. Fast or slow current decay is selected via the MODE pin. The PWM current regulator uses the AllegroTM patented mixed decay mode for reduced audible motor noise, increased step accuracy, and reduced power dissipation. 40 V output rating 3.2 A DC motor driver 1.6A bipolar stepper driver Synchronous rectification Internal undervoltage lockout (UVLO) Thermal shutdown circuitry Crossover-current protection Very thin profile QFN package Overcurrent protection Low-power sleep mode 3.3 and 5V compatible logic supply Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. PACKAGE: Protection features include thermal shutdown with hysteresis, undervoltage lockout (UVLO), crossover-current and shortcircuit protection. Special power-up sequencing is not required. 36-pin QFN with exposed thermal pad 0.90 mm nominal height (suffix EV) The A5989 is supplied in a leadless 6mm x 6mm x 0.9mm, 36-pin QFN package with exposed power tab for enhanced thermal performance. The package is lead (Pb) free, with 100% matte-tin leadframe plating. Not to scale 0.1 F 50 V CP1 0.1 F 50 V CP2 100 F 50 V VCP VBB 0.22 F 50 V VBB SLEEPn OUT1A PHASE1 SENSE1 OUT1B I01 Microcontroller or Controller Logic A5989 I11 OUT2A PHASE2 OUT2B I02 SENSE2 I12 PHASE3 OUT3A ENABLE OUT3A MODE OUT3B VREF1 OUT3B VREF2 SENSE3 VREF3 GND GND SENSE3 Figure 1:Typical Application Circuit A5989-DS, Rev. 4 MCO-0000346 February 20, 2020 A5989 Bipolar Stepper and High-Current DC Motor Driver SELECTION GUIDE Part Number Packing A5989GEVTR-T 1500 pieces per reel ABSOLUTE MAXIMUM RATINGS Characteristic Load Supply Voltage Symbol VBB Output Current [1] IOUT Logic Input Voltage Range VIN SENSEx Pin Voltage VREFx Pin Voltage Operating Temperature Range Junction Temperature Storage Temperature Range [1] Notes VSENSEx Stepper motor driver, continuous DC motor driver, continuous Pulsed tw < 1 s Rating Units -0.5 to 40 V 1.6 A 3.2 A -0.3 to 7 V 0.5 V 2.5 V 2.5 V -40 to 105 C TJ(max) 150 C Tstg -55 to 150 C VREFx TA Range G May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a Junction Temperature of 150C. THERMAL CHARACTERISTICS: May require derating at maximum conditions Package Thermal Resistance Symbol RJA Test Conditions EV package, 4-layer PCB based on JEDEC standard JESD51-5 Min. Units 27 C/W Power Dissipation versus Ambient Temperature 5500 5000 4500 4000 Power Dissipation, PD (mW) Characteristic 3500 3000 2500 2000 1500 EV Package 4-layer PCB (RJA = 27 C/W) 1000 500 0 25 50 75 100 125 Temperature (C) 150 175 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A5989 Bipolar Stepper and High-Current DC Motor Driver FUNCTIONAL BLOCK DIAGRAM 0.1 F 50 V 0.1 F 50 V SLEEPn DMOS Full Bridge 1 OSC CHARGE PUMP 0.22 F 50 V To VBB2 VBB VBB VCP CP2 CP1 100 F 50 V VBB1 VCP OUT1A PHASE1 OUT1B I01 I11 Control Logic Stepper Motor PHASE2 DMOS Full Bridge 2 I12 RS1 VBB1 - Sense1 3 PWM Latch BLANKING + VREF1 SENSE1 GATE DRIVE I02 OUT2A 3 + VREF2 PWM Latch BLANKING - Sense 2 OUT2B VCP PHASE3 Control Logic DC Motor ENABLE MODE Sense 2 - OUT3A OUT3A DMOS Full Bridge 3 PWM Latch BLANKING + 3 OUT3B OUT3B SENSE3 RS3 GND GND NC NC NC SENSE3 NC VREF3 RS2 Sense 3 GATE DRIVE Sense 3 SENSE2 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A5989 Bipolar Stepper and High-Current DC Motor Driver ELECTRICAL CHARACTERISTICS [1]: Valid at TA = 25C, VBB = 40 V, unless otherwise noted Characteristics Load Supply Voltage Range Symbol VBB Output On-Resistance (DC Motor Driver) RDS(on)DC Output On-Resistance (Stepper Motor Driver) RDS(on)st Vf, Outputs Test Conditions Operating IDSS VBB Supply Current Output Driver Slew Rate IBB SROUT Typ. [2] Max. Units 8 - 40 V Source driver, IOUT = -1.2 A, TJ = 25C - 250 300 m Sink driver, IOUT = 1.2 A, TJ = 25C - 240 300 m Source driver, IOUT = -1.2 A, TJ = 25C - 500 600 m Sink driver, IOUT = 1.2 A, TJ = 25C - 480 600 m IOUT = 1.2 A Output Leakage Min. Outputs, VOUT = 0 to VBB IOUT = 0 mA, outputs on, fPWM = 50 kHz, duty cycle = 50% - - 1.2 V -20 - 20 A - - 23 mA Outputs off - 12.7 15 mA Sleep mode -10 <1 10 A 10% to 90% 50 100 150 ns 2 - - V Control Logic Logic Input Voltage Logic Input Current Input Hysteresis Sleep Rising Threshold Sleep Falling Threshold Sleep Hysteresis Sleep Input Current Propagation Delay Times VIN(1) - - 0.8 V -20 <1 20 A Vhys 150 300 500 mV VSLEEPn(r) 2.5 2.7 2.95 V VIN(0) IIN VIN = 0 to 5 V VSLEEPn(f) - 2.4 - V VSLEEPn(hys) 250 325 450 mV A - 100 150 PWM change to source on 550 700 1000 ns PWM change to source off 35 - 450 ns PWM change to sink on 550 700 1000 ns PWM change to sink off 35 - 450 ns ISLEEPn tpd tCD 250 425 1000 ns Blank Time (DC Motor Driver) tBLANKdc 2.5 3.2 4 s Blank Time (Stepper Motor Driver) tBLANKst 0.7 1 1.3 s 0 - 1.5 V Crossover Delay VREFx Pin Input Voltage Range VREFx Pin Reference Input Current Current Trip-Level Error[3] VREFx IREF VERR Operating VREF = 1.5V - - 1 A VREF = 1.5V, phase current = 100% -5 - 5 % VREF = 1.5V, phase current = 67% -5 - 5 % VREF = 1.5V, phase current = 33% -15 - 15 % Continued on the next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A5989 Bipolar Stepper and High-Current DC Motor Driver ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TA = 25C, VBB = 40 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. [2] Max. Units 7.3 7.6 7.9 V 400 500 600 mV 1.6 - - A Protection Circuits VBB UVLO Threshold VUV(VBB) VBB Hysteresis VUV(VBB)hys IOVP(STEP) Overcurrent Protection Threshold Thermal Shutdown Hysteresis Stepper driver 3.2 - - A TJTSD 155 165 175 C TJTSDhys - 15 - C IOVP(DC) Thermal Shutdown Temperature [1] For VBB rising DC driver input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. [2] Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. [3] V ERR = [(VREF/3) - VSENSE] / (VREF/3). DC Control Logic PHASE ENABLE MODE 3 x VS > VREF OUTA OUTB 1 1 1 false H L Function 1 1 0 false H L Forward (fast decay SR) 0 1 1 false L H Reverse (slow decay SR) Forward (slow decay SR) 0 1 0 false L H Reverse (fast decay SR) X 0 1 X L L Brake (slow decay SR) 1 0 0 X L H Fast decay SR* 0 0 0 X H L Fast decay SR* X 1 1 true L L OCL chop / slow decay SR 1 1 0 true L H OCL chop / fast decay SR* 0 1 0 true H L OCL chop / fast decay SR* * To prevent reversal of current during fast decay SR - the outputs will go to the high-impedance state as the current gets near zero. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A5989 Bipolar Stepper and High-Current DC Motor Driver FUNCTIONAL DESCRIPTION Device Operation Control Logic The A5989 is designed to operate one DC motor and one bipolar stepper motor. The currents in each of the full bridges, all N-channel DMOS, are regulated with fixed off-time pulse-widthmodulated (PWM) control circuitry. The peak current in each full bridge is set by the value of an external current sense resistor, RSx, and a reference voltage, VREFx. Stepper motor communication is implemented via industry standard I1, I0, and PHASE interface. This communication logic allows for full-, half-, and quarter-step modes. Each bridge also has an independent VREF input so higher resolution step modes can be programmed by dynamically changing the voltage on the corresponding VREFx pin. The DC motor is controlled using standard PHASE, ENABLE communication. Fast or slow current decay during the off-time is selected via the MODE pin. Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a user-specified value, ITRIP. Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RSx. When the voltage across the current sense resistor equals the voltage on the VREFx pin, the current sense comparator resets the PWM latch, which turns off the source driver. The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITripMax = VREF / (3 x RS) The stepper motor outputs will define each current step as a percentage of the maximum current, ITripMax. The actual current at each step ITrip is approximated by: ITrip = (% ITripMax / 100) ITripMax where % ITripMax is given in the Step Sequencing table. Note: It is critical to ensure that the maximum rating of 500mV on each SENSEx pin is not exceeded. Fixed Off-Time The internal PWM current control circuitry uses a one-shot circuit to control the time the drivers remain off. The one-shot off-time, toff, is internally set to 30 s. Blanking This function blanks the output of the current sense comparator when the outputs are switched by the internal current control circuitry. The comparator output is blanked to prevent false detections of overcurrent conditions, due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. DC motors require more blank time than stepper motors. The stepper driver blank time, tBLANKst, is approximately 1 s. The DC driver blank time, tBLANKdc, is approximately 3 s. Charge Pump (CP1 and CP2) The charge pump is used to generate a gate supply greater than VBB in order to drive the source-side DMOS gates. A 0.1 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 F ceramic capacitor is required between VCP and VBBx to act as a reservoir to operate the highside DMOS devices. Sleep Mode To minimize power consumption when not in use, the A5989 can be put into Sleep Mode by bringing the SLEEPn pin low. Sleep Mode disables much of the internal circuitry, including the charge pump. Overcurrent Protection An overcurrent monitor protects the A5989 from damage due to output shorts. If a short is detected, the A5989 latches the fault and disables the outputs. The latched fault can only be cleared by cycling the power to VBB or by putting the device in Sleep Mode. During OCP events, Absolute Maximum Ratings may be exceeded for a short period of time before outputs are latched off. Shutdown In the event of a fault (excessive junction temperature, or low voltage on VCP), the outputs of the device are disabled until the fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers. Synchronous Rectification When a PWM off cycle is triggered by an internal fixed off-time cycle, load current will recirculate. The A5989 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay. This effectively shorts the body diode with the low RDS(on) driver. This significantly lowers power dissipation. When a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A5989 Bipolar Stepper and High-Current DC Motor Driver Mixed Decay Operation MODE The stepper driver operates in mixed decay mode. Referring to Figure 2, as the trip point is reached, the device goes into fast decay mode for 30.1% of the fixed off-time period. After this fast decay portion, tFD, the device switches to slow decay mode for the remainder of the off-time. The DC driver decay mode is determined by the MODE pin. During transitions from fast decay to slow decay, the drivers are forced off for approximately 600ns. This feature is added to prevent shoot-through in the bridge. As shown in Figure 2, during this "dead time" portion, synchronous rectification is not active, and the device operates in fast decay and slow decay only. Control input MODE is used to toggle between fast decay mode and slow decay mode for the DC driver. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled when ENABLE is low. Braking Driving the device in slow decay mode via the MODE pin and applying an ENABLE chop command implements the Braking function. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts the motor-generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations: high speed and high inertia loads. VPHASE + IOUT See Enlargement A 0 - Enlargement A Fixed Off-Time 30 s 9 s 21 s ITrip IOUT SDSR FDSR FDDT SDDT SDDT Figure 2: Mixed Decay Mode Operation Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A5989 Bipolar Stepper and High-Current DC Motor Driver STEP SEQUENCING DIAGRAMS 100.0 100.0 66.7 Phase 1 (%) 66.7 Phase 1 (%) 0 -66.7 -66.7 Phase 2 (%) 0 -100.0 -100.0 100.0 100.0 66.7 66.7 Phase 2 (%) 0 0 -66.7 -66.7 -100.0 -100.0 Full step 2 phase Half step 2 phase Modified full step 2 phase Modified half step 2 phase Figure 3: Step Sequencing for Full-Step Increments Figure 4: Step Sequencing for Half-Step Increments Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A5989 Bipolar Stepper and High-Current DC Motor Driver 100.0 66.7 33.3 Phase 1 (%) 0 -33.3 -66.7 -100.0 100.0 66.7 33.3 Phase 2 (%) 0 -33.3 -66.7 -100.0 Figure 5: Decay Modes for Quarter-Step Increments Step Sequencing Settings Full 1/2 1 1/4 1 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 *Denotes modified step mode Phase 1 (%ITripMax) 0 33 100/66* 100 100 100 100/66* 33 0 33 100/66* 100 100 100 100/66* 33 I0x I1x PHASE H L L/H* L L L L/H* L H L L/H* L L L L/H* L H H L L L L L H H H L L L L L H X 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 Phase 2 (%ITripMax) 100 100 100/66* 33 0 33 100/66* 100 100 100 100/66* 33 0 33 100/66* 100 I0x I1x PHASE L L L/H* L H L L/H* L L L L/H* L H L L/H* L L L L H H H L L L L L H H H L L 0 0 0 0 X 1 1 1 1 1 1 1 X 0 0 0 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A5989 Bipolar Stepper and High-Current DC Motor Driver LOGIC TIMING DIAGRAM, DC DRIVER ENB PH MODE VBB OUTA 0V VBB OUTB 0V IOUT 0A A 1 2 3 4 5 6 7 VBB 8 9 VBB 1 5 6 OutA OutB 3 A 2 4 7 OutA OutB 8 9 Charge Pump and VREG Power-up Delay (200 s) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A5989 Bipolar Stepper and High-Current DC Motor Driver APPLICATIONS INFORMATION Motor Configurations For applications that require either dual DC or dual stepper motors, Allegro offers the A5988 and A5995. Both devices are offered in a 36 pin QFN package. Refer to the Allegro website for datasheets and further information for the devices. Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A5989 must be soldered directly onto the board. On the underside of the A5989 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low-impedance ground point and thermal path. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is necessary because the ceramic capacitor will be responsible for delivering the high-frequency current components. Sense Pins In order to minimize the effects of ground bounce and offset issues, it is important to have a low-impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A5989, that area becomes an ideal location for a star ground point. The sense resistors, RSx, should have a very low-impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low-impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. A low-impedance ground will prevent ground bounce during high-current operation and ensure that the supply voltage remains Note: When selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the SENSEx pins of 500mV. Grounding VBB VBB CVCP CVCP GND OUT1B I11 I12 GND OUT3A CIN2 NC NC PHASE1 RS2 OUT2A VREF2 OUT3A OUT2A RS2 OUT3B SENSE3 VREF1 OUT2B RS3 VBB SENSE2 SLEEPn CIN2 OUT3B OUT2B PHASE3 CIN1 SENSE3 PAD VBB CIN1 CP1 A5989 SENSE1 PHASE2 RS1 OUT3A GND OUT3B VCP I01 MODE OUT1A U1 OUT1B NC NC OUT1A 1 VREF3 RS1 CP2 CIN3 RS3 I02 CCP ENABLE GND CIN3 CCP GND Figure 6: Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A5989 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A5989 Bipolar Stepper and High-Current DC Motor Driver Terminal List Table 19 NC Name 1 NC 2 OUT1A 3 SENSE1 4 OUT1B 5 VBB Description No Connect DMOS Full Bridge 1 Output A Sense Resistor Terminal for Bridge 1 DMOS Full Bridge 1 Output B I12 28 18 PHASE1 I11 29 17 PHASE2 16 GND 6 OUT2B 15 NC 7 SENSE2 CP1 32 14 VREF3 8 OUT2A CP2 33 13 VREF2 I01 34 12 VREF1 9 NC No Connect I02 35 11 SLEEPn 10 PHASE3 Control Input ENABLE 36 10 PHASE3 11 SLEEPn Active-Low Sleep Mode Input 9 20 OUT3A Number 12 VREF1 Analog Input NC 21 SENSE3 22 OUT3B 23 VBB 24 OUT3B 25 SENSE3 26 OUT3A 27 MODE Pinout Diagram 13 VREF2 Analog Input 14 VREF3 Analog Input 15 NC No Connect 16 PGND 17 PHASE2 Control Input 18 PHASE1 Control Input 19 NC No Connect 20 OUT3A 21 SENSE3 22 OUT3B PGND 30 8 OUT2A 7 SENSE2 6 OUT2B VBB 4 OUT1B 3 SENSE1 2 1 NC OUT1A 5 PAD VCP 31 Load Supply Voltage DMOS Full Bridge 2 Output B Sense Resistor Terminal for Bridge 2 DMOS Full Bridge 2 Output A Power Ground DMOS Full Bridge 3 Output A Sense Resistor Terminal for Bridge 3 DMOS Full Bridge 3 Output B 23 VBB 24 OUT3B Load Supply Voltage 25 SENSE3 26 OUT3A DMOS Full Bridge 3 Output B 27 MODE Control Input 28 I12 Control Input 29 I11 Control Input 30 GND Ground 31 VCP Reservoir Capacitor Terminal 32 CP1 Charge Pump Capacitor Terminal 33 CP2 Charge Pump Capacitor Terminal 34 I01 Control Input 35 I02 Control Input 36 ENABLE Control Input - PAD DMOS Full Bridge 3 Output A Sense Resistor Terminal for Bridge 3 Exposed pad for enhanced thermal performance. Should be soldered to the PCB Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A5989 Bipolar Stepper and High-Current DC Motor Driver PACKAGE OUTLINE DRAWING 1.15 6.00 0.15 1 2 0.30 0.50 36 36 1 2 A 6.00 0.15 D 37X SEATING PLANE 0.08 C 4.15 C 5.80 4.15 5.80 0.90 0.10 +0.05 0.25 -0.07 0.50 All dimensions nominal, not for tooling use (reference JEDEC MO-220VJJD-3, except pin count) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 0.55 0.20 B A Terminal #1 mark area 4.15 2 1 36 4.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals EV Package, 36-Pin QFN with Exposed Thermal Pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 A5989 Bipolar Stepper and High-Current DC Motor Driver Revision History Number Date Description - June 20, 2016 Initial release 1 July 29, 2016 Updated Selection Guide table 2 November 29, 2017 3 January 29, 2019 Minor editorial updates 4 February 20, 2020 Minor editorial updates Updated Step Sequences Settings table (page 9) Copyright 2020, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14