CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 1
Chronte
l
CH7317A SDVO◊ / RGB DAC
Features General Description
• High-speed SDVO◊ (1G~2Gbps) AC-coupled serial
differential RGB inputs
• Support for VGA RGB bypass
• Output Analog RGB.
• Three 10-bit video DAC outputs
• DAC output CRT RGB connector
• Fully programmable through serial port
• Programmable power management
• Configuration through Intel® SDVO OpCode◊
• Complete Windows driver support
• Offered in 64-pin LQFP and 64-pin QFN package
◊ Intel® Proprietary.
The CH7317A is a Display Controller device which accepts
a digital graphics high speed AC coupled serial differential
RGB input signal, and encodes and transmits data through
analog RGB port. The device accepts one channel of RGB
data over three pairs of serial data ports.
CH7317A output VGA style analog RGB for use as a CRT
DAC. Supported analog video VGA connector.
SDVO_Clk(+,-)
SDVO_R(+,-)
SDVO_G(+,-)
SDVO_B(+,-) Data Latch,
Serial to Parallel
Clock
Driver
SPC
SPD
RESET*
XI/FIN,XO
BCO/VSYNC
ISET
PLL
Control
2
2
Three
10-bit DAC's
DAC 2
DAC 1
DAC 0
SC_PROM
SD_PROM
AS
10bit-8bit
decoder
6
C/HSYNC SC_DDC
SD_DDC
DACA[2:0]
Serial
Port
Control
3
Figure 1: Functional Block Diagram
CHRONTEL CH7317A
2 201-0000-087 Rev. 1.2, 12/2/200 8
Table of Contents
1.0 Pin-Out ____________________________________________________________________ 4
1.1 Package Diagram ___________________________________________________________________4
1.2 Pin Description _____________________________________________________________________6
2.0 Functional Description________________________________________________________ 8
2.1 Input Interface______________________________________________________________________8
2.2 CRT Bypass Operation _______________________________________________________________8
2.3 Command Interface _________________________________________________________________9
2.4 Boundary scan Test__________________________________________________________________9
3.0 Register Control ____________________________________________________________ 12
4.0 Electrical Specifications______________________________________________________ 13
4.1 Absolute Maximum Ratings __________________________________________________________13
4.2 Recommended Operating Conditions ___________________________________________________13
4.3 Electrical Characteristics ____________________________________________________________14
4.4 DC Specifications __________________________________________________________________14
4.5 AC Specifications __________________________________________________________________16
5.0 Package Dimensions_________________________________________________________ 18
6.0 Revision History ____________________________________________________________ 20
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 3
Figures and Tables
List of Figures
Figure 1: Functional Block Diagram .............................................................................................................................1
Figure 2: 64-Pin LQFP Package ....................................................................................................................................4
Figure 3: 64-Pin QFN Package......................................................................................................................................5
Figure 4: Control Bus Switch ........................................................................................................................................9
Figure 5: NAND Tree Connection...............................................................................................................................10
Figure 6: 64 Pin LQFP Package ..................................................................................................................................18
Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................19
List of Tables
Table 1: Pin Description ................................................................................................................................................6
Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns...................................8
Table 3: Video DAC Configurations for CH7317A ......................................................................................................9
Table 4: Signal Order in the NAND Tree Testing.......................................................................................................10
Table 5: Signals not be tested in NAND Test besides power pins...............................................................................11
Table 6: Revisions .......................................................................................................................................................20
CHRONTEL CH7317A
4 201-0000-087 Rev. 1.2, 12/2/200 8
1.0 Pin-Out
1.1 Package Diagram
1.1.1 The 64-Pin LQFP Package Diagram
DGND
XI/FIN
XO
DVDD
VDAC1
DACA[2]
NC
DACA[1]
GDAC0
NC
ISET
DACA[0]
NC
SPD
SPC
RESET*
DVDD Chrontel
SDVO_B-
SDVO_B+
SDVO_G-
SDVO_G+
SDVO_R-
SDVO_R+
AGND
V3V
NC
CH7317
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
27
28
29
30
31
32
18
19
20
21
22
23
24
25
26
RPLL
NC
SDVO_CLK+
SDVO_CLK-
SD_DDC
SC_DDC
SD_PROM
SC_PROM
DGND
NC
AVDD
AGND
17
AVDD
NC
NC
NC
BCO/VSYNC
C/HSYNC
AS
BSCAN
NC
AGND
AVDD
NC
DGND
DGND
DVDD
DVDD
VDAC0
GDAC1
NC
NC
NC
NC
DGND
DVDD
VDAC2
GDAC2
Figure 2: 64-Pin LQFP Package
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 5
1.1.2 The 64-Pin QFN Package Diagram
27
28
29
30
31
32
18
19
20
21
22
23
24
25
26
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Chrontel
CH7317
DGND
XI/FIN
XO
DVDD
V3V
NC
NC
NC
NC
NC
BCO/VSYNC
C/HSYNC
DGND
DVDD
DGND
DVDD
SDVO_B-
SDVO_B+
SDVO_G-
SDVO_G+
SDVO_R-
SDVO_R+
AGND
RPLL
SDVO_CLK+
SDVO_CLK-
NC
AVDD
AGND
AVDD
AGND
AVDD
VDAC 1
DACA[2]
NC
DACA[1]
GDAC0
NC
ISET
DACA[0]
NC
VDAC 0
GDAC1
NC
NC
NC
NC
GDAC2
SPD
SPC
RESET*
DVDD
SD_DDC
SC_DDC
SD_PROM
SC_PROM
DGND
AS
BSCAN
NC
NC
DGND
DVDD
VDAC2
Figure 3: 64-Pin QFN Package
CHRONTEL CH7317A
6 201-0000-087 Rev. 1.2, 12/2/200 8
1.2 Pin Description
Table 1: Pin Description
Pin # Type Symbol Description
2 In/Out SD_DDC
Routed Serial Port Data Output to DDC
This pin functions as the bi-directional data pin of the serial port to DDC receiver. This
pin will require a 10k pull-up resistor to the desired high state voltage. Leave open i
f
unused.
3 In/Out SC_DDC
Routed Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to DDC receiver. This pin will
require a 10k pull-up resistor to the desired high state voltage. Leave open if unused.
4 In/Out SD_PROM
Routed Data Output to PROM
This pin functions as the bi-directional data pin of the serial port for PROM on ADD2
◊
card. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave
open if unused.
5 Out SC_PROM
Routed Clock Output to PROM
This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pi
n
will require a 10k pull-up resistor to the desired high state voltage. Leave open i
f
unused.
7 In RESET*
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When this pi
n
is high, reset is controlled through the serial port register. This pin is 3.3V compliant.
8 In AS Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS
is low the address is 72h, when high the address is 70h.
11 In/Out SPD Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates wit
h
inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external
4kΩ - 9 kΩ pull up resistor to 2.5V.
12 In/Out SPC Serial Port Clock
This pin functions as the clock of the serial port and operates from 0 to 2.5V. This pin
requires an external 4kΩ - 9kΩ pull up resistor to 2.5V.
14 In BSCAN BSCAN
(internal pull low)
This pin should be left open or pulled low with a 10k resistor in the
application. This pin enables the boundary scan for in-circuit testing. Voltage
level is 0 to DVDD. This pin should be pulled low during normal operation.
20,24,28 Out DACA[2:0] DAC Output A
Video Digital-to-Analog outputs. Refer to section 32.2.1 for information regarding
support for RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly
terminated load.
1,15,18,21,
22,25,26,
29,30,43,
44,46,47,
48,51
N
C
N
o Connect ( Reserved )
◊ Intel Proprietary.
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 7
Table 1: Pin Description (contd.)
Pin # Type Symbol Description
32 Ref. ISET Current Set Resistor
This pin sets the DAC current. A 1.2Kohm (+/- 1%) resistor should be connected
between this pin and DAC gr ound (pin 31) using shor t and wide traces.
34 Out CHSYNC
Composite / Horizontal Sync Output
A buffered version of VGA composite sync as well as horizontal sync can be
acquired from this pin.
36 Out VSYNC VSYNC
A buffered version of VGA vertical sync can be acquired from this pin.
39 In XI/FIN Crystal Input / External Reference Input
A parallel resonant 27MHz crystal (±100 ppm) should be attached between
this pin and XO. However, an external CMOS clock can drive the XI/FIN
input.
40 Out XO Crystal Output
A parallel resonant 27MHz crystal (±100 ppm) should be attached between
this pin and XI/FIN. However, if an external CMOS clock is attached to the
XI/FIN input, XO should be left open.
50 In RPLL PLL Resistor Input
External resistor 10Kohm should be connected between this pin and pin 49.
53,54,56,
57,59,60
In SDVO_R+/-,
SDVO_G+/-,
SDVO_B+/-
SDVO Data Channel Inputs
These pins accept 3 AC-coupled differential pair of RGB inputs from a digital video
port of a graphics controller.
62,63 In SDVO_CLK+/-
Differential Clock Input associated with SDVO Data channel
(SDVO_R+/-, SDVO_G+/-, SDVO_B+/-)
The range of this clock pair is 100~200MHz. For specified pixel rates in specifie
d
modes this clock pair will run at an integer multiple of the pixel rate. Refer to
section 32.1.3 for details.
6,13,35,41,
42
Power DVDD Digital Supply Voltage (2.5V)
9,10,37,38,
45
Power DGND Digital Ground
16 Power VDAC2 DAC Supply Voltage (3.3V)
17 Power GDAC2 DAC Ground
19 Power VDAC1 DAC Supply Voltage (3.3V)
23 Power GDAC1 DAC Ground
27 Power VDAC0 DAC Supply Voltage (3.3V)
31 Power GDAC0 DAC Ground
52,58,64 Power AVDD Analog Supply Voltage (2.5V)
49,55,61 Power AGND Analog Ground
33 Power V3V 3.3V Supply Voltage (3.3V)
CHRONTEL CH7317A
8 201-0000-087 Rev. 1.2, 12/2/200 8
2.0 Functional Description
2.1 Input Interface
2.1.1 Overview
One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The
input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate
(SDVO_CLK+/-). The CH7317A de-serializes the input into 10-bit parallel data with synchronization and
alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE).
2.1.2 Interface Voltage Levels
All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level
for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The
differential p-p output voltage has a min of 0.8V, with a max of 1.2V.
2.1.3 Inpu t Clock and Data Timing
A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of
the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.
The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate
do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) so
that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a
multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters
(‘0001111010’) are used to stuff the data stream. The CH7317A supports the following clock rate multipliers and
fill patterns shown in 3Table 2.
Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns
Pixel Rate Clock Rate – Multiplier Stuffing Format Data Transfer Rate - Multiplier
25~50 MP/s 100~200 MHz – 4xPixel Rate Data, Fill, Fill, Fill 1.00~2.00 Gbits/s – 10xClock Rate
50~100 MP/s 100~200 MHz – 2xPixel Rate Data, Fill 1.00~2.00 Gbits/s – 10xClock Rate
100~200 MP/s 100~200 MHz – 1xPixel Rate Data 1.00~2.00 Gbits/s – 10xClock Rate
2.1.4 Synchronization
Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during
the blank period. The CH7317A synchronizes during the initialization period and subsequently uses the blank
periods to re-synch to the data stream.
2.2 CRT Bypass Operation
The CH7317A operates in CRT RGB Bypass mode. In CRT Bypass mode, data from the graphics device, after
proper decoding, are bypassed directly to the video DACs to implement a second CRT DAC function. Sync signals,
after proper decoding, are buffered internally, and can be output to drive the CRT. The CH7317A can support a
pixel rate of 200MHz. This operating mode uses 8-bits of the DAC’s 10-bit range, and provides a nominal signal
swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75Ω doubly
terminated load. No scaling, scan conversion or flicker filtering is applied in CRT Bypass modes.
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 9
2.2.1 Video DAC Outputs
3Table 3 below lists the DAC output configurations of the CH7317A.
Table 3: Video DAC Configurations for CH7317A
Output Type DACA[0] DACA[1] DACA[2]
CRT RGB B G R
2.3 Command Interface
Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7317A accepts incoming
control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM,
DDC, or CH7317A internal registers. The control bus is able to run up to 1MHz when communicating with internal
registers, up to 400kHz for the PROM and up to 100kHz for the DDC.
Internal
Device
Registers
DDC
PROM
SPC,SPD
observer control
the
switch
on/off
default
position
Figure 4: Control Bus Switch
Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this
stage, the CH7317A observes the control bus traffic. If the observing logic sees a control bus transaction destined
for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal
registers. In the condition that traffic is to the internal registers, an op-code command is used to set the redirection
circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at
the stage of traffic to DDC occurs on observing a STOP after a START on the control bus.
2.4 Boundary scan Test
CH7317A provides a called “NAND TREE Testing” to verify IO cell function at the PC board level. This test will
check the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads, open
printed circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input
mode, connects all inputs with NAND gates as shown in the figure below and switches each signal to high or low
according to the sequence in 4Table 4. The test results then pass out at pin 51 (NC).
CHRONTEL CH7317A
10 201-0000-087 Rev. 1.2, 12/2/2008
Figure 5: NAND Tree Connection
Testing Sequence
Set BSCAN =1; (internal weak pull low)
Set all signals listed in 4Table 4 to 1.
Set all signals listed in 4Table 4 to 0, toggle one by one with certain time period suggested 100ns. Pin 51 (NC) will
change its value each time an input value changed.
Table 4: Signal Order in the NAND Tree Testing
Order Pin Name LQFP Pin
1 SD_DDC 2
2 SC_DDC 3
3 SD_PROM 4
4 SC_ PROM 5
5 RESETB 7
6 AS 8
7 SPD 11
8 SPC 12
9 NC 18
10 DACA[2] 20
11 NC 21
12 NC 22
13 DACA[1] 24
14 NC 25
15 NC 26
16 DACA[0] 28
17 NC 29
18 NC 30
19 ISET 32
20 CHSYNC 34
21 VSYNC 36
22 XI/FIN 39
23 XO 40
24 NC 43
25 NC 44
26 NC 46
27 NC 47
28 NC 48
29 NC 51
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 11
Table 5: Signals not be tested in NAND Test besides power pins
Pin Name LQFP Pin
SDVO_R+ 53
SDVO_R- 54
SDVO_G+ 56
SDVO_G- 57
SDVO_B+ 59
SDVO_B- 60
SDVO_CLK+ 62
SDVO_CLK- 63
BSCAN 14
NC 15
NC 1
CHRONTEL CH7317A
12 201-0000-087 Rev. 1.2, 12/2/2008
3.0 Register Control
The CH7317A is controlled via a serial control port. The serial bus uses only the SC clock to latch data into
registers, and does not use any internally generated clocks so that the device can be written to in all power down
modes. The device will retain all register values during power down modes.
Registers 00h to 11h are reserved for op-code use. All registers except bytes 00h to 11h are reserved for internal
factory use. For details regarding Intel® SDVO op-codes, please contact Intel®.
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 13
4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
Symbol Description Min Typ Max Units
All 2.5V power supplies relative to GND
All 3.3V power supplies relative to GND
-0.5
-0.5 3.0
5.0 V
TSC Analog output short circuit duration Indefinite Sec
TAMB Ambient operating temperature -20 85 °C
TSTOR Storage temperature -65 150 °C
TJ Junction temperature 150 °C
TVPS Vapor phase soldering (5 second)
Vapor phase soldering (11 second)
Vapor phase soldering (1 minute)
260
245
225
°C
Note:
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute
maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor
phase soldering apply to all standard and lead free parts.
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce
destructive latch-up.
4.2 Recommended Operating Conditions
Symbol Description Min Typ Max Units
AVDD Analog Power Supply Voltage 2.375 2.5 2.625 V
DVDD Digital Power Supply Voltage 2.375 2.5 2.625 V
VDAC DAC Power Supply 3.100 3.3 3.500 V
VDD33 Generic for all 3.3V supplies 3.100 3.3 3.500 V
VDD25 Generic for all 2.5V supplies 2.375 2.5 2.625 V
V3V 3.3V Power Supply 3.100 3.3 3.500 V
RSET Resistor on ISET pin (32) 1188 1200 1212 Ω
Ambient operating temperature -20 70 °C
CHRONTEL CH7317A
14 201-0000-087 Rev. 1.2, 12/2/2008
4.3 Electrical Characteristics
(Operating Conditions: TA = -20°C – 70°C, VDD25 =2.5V ± 5%, VDD33 = 3. 3V ± 5%,)
Symbol Description Min Typ Max Units
Video D/A Resolution 10 10 10 bits
Full scale output current 35. 3 mA
Video level error 10 %
IVDD25
(162 MHz
pixel clock)
Total VDD25 supply current (2.5V supplies) with 1600x1200,
32bit, 60H 131 mA
IVDD33
(162 MHz
pixel clock)
Total VDD33 supply current (3.3V supplies) with 1600x1200,
32bit, 60H 105 mA
IVDDV Total V3V current (3.3V supply) 0 mA
IPD Total Power Down Current 0.1 mA
4.4 DC Specifications
Symbol Description Test Condition Min Typ Max Unit
VRX-DIFFp-p SDVO Receiver Differential
Input Peak to Peak Voltage
VRX-DIFFp-p = 2 * ⏐VRX-D+
- VRX-D-⏐
0.175 1.200 V
ZRX-DIFF-DC SDVO Receiver DC Differential
Input Impedance
80 100 120
Ω
ZRX-COM-DC SDVO Receiver DC Common
Mode Input Impedance
40 50 60 Ω
ZRX-COM-INITIAL-
DC
SDVO Receiver Initial DC
Common Mode Input
Impedance
Impedance allowed when
receiver terminations are
first turned on
5 50 60 Ω
ZRX-COM-High-
IMP-DC
SDVO Receiver Powered
Down DC Common Mode
Input Impedance
Impedance allowed when
receiver terminations are not
powered
20k 200k
Ω
VPP_POCLK POCLK Differential Pk – Pk
Output Voltage 0.8 1.2 V
VSDOL
1 SPD (serial port data) Output
Low Voltage
IOL = 2.0 mA 0.4 V
VSPIH
2 Serial Port (SPC, SPD) Input
High Voltage
2.0 +5V
+0.5
V
VSPIL
2 Serial Port (SPC, SPD) Input
Low Voltage
GND-0.5 0.4 V
VHYS Hysteresis of Serial Port Inputs 0.25 V
VDDCIH DDC Serial Port
Input High Voltage
4.0
+5V
+0.5
V
VDDCIL DDC Serial Port
Input Low Voltage
GND-0.5
0.4
V
VPROMIH PROM Serial Port
Input High Voltage
4.0
+5V
+0.5
V
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 15
Symbol Description Test Condition Min Typ Max Unit
VPROMIL PROM Serial Port
Input Low Voltage
GND-0.5
0.4
V
VSD_DDCOL
3 SPD (serial port data) Output
Low Voltage from SD_DDC (or
SD_EPROM)
Input is VINL at SD_DDC or
SD_EPROM.
4.0kΩ pullup to 2.5V.
0.9*VINL +
0.25
V
VDDCOL
4 SC_DDC and SD_DDC Output
Low Voltage
Input is VINL at SPC and
SPD.
5.6kΩ pullup to 5.0V.
0.933*VINL
+ 0.35
V
VEPROMOL
5 SC_EPROM and SD_EPROM
Output Low Voltage
Input is VINL at SPC and
SPD.
5.6kΩ pullup to 5.0V.
0.933*VINL
+ 0.35
V
VMISC1IH
6 RESET*
Input High Voltage
2.7 VDD33 +
0.5
V
VMISC1IL
6 RESET*
Input Low Voltage
GND-0.5 0.5 V
VMISC2IH
7 AS, BSCAN
Input High Voltage
2.0 VDD25 +
0.5
V
VMISC2IL
7 AS, BSCAN
Input Low Voltage
DVDD=2.5V GND-0.5 0.5 V
IPU AS, RESET*
Pull Up Current
VIN = 0V 10 30 μA
IPD BSCAN
Pull Down Current
VIN = 2.5V 10 30 μA
VSYNCOH
8 CHSYNC, VSYNC
Output High Voltage
IOH = -0.4mA 2.0 V
VSYNCOL
8 CHSYNC, VSYNC
Output Low Voltage
IOL = 3.2mA 0.4 V
ZDL DL[3:1]
Output Impedance
DC 7 10 13 kΩ
Notes:
1. VSDOL is the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM.
2. VSPIH and VSPIL are the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate
requirements may exist for transmission to the DDC and EEPROM.
3. VSD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is VINL. Maximum output
voltage has been calculated with a worst case pull-up of 4.0kΩ to 2.5V on SPD.
4. VDDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output
voltage has been calculated with 5.6k pull-up to 5V on SC_DDC and SD_DDC.
5. VEPROMOL is the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is VINL.
Maximum output voltage has been calculated with 5.6kΩ pull-up to 5V on SC_EPROM and SD_EPROM.
6. VMISC1 - refers to RESET* input which is 3.3V compliant.
7. VMISC2 - refers to AS, BSCAN which are 2.5V compliant
8. VSYNC – refers to CHSYNC and VSYNC outputs.
CHRONTEL CH7317A
16 201-0000-087 Rev. 1.2, 12/2/2008
4.5 AC Specifications
Symbol Description Test Condition Min Typ Max Unit
UIDATA SDVO Receiver Unit Interval
for Data Channels
Typ. –
300ppm
1/[Data
Transfer
Rate]
Typ. +
300ppm
ps
fSDVO_CLK SDVO CLK Input Frequency 100 200 MHz
fPIXEL SDVO Receiver Pixel
frequency
25 165 MHz
fSYMBOL SDVO Receiver Symbol
frequency
1 2 GHz
tRX-EYE SDVO Receiver Minimum Eye
Width
0.4 UI
tRX-EYE-JITTER SDVO Receiver Max. time
between jitter median and
max. deviation from median
0.3 UI
VRX-CM-ACp SDVO Receiver AC Peak
Common Mode Input Voltage
150 mV
RLRX-DIFF Differential Return Loss 50MHz – 1.25GHz 15 dB
RLRX-CM Common Mode Return Loss 50MHz – 1.25GHz 6 dB
TSPR SPC, SPD Rise Time
(20% - 80%)
Standard mode 100k
Fast mode 400k
1M running speed
1000
300
150
ns
ns
ns
TSPF SPC, SPD Fall Time
(20% - 80%)
Standard mode 100k
Fast mode 400k
1M running speed
300
300
150
ns
ns
ns
TPROMR SC_PROM, SD_PROM Rise
Time (20% - 80%)
Fast mode 400K 300 ns
TPROMF SC_PROM, SD_PROM Rise
Time (20% - 80%)
Fast mode 400K 300 ns
TDDCR SC_DDC, SD_DDC Rise
Time (20% - 80%)
Standard mode 100k 1000 ns
TDDCF SC_DDC, SD_DDC Fall
Time (20% - 80%)
Standard mode 100k 300 ns
TDDCR-DELAY
1 SC_DDC, SD_DDC Rise
Time Delay (50%)
Standard mode 100k 0 ns
TDDCF-DELAY
1 SC_DDC, SD_DDC Fall
Time Delay (50%)
Standard mode 100k 3 ns
tSKEW SDVO Receiver Total Lane to
Lane Skew of Inputs
Across all lanes 2 ns
tR CHSYNC and VSYNC (when
configured as outputs)
Output Rise Time
(20% - 80%)
15pF load
DVDD = 2.5V
1.50 ns
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 17
tF H and V (when configured as
outputs)
Output Fall Time
(20% - 80%)
15pF load
DVDD = 2.5V
1.50 ns
Notes:
1. Refers to the figure below, the delay refers to the time pass through the internal switches.
R=5K
3.3V typ. 2.5V typ.
To SPC/SPD pin
To DDC pin
CHRONTEL CH7317A
18 201-0000-087 Rev. 1.2, 12/2/2008
5.0 Package Dimensions
I
BA
1
E
F
.004
“
LEAD
CO-PLANARITY
CD
B
A
H
J
G
Figure 6: 64 Pin LQFP Package
Table of Dimensions
No. of Leads SYMBOL
64 (10 X 10 mm) A B C D E F G H I J
MIN 0.17 1.35 0.05 0.45 0.09 0° Milli-
meters MAX 12 10 0.50
0.27 1.45 0.15 1.00 0.75 0.20 7°
Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D.
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 19
TOP VIEW
4833
17
32
116
A
64
49
A
I
H
G
BOTTOM VIEW
C
C/2
B
B/2
F
17
32
33
1
49
48
16
64
E
D
Pin 1
Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm)
Table of Dimensions
No. of Leads SYMBOL
64 (8 X 8 mm) A B C D E F G H I
MIN 6.1 6.1 0.15 0.35 0.7 0 Milli-
meters MAX 8 6.3 6.3 0.4 0.25 0.45 0.8 0.05
0.203
Notes:
1. Conforms to JEDEC standard JESD-30 MO-220.
CHRONTEL CH7317A
20 201-0000-087 Rev. 1.2, 12/2/2008
6.0 Revision History
Table 6: Revis ions
Rev. # Date Section Description
1.0 12/19/06 All Initial official release.
1.1 9/13/07 1.1, 5.0 Add 64-QFN package.
1.11 10/26/07 4.4 Change VDD5+ to +5V
1.2 12/2/08 4.2, 4.3 Update operating temperature.
CHRONTEL CH7317A
201-0000-087 Rev. 1.2, 12/2/200 8 21
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use
of our products and assume no liability for errors contained in this document. The customer should make sure that
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not
infringe upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number Package Type Number of
Pins Voltage Supply
CH7317A-TF Lead Free LQFP 64 2.5V & 3.3V
CH7317A-TF-TR Lead Free LQFP
in Tape & Reel 64 2.5V & 3.3V
CH7317A-BF Lead Free QFN 64 2.5V & 3.3V
CH7317A-BF-TR Lead Free QFN
in Tape & Reel 64 2.5V & 3.3V
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
©2008 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
