SST34HF324G-70-4C-L3KE - Silicon Storage Technology

S71310-02-EOL 12/07

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

ComboMemory is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Data Sheet

FEATURES:

• Flash Organization: 2M x16

– 32 Mbit: 24Mbit + 8Mbit

• Concurrent Operation

– Read from or Write to SRAM while

Erase/Program Flash

• SRAM Organization:

– 4 Mbit: 256K x16

• Single 2.7-3.3V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption: (typical values @ 5 MHz)

– Active Current: Flash 10 mA (typical)

SRAM 6 mA (typical)

– Standby Current: 10 µA (typical)

• Hardware Sector Protection (WP#)

– Protects 4 outer most sectors (8 KWord) in the

smaller bank by holding WP# low and unprotects

by holding WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

data array

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Read Access Time

– Flash: 70 ns

–SRAM: 70 ns

• Erase-Suspend / Erase-Resume Capabilities

• Latched Address and Data

• Fast Erase and Word-Program (typical):

– Sector-Erase Time: 18 ms

– Block-Erase Time: 18 ms

– Chip-Erase Time: 35 ms

– Word-Program Time: 7 µs

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Packages Available

– 48-ball LFBGA (6mm x 8mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST34HF324G ComboMemory integrates a 2M x16

CMOS flash memory bank with 256K x16 CMOS SRAM

memory bank in a multi-chip package (MCP). This device

is fabricated using SST proprietary, high-performance

CMOS SuperFlash technology incorporating the split-gate

cell design and thick-oxide tunneling injector to attain better

reliability and manufacturability compared with alternate

approaches. The SST34HF324G is ideal for applications

such as cellular phones, GPS devices, PDAs, and other

portable electronic devices in a low power and small form

factor system.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore, the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles. The SST34HF324G devices offer a guaran-

teed endurance of 10,000 cycles. Data retention is rated at

greater than 100 years. With high-performance Program

operations, the flash memory banks provide a typical

Word-Program time of 7 µsec. To protect against inadvert-

ent flash write, the SST34HF324G devices contain on-chip

hardware and software data protection schemes.

The flash and SRAM operate as two independent memory

banks with respective bank enable signals. The memory

bank selection is done by two bank enable signals. The

SRAM bank enable signal, BES#, selects the SRAM bank.

The flash memory bank enable signal, BEF#, has to be

used with Software Data Protection (SDP) command

sequence when controlling the Erase and Program opera-

tions in the flash memory bank. The memory banks are

superimposed in the same memory address space where

they share common address lines, data lines, WE# and

OE# which minimize power consumption and area. See

Table 3 for memory organization.

Designed, manufactured, and tested for applications requir-

ing low power and small form factor, the SST34HF324G

are offered in both commercial and extended temperatures

and a small footprint package to meet board space con-

straint requirements. See Figure 2 for pin assignments.

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

Device Operation

The SST34HF324G use BES# and BEF# to control opera-

tion of either the flash or the SRAM memory bank. When

BEF# is low, the flash bank is activated for Read, Program

or Erase operation. When BES# is low the SRAM is acti-

vated for Read and Write operation. BEF# and BES# can-

not be at low level at the same time. If all bank enable

signals are asserted, bus contention will result and the

device may suffer permanent damage. All address,

data, and control lines are shared by flash and SRAM

memory banks which minimizes power consumption and

loading. The device goes into standby when BEF# and

BES# bank enables are raised to VIHC (Logic High) or

when BEF# is high.

Concurrent Read/Write Operation

The SST34HF324G provide the unique benefit of being

able to read from or write to SRAM, while simultaneously

erasing or programming the flash. This allows data alter-

ation code to be executed from SRAM, while altering the

data in flash. The following table lists all valid states.

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

Flash Read Operation

The Read operation of the SST34HF324G is controlled by

BEF# and OE#, both have to be low for the system to

obtain data from the outputs. BEF# is used for device

selection. When BEF# is high, the chip is deselected and

only standby power is consumed. OE# is the output control

and is used to gate data from the output pins. The data bus

is in high impedance state when either BEF# or OE# is

high. Refer to the Read cycle timing diagram for further

details (Figure 6).

Flash Program Operation

These devices are programmed on a word-by-word basis.

Before programming, one must ensure that the sector

which is being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Software Data Protection is initiated using the

three-byte load sequence.

2. Address and data are loaded.

During the Program operation, the addresses are

latched on the falling edge of either BEF# or WE#,

whichever occurs last. The data is latched on the

rising edge of either BEF# or WE#, whichever

occurs first.

3. The internal Program operation is initiated after

the rising edge of the fourth WE# or BEF#, which-

ever occurs first. The Program operation, once ini-

tiated, will be completed typically within 7 µs.

See Figures 7 and 8 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 20 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during an internal Program opera-

tion are ignored.

Flash Sector- /Block-Erase Operation

These devices offer both Sector-Erase and Block-Erase

operations. These operations allow the system to erase the

devices on a sector-by-sector (or block-by-block) basis.

The sector architecture is based on a uniform sector size of

2 KWord. The Block-Erase mode is based on a uniform

block size of 32 KWord. The Sector-Erase operation is initi-

ated by executing a six-byte command sequence with a

Sector-Erase command (50H) and sector address (SA) in

the last bus cycle. The Block-Erase operation is initiated by

executing a six-byte command sequence with Block-Erase

command (30H) and block address (BA) in the last bus

cycle. The sector or block address is latched on the falling

edge of the sixth WE# pulse, while the command (30H or

50H) is latched on the rising edge of the sixth WE# pulse.

The internal Erase operation begins after the sixth WE#

pulse. Any commands issued during the Block- or Sector-

Erase operation are ignored except Erase-Suspend and

Erase-Resume. See Figures 12 and 13 for timing wave-

forms.

Concurrent Read/Write State Table

Flash SRAM

Program/Erase Read

Program/Erase Write

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

Flash Chip-Erase Operation

The SST34HF324G provide a Chip-Erase operation,

which allows the user to erase all sectors/blocks to the “1”

state. This is useful when the device must be quickly

erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

BEF#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bits or Data# Polling. See

Table 6 for the command sequence, Figure 11 for timing

diagram, and Figure 23 for the flowchart. Any commands

issued during the Chip-Erase operation are ignored.

Flash Erase-Suspend/-Resume Operations

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing a one-byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode within 20 µs after

the Erase-Suspend command had been issued. Valid data

can be read from any sector or block that is not suspended

from an Erase operation. Reading at address location

within erase-suspended sectors/blocks will output DQ2 tog-

gling and DQ6 at “1”. While in Erase-Suspend mode, a Pro-

gram operation is allowed except for the sector or block

selected for Erase-Suspend. To resume Sector-Erase or

Block-Erase operation which has been suspended, the

system must issue an Erase-Resume command. The

operation is executed by issuing a one-byte command

sequence with Erase Resume command (30H) at any

address in the one-byte sequence.

Flash Write Operation Status Detection

The SST34HF324G provides two software means to

detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system Write cycle time.

The software detection includes two status bits: Data#

Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write

detection mode is enabled after the rising edge of WE#,

which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling

(DQ7) or Toggle Bit (DQ6) read may be simultaneous with

the completion of the Write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7 or DQ6. In order to pre-

vent spurious rejection, if an erroneous result occurs, the

software routine should include a loop to read the

accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle,

otherwise the rejection is valid.

Flash Data# Polling (DQ7)

When the device is in an internal Program operation, any

attempt to read DQ7 will produce the complement of the

true data. Once the Program operation is completed, DQ7

will produce true data. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE# (or

BEF#) pulse for Program operation. For Sector-, Block-, or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Poll-

ing (DQ7) timing diagram and Figure 21 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. The toggle bit is valid after the rising edge of the fourth

WE# (or BEF#) pulse for Program operations. For Sector-,

Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the

rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to

“1” if a Read operation is attempted on an Erase-sus-

pended Sector/Block. If Program operation is initiated in a

sector/block not selected in Erase-Suspend mode, DQ6 will

toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6 to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bit information. The Toggle Bit (DQ2)

is valid after the rising edge of the last WE# (or BEF#)

pulse of a Write operation. See Figure 10 for Toggle Bit tim-

ing diagram and Figure 21 for a flowchart.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

Note: DQ7, DQ6, and DQ2 require a valid address when reading

status information.

Data Protection

The SST34HF324G provide both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Hardware Block Protection

The SST34HF324G provide a hardware block protection

which protects the outermost 8 KWord in Bank 1. The block

is protected when WP# is held low. See Figure 3 for Block-

Protection location.

A user can disable block protection by driving WP# high

thus allowing erase or program of data into the protected

sectors. WP# must be held high prior to issuing the write

command and remain stable until after the entire Write

operation has completed.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode (see Figure 17). When no internal

Program/Erase operation is in progress, a minimum period

of TRHR is required after RST# is driven high before a valid

Read can take place (see Figure 16).

The Erase operation that has been interrupted needs to be

reinitiated after the device resumes normal operation mode

to ensure data integrity. See Figures 16 and 17 for timing

diagrams.

Software Data Protection (SDP)

The SST34HF324G provide the JEDEC standard Soft-

ware Data Protection scheme for all data alteration opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. The SST34HF324G are shipped with

the Software Data Protection permanently enabled. See

Table 6 for the specific software command codes. During

SDP command sequence, invalid commands will abort the

device to Read mode within TRC. The contents of DQ15-

DQ8 are “Don’t Care” during any SDP command

sequence.

TABLE 1: Write Operation Status

Status DQ7DQ6DQ2

Normal

Operation

Standard

Program

DQ7# Toggle No Toggle

Standard

Erase

0 Toggle Toggle

Erase-

Suspend

Mode

Read From

Erase

Suspended

Sector/

Block

1 1 Toggle

Read From

Non-Erase

Suspended

Sector/

Block

Data Data Data

Program DQ7# Toggle No Toggle

T1.0 1310

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

Product Identification

The Product Identification mode identifies the device as

SST34HF324G and the manufacturer as SST. This mode

may be accessed by software operations only. The hard-

ware device ID Read operation, which is typically used by

programmers cannot be used on this device because of

the shared lines between flash and SRAM in the multi-chip

package. Therefore, application of high voltage to pin A9

may damage this device. Users may use the software

Product Identification operation to identify the part (i.e.,

using the device ID) when using multiple manufacturers in

the same socket. For details, see Tables 5 and 6 for soft-

ware operation, Figure 14 for the Software ID Entry and

Read timing diagram and Figure 22 for the ID Entry com-

mand sequence flowchart.

Note: BK = Bank Address (A20-A18)

Product Identification Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit

command is ignored during an internal Program or Erase

operation. See Table 6 for software command codes, Fig-

ure 15 for timing waveform and Figure 22 for a flowchart.

SRAM Operation

With BES# low and BEF# high, the SST34HF324G oper-

ates as either 256K x16 CMOS SRAM, with fully static

operation requiring no external clocks or timing strobes.

When BES# and BEF# are high, all memory banks are

deselected and the device enters standby. Read and Write

cycle times are equal. The control signals UBS# and LBS#

provide access to the upper data byte and lower data byte.

See Table 5 for SRAM Read and Write data byte control

modes of operation.

SRAM Read

The SRAM Read operation of the SST34HF324G is con-

trolled by OE# and BES#, both have to be low with WE#

high for the system to obtain data from the outputs. BES#

is used for SRAM bank selection. OE# is the output control

and is used to gate data from the output pins. The data

bus is in high impedance state when OE# is high. Refer to

the Read cycle timing diagram, Figure 3, for further details.

SRAM Write

The SRAM Write operation of the SST34HF324G is con-

trolled by WE# and BES#, both have to be low for the sys-

tem to write to the SRAM. During the Word-Write

operation, the addresses and data are referenced to the

rising edge of either BES# or WE# whichever occurs first.

The write time is measured from the last falling edge of

BES# or WE# to the first rising edge of BES# or WE#.

Refer to the Write cycle timing diagrams, Figures 4 and 5,

for further details.

TABLE 2: Product Identification

ADDRESS DATA

Manufacturer’s ID BK0000H 00BFH

Device ID

SST34HF324G BK0001H 7353H

T2.0 1310

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 1: Functional Block Diagram

1310 B1.0

SuperFlash Memory

(Bank 1)

I/O Buffers

SuperFlash Memory

(Bank 2)

4 Mbit SRAM

A20- A0

DQ15 - DQ0

Control

Logic

BEF#

LBS#

UBS#

WE#

OE#

BES#

Address

Buffers

Address

Buffers

WP#

RST#

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 3: Dual-Bank Memory Organization (1 of 2)

SST34HF324G Block Block Size Address Range x8 Address Range x16

Bank 1

BA63 8 KW / 16 KB 3FC000H–3FFFFFH 1FE000H–1FFFFFH

24 KW / 48 KB 3F0000H–3FBFFFH 1F8000H–1FDFFFH

BA62 32 KW / 64 KB 3E0000H–3EFFFFH 1F0000H–1F7FFFH

BA61 32 KW / 64 KB 3D0000H–3DFFFFH 1E8000H–1EFFFFH

BA60 32 KW / 64 KB 3C0000H–3CFFFFH 1E0000H–1E7FFFH

BA59 32 KW / 64 KB 3B0000H–3BFFFFH 1D8000H–1DFFFFH

BA58 32 KW / 64 KB 3A0000H–3AFFFFH 1D0000H–1D7FFFH

BA57 32 KW / 64 KB 390000H–39FFFFH 1C8000H–1CFFFFH

BA56 32 KW / 64 KB 380000H–38FFFFH 1C0000H–1C7FFFH

BA55 32 KW / 64 KB 370000H–37FFFFH 1B8000H–1BFFFFH

BA54 32 KW / 64 KB 360000H–36FFFFH 1B0000H–1B7FFFH

BA53 32 KW / 64 KB 350000H–35FFFFH 1A8000H–1AFFFFH

BA52 32 KW / 64 KB 340000H–34FFFFH 1A0000H–1A7FFFH

BA51 32 KW / 64 KB 330000H–33FFFFH 198000H–19FFFFH

BA50 32 KW / 64 KB 320000H–32FFFFH 190000H–197FFFH

BA49 32 KW / 64 KB 310000H–31FFFFH 188000H–18FFFFH

BA48 32 KW / 64 KB 300000H–30FFFFH 180000H–187FFFH

Bank 2

BA47 32 KW / 64 KB 2F0000H–2FFFFFH 178000H–17FFFFH

BA46 32 KW / 64 KB 2E0000H–2EFFFFH 170000H–177FFFH

BA45 32 KW / 64 KB 2D0000H–2DFFFFH 168000H–16FFFFH

BA44 32 KW / 64 KB 2C0000H–2CFFFFH 160000H–167FFFH

BA43 32 KW / 64 KB 2B0000H–2BFFFFH 158000H–15FFFFH

BA42 32 KW / 64 KB 2A0000H—2AFFFFH 150000H–157FFFH

BA41 32 KW / 64 KB 290000H—29FFFFH 148000H–14FFFFH

BA40 32 KW / 64 KB 280000H—28FFFFH 140000H–147FFFH

BA39 32 KW / 64 KB 270000H—27FFFFH 138000H–13FFFFH

BA38 32 KW / 64 KB 260000H—26FFFFH 130000H–137FFFH

BA37 32 KW / 64 KB 250000H—25FFFFH 128000H–12FFFFH

BA36 32 KW / 64 KB 240000H—24FFFFH 120000H–127FFFH

BA35 32 KW / 64 KB 230000H—23FFFFH 118000H–11FFFFH

BA34 32 KW / 64 KB 220000H—22FFFFH 110000H–117FFFH

BA33 32 KW / 64 KB 210000H—21FFFFH 108000H–10FFFFH

BA32 32 KW / 64 KB 200000H—20FFFFH 100000H–107FFFH

BA31 32 KW / 64 KB 1F0000H—1FFFFFH 0F8000H–0FFFFFH

BA30 32 KW / 64 KB 1E0000H—1EFFFFH 0F0000H–0F7FFFH

BA29 32 KW / 64 KB 1D0000H—1DFFFFH 0E8000H–0EFFFFH

BA28 32 KW / 64 KB 1C0000H—1CFFFFH 0E0000H–0E7FFFH

BA27 32 KW / 64 KB 1B0000H—1BFFFFH 0D8000H–0DFFFFH

BA26 32 KW / 64 KB 1A0000H—1AFFFFH 0D0000H–0D7FFFH

BA25 32 KW / 64 KB 190000H—19FFFFH 0C8000H–0CFFFFH

BA24 32 KW / 64 KB 180000H—18FFFFH 0C0000H–0C7FFFH

BA23 32 KW / 64 KB 170000H—17FFFFH 0B8000H–0BFFFFH

BA22 32 KW / 64 KB 160000H—16FFFFH 0B0000H–0B7FFFH

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 2: Pin Assignments for 48-ball LFBGA (6mm x 8mm)

Bank 2

BA21 32 KW / 64 KB 150000H—15FFFFH 0A8000H–0AFFFFH

BA20 32 KW / 64 KB 140000H—14FFFFH 0A0000H–0A7FFFH

BA19 32 KW / 64 KB 130000H—13FFFFH 098000H–09FFFFH

BA18 32 KW / 64 KB 120000H—12FFFFH 090000H–097FFFH

BA17 32 KW / 64 KB 110000H—11FFFFH 088000H–08FFFFH

BA16 32 KW / 64 KB 100000H—10FFFFH 080000H–087FFFH

BA15 32 KW / 64 KB 0F0000H—0FFFFFH 078000H–07FFFFH

BA14 32 KW / 64 KB 0E0000H—0EFFFFH 070000H–077FFFH

BA13 32 KW / 64 KB 0D0000H—0DFFFFH 068000H–06FFFFH

BA12 32 KW / 64 KB 0C0000H—0CFFFFH 060000H–067FFFH

BA11 32 KW / 64 KB 0B0000H—0BFFFFH 058000H–05FFFFH

BA10 32 KW / 64 KB 0A0000H—0AFFFFH 050000H–057FFFH

BA9 32 KW / 64 KB 090000H—09FFFFH 048000H–04FFFFH

BA8 32 KW / 64 KB 080000H—08FFFFH 040000H–047FFFH

BA7 32 KW / 64 KB 070000H—07FFFFH 038000H–03FFFFH

BA6 32 KW / 64 KB 060000H—06FFFFH 030000H–037FFFH

BA5 32 KW / 64 KB 050000H–05FFFFH 028000H–02FFFFH

BA4 32 KW / 64 KB 040000H–04FFFFH 020000H–027FFFH

BA3 32 KW / 64 KB 030000H–03FFFFH 018000H–01FFFFH

BA2 32 KW / 64 KB 020000H–02FFFFH 010000H–017FFFH

BA1 32 KW / 64 KB 010000H–01FFFFH 008000H–00FFFFH

BA0 32 KW / 64 KB 000000H–00FFFFH 000000H–007FFFH

T3.0 1310

TABLE 3: Dual-Bank Memory Organization (Continued) (2 of 2)

SST34HF324G Block Block Size Address Range x8 Address Range x16

1310 48-lfbga L3K P1a.0

SST34HF324G

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

BES#

A12

RST#

WP#

A17

A14

A10

LBS#

A18

A15

A11

A19

A20

A16

DQ7

DQ5

DQ2

DQ0

UBS#

DQ14

DQ12

DQ10

DQ8

BEF#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 4: Pin Description

Symbol Pin Name Functions

AMS1 to A0Address Inputs To provide Flash address, A20-A0.

To provide SRAM address, A17-A0

DQ15-DQ0Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle.

The outputs are in tri-state when OE#, BES#, and BEF# are high.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0

WP# Write Protect To protect and unprotect the bottom 8 KWord (4 sectors)

from Erase or Program operation

RST# Reset To Reset and return the device to Read mode

VSS Ground

VDD Power Supply 2.7-3.3V Power Supply

T4.0 1310

1. AMS = Most Significant Address

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 5: Operational Modes Selection for SRAM

Mode BEF#1BES#1,2 OE#2WE#2LBS#2UBS#2DQ15-0 DQ15-8

Full Standby VIH VIH X X X X HIGH-Z HIGH-Z HIGH-Z

XXXXX

Output Disable VIH VIL VIH VIH X X HIGH-Z HIGH-Z HIGH-Z

VIL XXV

IH VIH

VIL VIH VIH VIH X X HIGH-Z HIGH-Z HIGH-Z

Flash Read VIL VIH VIL VIH XXD

OUT DOUT DQ15-8=HIGH-Z

Flash Write VIL VIH V

IH VIL XXD

IN DIN DQ15-8=HIGH-Z

Flash Erase VIL VIH V

IH VIL XX X X X

SRAM Read VIH V

IL VIL VIH VIL V

IL DOUT DOUT DOUT

VIH VIL HIGH-Z DOUT DOUT

VIL VIH DOUT HIGH-Z HIGH-Z

SRAM Write VIH VIL XV

IL VIL VIL DIN DIN DIN

VIH VIL HIGH-Z DIN DIN

VIL VIH DIN HIGH-Z HIGH-Z

Product

Identification3

VIL VIH V

IL VIH X X Manufacturer’s ID4

Device ID4

T5.0 1310

1. Do not apply BEF# = VIL and BES# = VIL at the same time

2. X can be VIL or VIH, but no other value.

3. Software mode only

4. With A20-A18 = VIL;SST Manufacturer’s ID = BFH, is read with A0=0,

SST34HF324G Device ID = 7353H, is read with A0=1

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 6: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Program 555H AAH 2AAH 55H 555H A0H WA3Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX450H

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Software ID Entry5555H AAH 2AAH 55H BKX6

555H

90H

Software ID Exit 555H AAH 2AAH 55H 555H F0H

Software ID Exit XXH F0H

T6.0 1310

1. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value, for the command sequence.

2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence

3. WA = Program word address

4. SAX for Sector-Erase; uses A20-A11 address lines

BAX for Block-Erase; uses A20-A15 address lines

BKx for Bank address; uses A20-A15 address lines

5. The device does not remain in Software Product Identification mode if powered down.

6. A20-A18 = VIL

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.3V

Extended -20°C to +85°C 2.7-3.3V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 18 and 19

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 7: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD1

1. See Figure 18

Active VDD Current Address input = VILT/VIHT, at f=5 MHz,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

Flash 15 mA BEF#=VIL, BES#=VIH

SRAM 10 mA BEF#=VIH, BES#=VIL

Concurrent Operation 45 mA BEF#=VIH, BES#=VIL

Write2

2. IDD active while Erase or Program is in progress.

WE#=VIL

Flash 40 mA BEF#=VIL, BES#=VIH, OE#=VIH

SRAM 30 mA BEF#=VIH, BES#=VIL

ISB Standby VDD Current 30 µA VDD = VDD Max, BEF#=BES#=VIHC

IRT Reset VDD Current 30 µA RST#=GND

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILIW Input Leakage Current on

WP# pin and RST# pin

10 µA WP#=GND to VDD, VDD=VDD Max

RST#=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Flash and SRAM Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Flash and SRAM Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T7.0 1310

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 8: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T8.0 1310

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 9: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 20 pF

CIN1Input Capacitance VIN = 0V 16 pF

T9.0 1310

TABLE 10: Flash Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T10.0 1310

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

AC CHARACTERISTICS

TABLE 11: SRAM Read Cycle Timing Parameters

Symbol Parameter Min Max Units

TRCS Read Cycle Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 25 ns

TBYHZS1UBS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T11.0 1310

TABLE 12: SRAM Write Cycle Timing Parameters

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to End-of-Write 60 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 ns

T12.0 1310

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

TABLE 13: Flash Read Cycle Timing Parameters VDD = 2.7-3.3V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1BEF# High to High-Z Output 16 ns

TOHZ1OE# High to High-Z Output 16 ns

TOH1Output Hold from Address Change 0 ns

TRP1,2 RST# Pulse Width 500 ns

TRHR1,2 RST# High Before Read 50 ns

TRY1,2,3 RST# Pin Low to Read 20 µs

T13.0 1310

1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.

2. L3K package only

3. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.

TABLE 14: Flash Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Program Time 12 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 40 ns

TCS WE# and BEF# Setup Time 0 ns

TCH WE# and BEF# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1 BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TES Erase-Suspend Latency 10 µs

TBR1Bus# Recovery Time 1µs

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

T14.1 1310

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 3: SRAM Read Cycle Timing Diagram

FIGURE 4: SRAM Write Cycle Timing Diagram (WE# Controlled)

ADDRESSES

AMSS-0

DQ15-0

UBS#, LBS#

OE#

BES#

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS

TBYES

TBYLZS TBYHZS

DATA VALID

TOHZS

TBHZS

TOHS

1310 F02.0

Note: AMSS = Most Significant Address

AMSS = A17 for SST34HF324G

TAWS

ADDRESSES

AMSS3-0

BES#

WE#

UBS#, LBS#

TWPS TWRS

TWCS

TASTS

TBWS

TBYWS

TODWS TOEWS

TDSS TDHS

1310 F03.0

NOTE 2

DQ15-8, DQ7-0 VALID DATA IN

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES# goes low coincident with or after WE# goes low, the output will remain at high impedance.

If BES# goes high coincident with or before WE# goes high, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A17 for SST34HF324G

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 5: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)

FIGURE 6: Flash Read Cycle Timing Diagram

ADDRESSES

AMSS3-0

WE#

BES#

TBWS

TAWS

TWCS

TWPS TWRS

TASTS TBYWS

DQ15-8, DQ7-0 VALID DATA IN

TDSS TDHS

UBS#, LBS#

1310 F04.0

NOTE 2 NOTE 2

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A17 for SST34HF324G

1310 F05.0

ADDRESS A20-0

DQ15-0

WE#

OE#

BEF#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 7: Flash WE# Controlled Program Cycle Timing Diagram

FIGURE 8: Flash BEF# Controlled Program Cycle Timing Diagram

1310 F06.0

ADDRESS A20-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS?

BEF#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: X can be VIL or VIH, but no other value.

VALID

1310 F07.0

ADDRESS A20-0

DQ15-0

TDH

CPH

TDS

TCP

TAH

TAS

TCH

TCS?

WE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

BEF#

TBP

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 9: Flash Data# Polling Timing Diagram

FIGURE 10: Flash Toggle Bit Timing Diagram

1310 F08.0

ADDRESS A20-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

1310 F09.0

ADDRESS A20-0

DQ6

WE#

OE#

BEF#

TOE

TOEH

TCE

TWO READ CYCLES

WITH SAME OUTPUTS

VALID DATA

TBR

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 11: Flash WE# Controlled Chip-Erase Timing Diagram

FIGURE 12: Flash WE# Controlled Block-Erase Timing Diagram

VALID

1310 F10.0

ADDRESS A

20-0

15-0

WE#

555 2AA 2AA555 555

XX55 XX10XX55XXAA XX80 XXAA

555

OE#

BEF#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

Note: This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.)

X can be VIL or VIH, but no other value.

1310 F11.0

ADDRESS

A20-0

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX30XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

VALID

TBE

Note: This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.)

BAX = Block Address

X can be VIL or VIH, but no other value.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 13: Flash WE# Controlled Sector-Erase Timing Diagram

FIGURE 14: Flash Software ID Entry and Read

1310 F12.0

ADDRESS

20-0

15-0

WE#

555 2AA 2AA555 555

XX55 XX50XX55XXAA XX80 XXAA

OE#

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

VALID

Note: This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.)

SAX = Sector Address

X can be VIL or VIH, but no other value.

1310 F13.0

ADDRESSES

TIDA

DQ15-0

WE#

555 2AA 555 0000 0001

OE#

BEF#

Three-Byte Sequence For Software ID Entry

TWP

TWPH TAA

00BF Device ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value.

Device ID - 7353H for SST34HF324G

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 15: Flash Software ID Exit

1310 F14.0

ADDRESSES

DQ15-0

TIDA

TWP

TWPH

WE#

555 2AA 555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 16: RST# Timing (when no internal operation is in progress)

FIGURE 17: RST# Timing (during Sector- or Block-Erase operation)

1310 F15.0

RY/BY#

RST#

BEF#/OE#

TRP

RHR

1310 F16.0

RY/BY#

BEF#

OE#

TRP

TRY

TBR

RST#

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 18: AC Input/Output Reference Waveforms

FIGURE 19: A Test Load Example

1310 F17.0

REFERENCE POINTS OUTPUTINPUT? VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te st

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1310 F18.0

TO TESTER

TO DUT

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 20: Program Algorithm

1310 F19.0

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load

Address/Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 21: Wait Options

1310 F20.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte/word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read

byte/word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 22: Software Product ID Command Flowcharts

1310 F21.0

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

Software ID Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Wait TIDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

FIGURE 23: Erase Command Sequence

1310 F22.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

PRODUCT ORDERING INFORMATION

Valid combinations for SST34HF324G

SST34HF324G-70-4C-L3KE

SST34HF324G-70-4E-L3KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Package Attribute

E1 = non-Pb

Package Modifier

K = 48 balls

Package Type

L3 = LFBGA (6mm x 8mm x 1.4mm, 0.45mm ball size)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 =10,000 cycles

Read Access Speed

70 = 70 ns

Version

G = Flash WP# and RST# + SRAM

SRAM Density

4 = 4 Mbit

Flash Density

32 = 32Mbit

Voltage

H = 2.7-3.3V

Product Series

34 = Dual-Bank Flash + SRAM ComboMemory

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

Device Speed Suffix1 Suffix2

SST34HF324G - XXX -XX-XXXX

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EOL Data Sheet

32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

SST34HF324G

PACKAGING DIAGRAMS

48-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 6mm x 8mm

SST Package Code: L3K

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.30 ± 0.10

0.12

0.80

4.00

0.80

5.60

48-lfbga-L3K-6x8-450mic-5

Note: 1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1',

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

0.45 ± 0.05

(48X)

A1 CORNER

6.00 ± 0.20

A1 CORNER

8.00 ± 0.20

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

TABLE 15: Revision History

Number Description Date

00 •Initial Release Jun 2006

01 •Changed ‘Program Time: 7 µs’ to ‘Word-Program Time: 7 µs’ on page 1, Features

•Edited Product Description on page 1

Aug 2007

02 •EOL all valid combinations in this data sheet.

Replacement part SST34HF3244 (S71335)

Dec 2007

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