32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory EOL Data Sheet FEATURES: * Flash Organization: 2M x16 - 32 Mbit: 24Mbit + 8Mbit * Concurrent Operation - Read from or Write to SRAM while Erase/Program Flash * SRAM Organization: - 4 Mbit: 256K x16 * Single 2.7-3.3V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: (typical values @ 5 MHz) - Active Current: Flash 10 mA (typical) SRAM 6 mA (typical) - Standby Current: 10 A (typical) * Hardware Sector Protection (WP#) - Protects 4 outer most sectors (8 KWord) in the smaller bank by holding WP# low and unprotects by holding WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading data array * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Read Access Time - Flash: 70 ns - SRAM: 70 ns * Erase-Suspend / Erase-Resume Capabilities * Latched Address and Data * Fast Erase and Word-Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 35 ms - Word-Program Time: 7 s * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Packages Available - 48-ball LFBGA (6mm x 8mm) * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST34HF324G ComboMemory integrates a 2M x16 CMOS flash memory bank with 256K x16 CMOS SRAM memory bank in a multi-chip package (MCP). This device is fabricated using SST proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF324G is ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF324G devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 12/07 1 Word-Program time of 7 sec. To protect against inadvertent flash write, the SST34HF324G devices contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES#, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. See Table 3 for memory organization. Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF324G are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 2 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. http://store.iiic.cc/ 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Device Operation Flash Program Operation The SST34HF324G use BES# and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES# is low the SRAM is activated for Read and Write operation. BEF# and BES# cannot be at low level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES# bank enables are raised to VIHC (Logic High) or when BEF# is high. These devices are programmed on a word-by-word basis. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. Concurrent Read/Write Operation 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 s. The SST34HF324G provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Concurrent Read/Write State Table Flash Program/Erase Program/Erase SRAM Read Write The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Flash Sector- /Block-Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or SectorErase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 12 and 13 for timing waveforms. Flash Read Operation The Read operation of the SST34HF324G is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 2 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Flash Chip-Erase Operation The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. The SST34HF324G provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the "1" state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 6 for the command sequence, Figure 11 for timing diagram, and Figure 23 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Flash Data# Polling (DQ7) When the device is in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling (DQ7) timing diagram and Figure 21 for a flowchart. Flash Erase-Suspend/-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the one-byte sequence. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. Flash Write Operation Status Detection The SST34HF324G provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 21 for a flowchart. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 3 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Hardware Reset (RST#) TABLE 1: Write Operation Status Status Normal Operation EraseSuspend Mode DQ7 DQ6 DQ2 Standard Program DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Read From Erase Suspended Sector/ Block 1 1 Toggle Read From Non-Erase Suspended Sector/ Block Data Data Data Program DQ7# Toggle No Toggle The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 17). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 16). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 16 and 17 for timing diagrams. Software Data Protection (SDP) The SST34HF324G provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF324G are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 are "Don't Care" during any SDP command sequence. T1.0 1310 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. Data Protection The SST34HF324G provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The SST34HF324G provide a hardware block protection which protects the outermost 8 KWord in Bank 1. The block is protected when WP# is held low. See Figure 3 for BlockProtection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 4 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Product Identification SRAM Operation The Product Identification mode identifies the device as SST34HF324G and the manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 5 and 6 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 22 for the ID Entry command sequence flowchart. With BES# low and BEF# high, the SST34HF324G operates as either 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. When BES# and BEF# are high, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 5 for SRAM Read and Write data byte control modes of operation. SRAM Read The SRAM Read operation of the SST34HF324G is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. TABLE 2: Product Identification ADDRESS DATA BK0000H 00BFH BK0001H 7353H Manufacturer's ID Device ID SST34HF324G SRAM Write T2.0 1310 The SRAM Write operation of the SST34HF324G is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE# whichever occurs first. The write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. Note: BK = Bank Address (A20-A18) Product Identification Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 15 for timing waveform and Figure 22 for a flowchart. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 5 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Address Buffers A20- A0 WP# RST# BEF# LBS# UBS# WE# OE# BES# SuperFlash Memory (Bank 1) SuperFlash Memory (Bank 2) Control Logic I/O Buffers Address Buffers DQ15 - DQ0 4 Mbit SRAM 1310 B1.0 FIGURE 1: Functional Block Diagram (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 6 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 3: Dual-Bank Memory Organization (1 of 2) SST34HF324G Block BA63 BA62 Bank 1 Bank 2 Block Size Address Range x8 Address Range x16 8 KW / 16 KB 3FC000H-3FFFFFH 1FE000H-1FFFFFH 24 KW / 48 KB 3F0000H-3FBFFFH 1F8000H-1FDFFFH 32 KW / 64 KB 3E0000H-3EFFFFH 1F0000H-1F7FFFH BA61 32 KW / 64 KB 3D0000H-3DFFFFH 1E8000H-1EFFFFH BA60 32 KW / 64 KB 3C0000H-3CFFFFH 1E0000H-1E7FFFH BA59 32 KW / 64 KB 3B0000H-3BFFFFH 1D8000H-1DFFFFH BA58 32 KW / 64 KB 3A0000H-3AFFFFH 1D0000H-1D7FFFH BA57 32 KW / 64 KB 390000H-39FFFFH 1C8000H-1CFFFFH BA56 32 KW / 64 KB 380000H-38FFFFH 1C0000H-1C7FFFH BA55 32 KW / 64 KB 370000H-37FFFFH 1B8000H-1BFFFFH BA54 32 KW / 64 KB 360000H-36FFFFH 1B0000H-1B7FFFH BA53 32 KW / 64 KB 350000H-35FFFFH 1A8000H-1AFFFFH BA52 32 KW / 64 KB 340000H-34FFFFH 1A0000H-1A7FFFH BA51 32 KW / 64 KB 330000H-33FFFFH 198000H-19FFFFH BA50 32 KW / 64 KB 320000H-32FFFFH 190000H-197FFFH BA49 32 KW / 64 KB 310000H-31FFFFH 188000H-18FFFFH BA48 32 KW / 64 KB 300000H-30FFFFH 180000H-187FFFH BA47 32 KW / 64 KB 2F0000H-2FFFFFH 178000H-17FFFFH BA46 32 KW / 64 KB 2E0000H-2EFFFFH 170000H-177FFFH BA45 32 KW / 64 KB 2D0000H-2DFFFFH 168000H-16FFFFH BA44 32 KW / 64 KB 2C0000H-2CFFFFH 160000H-167FFFH BA43 32 KW / 64 KB 2B0000H-2BFFFFH 158000H-15FFFFH BA42 32 KW / 64 KB 2A0000H--2AFFFFH 150000H-157FFFH BA41 32 KW / 64 KB 290000H--29FFFFH 148000H-14FFFFH BA40 32 KW / 64 KB 280000H--28FFFFH 140000H-147FFFH BA39 32 KW / 64 KB 270000H--27FFFFH 138000H-13FFFFH BA38 32 KW / 64 KB 260000H--26FFFFH 130000H-137FFFH BA37 32 KW / 64 KB 250000H--25FFFFH 128000H-12FFFFH BA36 32 KW / 64 KB 240000H--24FFFFH 120000H-127FFFH BA35 32 KW / 64 KB 230000H--23FFFFH 118000H-11FFFFH BA34 32 KW / 64 KB 220000H--22FFFFH 110000H-117FFFH BA33 32 KW / 64 KB 210000H--21FFFFH 108000H-10FFFFH BA32 32 KW / 64 KB 200000H--20FFFFH 100000H-107FFFH BA31 32 KW / 64 KB 1F0000H--1FFFFFH 0F8000H-0FFFFFH BA30 32 KW / 64 KB 1E0000H--1EFFFFH 0F0000H-0F7FFFH BA29 32 KW / 64 KB 1D0000H--1DFFFFH 0E8000H-0EFFFFH BA28 32 KW / 64 KB 1C0000H--1CFFFFH 0E0000H-0E7FFFH BA27 32 KW / 64 KB 1B0000H--1BFFFFH 0D8000H-0DFFFFH BA26 32 KW / 64 KB 1A0000H--1AFFFFH 0D0000H-0D7FFFH BA25 32 KW / 64 KB 190000H--19FFFFH 0C8000H-0CFFFFH BA24 32 KW / 64 KB 180000H--18FFFFH 0C0000H-0C7FFFH BA23 32 KW / 64 KB 170000H--17FFFFH 0B8000H-0BFFFFH BA22 32 KW / 64 KB 160000H--16FFFFH 0B0000H-0B7FFFH (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 7 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 3: Dual-Bank Memory Organization (Continued) (2 of 2) SST34HF324G Bank 2 Block Block Size Address Range x8 Address Range x16 BA21 32 KW / 64 KB 150000H--15FFFFH 0A8000H-0AFFFFH BA20 32 KW / 64 KB 140000H--14FFFFH 0A0000H-0A7FFFH BA19 32 KW / 64 KB 130000H--13FFFFH 098000H-09FFFFH BA18 32 KW / 64 KB 120000H--12FFFFH 090000H-097FFFH BA17 32 KW / 64 KB 110000H--11FFFFH 088000H-08FFFFH BA16 32 KW / 64 KB 100000H--10FFFFH 080000H-087FFFH BA15 32 KW / 64 KB 0F0000H--0FFFFFH 078000H-07FFFFH BA14 32 KW / 64 KB 0E0000H--0EFFFFH 070000H-077FFFH BA13 32 KW / 64 KB 0D0000H--0DFFFFH 068000H-06FFFFH BA12 32 KW / 64 KB 0C0000H--0CFFFFH 060000H-067FFFH BA11 32 KW / 64 KB 0B0000H--0BFFFFH 058000H-05FFFFH BA10 32 KW / 64 KB 0A0000H--0AFFFFH 050000H-057FFFH BA9 32 KW / 64 KB 090000H--09FFFFH 048000H-04FFFFH BA8 32 KW / 64 KB 080000H--08FFFFH 040000H-047FFFH BA7 32 KW / 64 KB 070000H--07FFFFH 038000H-03FFFFH BA6 32 KW / 64 KB 060000H--06FFFFH 030000H-037FFFH BA5 32 KW / 64 KB 050000H-05FFFFH 028000H-02FFFFH BA4 32 KW / 64 KB 040000H-04FFFFH 020000H-027FFFH BA3 32 KW / 64 KB 030000H-03FFFFH 018000H-01FFFFH BA2 32 KW / 64 KB 020000H-02FFFFH 010000H-017FFFH BA1 32 KW / 64 KB 010000H-01FFFFH 008000H-00FFFFH BA0 32 KW / 64 KB 000000H-00FFFFH 000000H-007FFFH T3.0 1310 TOP VIEW (balls facing down) 6 5 A13 A12 A14 A15 A16 UBS# DQ15 VSS A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# LBS# A19 DQ5 DQ12 VDD DQ4 BES# WP# 4 3 A18 A20 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 DQ9 DQ1 2 A7 A17 A6 A5 A3 A4 A2 A1 A0 A B C D E 1 BEF# OE# VSS F G 1310 48-lfbga L3K P1a.0 SST34HF324G H FIGURE 2: Pin Assignments for 48-ball LFBGA (6mm x 8mm) (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 8 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 4: Pin Description Symbol Pin Name Functions AMS1 to A0 Address Inputs To provide Flash address, A20-A0. To provide SRAM address, A17-A0 DQ15-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE#, BES#, and BEF# are high. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0 WP# Write Protect To protect and unprotect the bottom 8 KWord (4 sectors) from Erase or Program operation RST# Reset To Reset and return the device to Read mode VSS Ground VDD Power Supply 2.7-3.3V Power Supply T4.0 1310 1. AMS = Most Significant Address (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 9 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 5: Operational Modes Selection for SRAM BEF#1 BES#1,2 OE#2 WE#2 LBS#2 UBS#2 DQ15-0 Full Standby VIH VIH X X X X HIGH-Z HIGH-Z HIGH-Z X X X X X Output Disable VIH VIL VIH VIH X X HIGH-Z HIGH-Z HIGH-Z VIL X X VIH VIH VIL VIH VIH VIH X X HIGH-Z HIGH-Z HIGH-Z Flash Read VIL VIH VIL VIH X X DOUT DOUT DQ15-8=HIGH-Z Flash Write VIL VIH VIH VIL X X DIN DIN DQ15-8=HIGH-Z Flash Erase VIL VIH VIH VIL X X X X X SRAM Read VIH VIL VIL VIH VIL VIL DOUT DOUT DOUT VIH VIL HIGH-Z DOUT DOUT VIL VIH DOUT HIGH-Z HIGH-Z Mode DQ15-8 X X X X SRAM Write Product Identification3 VIH VIL VIL VIH X VIL VIL VIL VIL DIN DIN DIN VIH VIL HIGH-Z DIN DIN VIL VIH DIN HIGH-Z HIGH-Z X X VIH Manufacturer's ID4 Device ID4 T5.0 1310 1. 2. 3. 4. Do not apply BEF# = VIL and BES# = VIL at the same time X can be VIL or VIH, but no other value. Software mode only With A20-A18 = VIL; SST Manufacturer's ID = BFH, is read with A0=0, SST34HF324G Device ID = 7353H, is read with A0=1 (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 10 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 6: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Program 555H AAH 2AAH 55H 555H A0H WA3 Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAH 55H SAX4 50H 4 30H 10H Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H 555H AAH 2AAH 55H BKX6 555H 90H Software ID Exit 555H AAH 2AAH 55H 555H F0H Software ID Exit XXH F0H Software ID Entry5 T6.0 1310 1. 2. 3. 4. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value, for the command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence WA = Program word address SAX for Sector-Erase; uses A20-A11 address lines BAX for Block-Erase; uses A20-A15 address lines BKx for Bank address; uses A20-A15 address lines 5. The device does not remain in Software Product Identification mode if powered down. 6. A20-A18 = VIL Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range Range Commercial Extended Ambient Temp VDD 0C to +70C 2.7-3.3V -20C to +85C 2.7-3.3V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 18 and 19 (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 11 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 7: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V) Limits Symbol Parameter IDD1 Active VDD Current Min Max Units Test Conditions Address input = VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open Read OE#=VIL, WE#=VIH Flash 15 mA BEF#=VIL, BES#=VIH SRAM 10 mA BEF#=VIH, BES#=VIL 45 mA Concurrent Operation Write2 BEF#=VIH, BES#=VIL WE#=VIL Flash 40 mA BEF#=VIL, BES#=VIH, OE#=VIH SRAM 30 mA BEF#=VIH, BES#=VIL ISB Standby VDD Current 30 A VDD = VDD Max, BEF#=BES#=VIHC IRT Reset VDD Current 30 A RST#=GND ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILIW Input Leakage Current on WP# pin and RST# pin 10 A WP#=GND to VDD, VDD=VDD Max RST#=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7 VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOL Flash and SRAM Output Low Voltage VOH Flash and SRAM Output High Voltage 0.2 VDD-0.2 V VDD=VDD Max V IOL=100 A, VDD=VDD Min V IOH=-100 A, VDD=VDD Min T7.0 1310 1. See Figure 18 2. IDD active while Erase or Program is in progress. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 12 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 8: Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 s Power-up to Write Operation 100 s TPU-WRITE 1 T8.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: Capacitance (Ta = 25C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 20 pF Input Capacitance VIN = 0V 16 pF CIN 1 T9.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Flash Reliability Characteristics Symbol NEND 1 Parameter Minimum Specification Units Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up Test Method JEDEC Standard 78 T10.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 13 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet AC CHARACTERISTICS TABLE 11: SRAM Read Cycle Timing Parameters Symbol Parameter Min 70 Max Units TRCS Read Cycle Time TAAS Address Access Time 70 ns TBES Bank Enable Access Time 70 ns TOES Output Enable Access Time 35 ns TBYES UBS#, LBS# Access Time 70 ns TBLZS1 BES# to Active Output 0 ns TOLZS1 Output Enable to Active Output 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 ns TBHZS 1 TOHZS1 TBYHZS 1 TOHS ns BES# to High-Z Output 25 ns Output Disable to High-Z Output 25 ns 35 ns UBS#, LBS# to High-Z Output Output Hold from Address Change 10 ns T11.0 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: SRAM Write Cycle Timing Parameters Symbol Parameter Min TWCS Write Cycle Time 70 Max Units TBWS Bank Enable to End-of-Write 60 ns TAWS Address Valid to End-of-Write 60 ns TASTS Address Set-up Time 0 ns TWPS Write Pulse Width 60 ns TWRS Write Recovery Time 0 ns TBYWS UBS#, LBS# to End-of-Write 60 ns TODWS Output Disable from WE# Low TOEWS Output Enable from WE# High 0 ns TDSS Data Set-up Time 30 ns TDHS Data Hold from Write Time 0 ns 30 ns ns T12.0 1310 (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 14 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TABLE 13: Flash Read Cycle Timing Parameters VDD = 2.7-3.3V Symbol Parameter Min TRC Read Cycle Time 70 TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time TCLZ1 BEF# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 BEF# High to High-Z Output TOHZ1 OE# High to High-Z Output TOH1 Output Hold from Address Change TRP 1,2 TRHR1,2 TRY 1,2,3 Max Units ns 35 ns ns ns 16 ns 16 ns 0 ns RST# Pulse Width 500 ns RST# High Before Read 50 ns RST# Pin Low to Read 20 s T13.0 1310 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 2. L3K package only 3. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase. TABLE 14: Flash Program/Erase Cycle Timing Parameters Symbol Parameter TBP Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 40 ns TCS WE# and BEF# Setup Time 0 ns TCH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH 1 Min Max Units 12 s WE# Pulse Width High 30 ns TCPH1 BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 ns TIDA 1 TES TBR 1 Software ID Access and Exit Time 150 ns Erase-Suspend Latency 10 s Bus# Recovery Time 1 s TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T14.1 1310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 15 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TRCS ADDRESSES AMSS-0 TOHS TAAS TBES BES# TBLZS TBHZS TOES OE# TOLZS TOHZS TBYES UBS#, LBS# TBYLZS TBYHZS DQ15-0 DATA VALID 1310 F02.0 Note: AMSS = Most Significant Address AMSS = A17 for SST34HF324G FIGURE 3: SRAM Read Cycle Timing Diagram TWCS ADDRESSES AMSS3-0 TASTS TWPS TWRS WE# TAWS TBWS BES# TBYWS UBS#, LBS# TODWS DQ15-8, DQ7-0 TDSS NOTE 2 TOEWS TDHS VALID DATA IN NOTE 2 1310 F03.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES# goes low coincident with or after WE# goes low, the output will remain at high impedance. If BES# goes high coincident with or before WE# goes high, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST34HF324G FIGURE 4: SRAM Write Cycle Timing Diagram (WE# Controlled) (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 16 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TWCS ADDRESSES AMSS3-0 TWPS TWRS WE# TBWS BES# TAWS TASTS TBYWS UBS#, LBS# TDSS VALID DATA IN NOTE 2 DQ15-8, DQ7-0 TDHS NOTE 2 1310 F04.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST34HF324G FIGURE 5: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled) TRC TAA ADDRESS A20-0 TCE BEF# TOE OE# VIH TOHZ TOLZ WE# DQ15-0 HIGH-Z TOH TCLZ DATA VALID TCHZ HIGH-Z DATA VALID 1310 F05.0 FIGURE 6: Flash Read Cycle Timing Diagram (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 17 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TBP 555 TAH ADDRESS A20-0 2AA 555 ADDR TWP WE# TWPH TAS OE# TCH BEF# TCS? TDS TDH DQ15-0 XXAA XX55 XXA0 VALID DATA WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. 1310 F06.0 FIGURE 7: Flash WE# Controlled Program Cycle Timing Diagram TBP 555 TAH ADDRESS A20-0 2AA 555 ADDR TCP BEF# TAS TCPH OE# TCH WE# TDS TCS? TDH DQ15-0 XXAA XX55 XXA0 DATA VALID WORD (ADDR/DATA) Note: X can be VIL or VIH, but no other value. 1310 F07.0 FIGURE 8: Flash BEF# Controlled Program Cycle Timing Diagram (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 18 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet ADDRESS A20-0 TCE BEF# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1310 F08.0 FIGURE 9: Flash Data# Polling Timing Diagram ADDRESS A20-0 TCE BEF# TOEH TOE OE# WE# TBR DQ6 VALID DATA TWO READ CYCLES WITH SAME OUTPUTS 1310 F09.0 FIGURE 10: Flash Toggle Bit Timing Diagram (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 19 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE 555 ADDRESS A20-0 2AA 555 555 2AA 555 BEF# OE# TWP WE# XXAA DQ15-0 XX55 XX80 XXAA XX55 XX10 VALID 1310 F10.0 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.) X can be VIL or VIH, but no other value. FIGURE 11: Flash WE# Controlled Chip-Erase Timing Diagram TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A20-0 555 2AA 555 555 2AA BAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 1310 F11.0 Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 12: Flash WE# Controlled Block-Erase Timing Diagram (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 20 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A20-0 555 2AA 555 555 TSE 2AA SAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1310 F12.0 Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 14.) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 13: Flash WE# Controlled Sector-Erase Timing Diagram Three-Byte Sequence For Software ID Entry ADDRESSES 555 2AA 555 0000 0001 BEF# OE# TIDA TWP WE# TWPH XXAA DQ15-0 XX55 TAA XX90 00BF Device ID 1310 F13.0 Note: X can be VIL or VIH, but no other value. Device ID - 7353H for SST34HF324G FIGURE 14: Flash Software ID Entry and Read (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 21 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESSES 555 DQ15-0 2AA XXAA 555 XX55 XXF0 TIDA CE# OE# TWP WE# TWPH 1310 F14.0 Note: X can be VIL or VIH, but no other value. FIGURE 15: Flash Software ID Exit (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 22 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet RY/BY# 0V TRP RST# BEF#/OE# TRHR 1310 F15.0 FIGURE 16: RST# Timing (when no internal operation is in progress) TRY RY/BY# RST# TRP BEF# TBR OE# 1310 F16.0 FIGURE 17: RST# Timing (during Sector- or Block-Erase operation) (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 23 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet VIHT INPUT? VIT REFERENCE POINTS VOT OUTPUT VILT 1310 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 18: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1310 F18.0 FIGURE 19: A Test Load Example (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 24 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Address/Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1310 F19.0 Note: X can be VIL or VIH, but no other value. FIGURE 20: Program Algorithm (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 25 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Read byte/word Read DQ7 Wait TBP, TSCE, TSE or TBE Read same byte/word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1310 F20.0 FIGURE 21: Wait Options (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 26 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Software Product ID Entry Command Sequence Software ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX90H Address: 555 Load data: XXF0H Address: 555H Wait TIDA Wait TIDA Read Software ID Return to normal operation 1310 F21.0 Note: X can be VIL or VIH, but no other value. FIGURE 22: Software Product ID Command Flowcharts (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 27 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1310 F22.0 Note: X can be VIL or VIH, but no other value. FIGURE 23: Erase Command Sequence (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 28 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet PRODUCT ORDERING INFORMATION Device Speed SST34HF324G - XXX Suffix1 - XX Suffix2 - XXXX Package Attribute E1 = non-Pb Package Modifier K = 48 balls Package Type L3 = LFBGA (6mm x 8mm x 1.4mm, 0.45mm ball size) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 =10,000 cycles Read Access Speed 70 = 70 ns Version G = Flash WP# and RST# + SRAM SRAM Density 4 = 4 Mbit Flash Density 32 = 32Mbit Voltage H = 2.7-3.3V Product Series 34 = Dual-Bank Flash + SRAM ComboMemory 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST34HF324G SST34HF324G-70-4C-L3KE SST34HF324G-70-4E-L3KE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 29 http://store.iiic.cc/ 12/07 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G EOL Data Sheet PACKAGING DIAGRAMS TOP VIEW BOTTOM VIEW 8.00 0.20 5.60 0.45 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 0.20 3 3 2 2 1 1 0.80 H G F E D C B A A B C D E F G H A1 CORNER SIDE VIEW A1 CORNER 1.30 0.10 0.12 SEATING PLANE 1mm 0.35 0.05 Note: 1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-lfbga-L3K-6x8-450mic-5 48-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) 6mm x 8mm SST Package Code: L3K TABLE 15: Revision History Number Description Date 00 * Initial Release Jun 2006 01 * * Changed `Program Time: 7 s' to `Word-Program Time: 7 s' on page 1, Features Edited Product Description on page 1 Aug 2007 02 * EOL all valid combinations in this data sheet. Replacement part SST34HF3244 (S71335) Dec 2007 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2007 Silicon Storage Technology, Inc. S71310-02-EOL 30 http://store.iiic.cc/ 12/07