IRF240 Data Sheet March 1999 18A, 200V, 0.180 Ohm, N-Channel Power MOSFET * 18A, 200V Formerly developmental type TA17422. Ordering Information PACKAGE 1584.3 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number * rDS(ON) = 0.180 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND D IRF240 TO-204AE IRF240 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-204AE TOP VIEW DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF240 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF240 200 200 18 11 72 20 125 1.0 580 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250A (Figure 10) 200 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 2.0 - 4.0 V - - 25 A - - 250 A 18 - - A Zero Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage IGSS Drain to Source On Resistance rDS(ON) Forward Transconductance (Note 2) Turn-On Delay Time gfs tD(ON) Rise Time tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V - - 100 nA VGS = 10V, ID = 10A (Figures 8, 9) - 0.14 0.180 6.7 9.0 - S - 16 30 ns - 27 60 ns - 40 80 ns - 31 60 ns - 43 60 nC - 8 - nC - 27 - nC - 1275 - pF VDS = 10V, ID = 11V (Figure 12) VDD = 100V, ID 18A, RG = 9.1, RL = 5.3 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature tD(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Qg Gate to Source Charge Qgs VGS = 10V, ID = 18A, VDS = 0.8 x Rated BVDSS , Ig(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS - 500 - pF Reverse-Transfer Capacitance CRSS - 160 - pF - 5.0 - nH - 12.5 - nH - - 1.0 oC/W - - 30 oC/W Internal Drain Inductance LD Internal Source Inductance LS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured between the Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA 2 Free Air Operation IRF240 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current TEST CONDITIONS ISD Pulse Source to Drain Current (Note 3) Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISM MIN TYP MAX UNITS - - 18 A - - 72 A - - 2.0 V - 650 - ns - 4.1 - C D G S Source to Drain Diode Voltage (Note 2) TJ = 25oC, ISD = 18A, VGS = 0V (Figure 13) TJ = 150oC, ISD = 18A, dISD/dt = 100A/s TJ = 150oC, ISD = 18A, dISD/dt = 100A/s VSD Reverse Recovery Time trr Reverse Recovered Charge QRR NOTES: 2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 2.7mH, RG = 25, peak IAS = 9A. See Figures 15 and 16. Typical Performance Curves Unless Otherwise Specified 20 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 16 12 8 4 0 0 50 100 25 150 50 TC , CASE TEMPERATURE (oC) 75 125 100 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZJC, THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 PDM 0.1 0.1 0.05 t1 t2 t2 0.02 0.01 0.01 10-5 NOTES: DUTY FACTOR: D = t1/t2 PER UNIT BASE = RJC = 1.0oCW TJM - TC = PDM x ZJC (t) SINGLE PULSE 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRF240 Typical Performance Curves Unless Otherwise Specified (Continued) 100 40 10V 8V 80s PULSE TEST 10s 100s ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 9V 10 1ms OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 1 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 1.0 32 7V 24 16 VGS = 6V 8 5V 4V 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 103 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 40 40 32 24 TJ = -55oC ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) FIGURE 5. OUTPUT CHARACTERISTICS VGS = 10V VGS = 9V VGS = 8V 80s PULSE TEST 50 VGS = 7V 16 VGS = 6V 8 VGS = 5V TJ = 25oC 32 TJ = 125oC 24 VDS > ID(ON) x RDS(ON)MAX 80s PULSE TEST 16 8 VGS = 4V 0 0 1 2 3 4 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 5 0 FIGURE 6. SATURATION CHARACTERISTICS 2 4 6 8 VSD , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS 0.5 2.5 80s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE ON RESISTANCE () rDS(ON), DRAIN TO SOURCE ID = 18A 0.4 VGS = 10V 0.3 0.2 VGS = 20V 0.1 VGS = 10V 2.0 1.5 1.0 0.5 0 0 20 60 40 ID , DRAIN CURRENT (A) 80 100 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRF240 Typical Performance Curves (Continued) 2000 ID = 250A 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS 1800 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified 1.05 0.95 0.85 1200 CISS 800 COSS CRSS 400 0.75 -40 0 40 80 120 0 160 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 19.0 50 15.2 ISD, SOURCE TO DRAIN CURRENT (A) 80s PULSE TEST TJ = -55oC TJ = 25oC 11.4 TJ = 125oC 7.6 3.8 20 10 0 8 16 24 ID , DRAIN CURRENT (A) 32 40 TJ = 150oC 5 TJ = 25oC 2 1 0 0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0.4 0.8 1.2 1.6 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 50 ID = 18A 16 VDS = 40V 12 VDS = 100V VDS = 160V 8 4 0 0 12 24 36 48 60 Qg , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 2.0 IRF240 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr VDS RL 90% 90% + RG - VDD 10% 10% 0 90% DUT VGS VGS 0 10% VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0.2F 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G Ig(REF) 0 S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 Ig(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF240 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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