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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 1©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Features
Mobile LPDDR (only)
152-Ball Package-on-Package (PoP) TI-OMAP™
MT46HxxxMxxLxCG
MT46HxxxMxxLxKZ
Features
•V
DD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pi pelined double data rate (DDR)
architecture; 2 data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands enter ed on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
per byte
• Programmable burst lengths (BLs): 2, 4, 8, or 161
• Concurr ent auto precharge option is supported
• Auto refres h and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PAS R)
• Deep power-down (DPD)
• STATUS REGISTER READ (SRR) supported2
• Selectable output drive strength (DS)
• Clock stop cap abi lity
• 64ms refresh Notes: 1. BL 16: contact factory for availability.
2. Contact factory for remapped SRR output.
Options Marking
•V
DD/VDDQ
–1.8V/1.8V H
• Configuration
–128 Meg x 32 (16 Meg x 16 x 4 banks x 4)
–64 Meg x 32 (8 Meg x 32 x 4 banks x 2)
–32 M eg x 32 (8 Meg x 32 x 4 banks)
–16 M eg x 32 (4 Meg x 32 x 4 banks)
128M32
64M32
32M32
16M32
•Device version
–Single die, standard addressing
–2-die stack, standard addressing
–4-die stack, standard addressing
LF
L2
L4
•Plastic “green” package
–152-ball VFBGA (14 x 14 x 1.0mm)
–152-ball VFBGA (14 x 14 x 1.2mm) CG
KZ
• Timing – cycle time
–5ns @ CL = 3
–5.4ns @ CL = 3
–6ns @ CL = 3
-5
-54
-6
• Operating temper ature range
–Commercial (0°C to +70°C)
–Industrial (–40°C to +85°C) None
IT
Notes: 1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bit-
wide bus.
Table 1: Configuration Addressing
Architecture 128 Meg x 32164 Meg x 32 32 Meg x 32 16 Meg x 32
Configuration 16 Meg x 16
x 4 banks x 4 die 8 Meg x 32
x 4 banks x 2 die 8 Meg x 32
x 4 banks 4 Meg x 32
x 4 banks
Refresh count 8K 8K 8K 8K
Row addr ess ing 16K (A[13:0]) 8K (A[12:0]) 8K (A[12:0]) 8K (A[12:0])
Column addressing 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) 512 (A[8:0])
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 2©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Part Numbering Information – 152-Ball PoP
Part Numbering Information – 152-Ball PoP
Micron® 152-ball packaged LPDDR devices are available in several configurations.
Figure 1: Marketing Part Number Example
Micron Technology
Product Family
46 = LPDDR-SDRAM
Operating Voltage
H = 1.8V/1.8V
Configuration
128 Meg x 32
64 Meg x 32
32 Meg x 32
16 Meg x 32
Device Version
LF = Single die, standard addressing
L2 = 2-die stack, standard addressing
L4 = Quad die, standard addressing
Design Revision
:A = First generation
:B = Second generation
Operating Temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Cycle Time
-5 = 5ns
tCK CL = 3
-54 = 5.4ns tCK CL = 3
-6 = 6ns
tCK CL = 3
Package Code
CG = 152-ball (14 x 14 x 1.0mm) VFBGA
KZ = 152-ball (14 x 14 x 1.2mm) VFBGA
MT 46 H 32M32 LF CG -6 IT :A
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 3©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Device Marking
Device Marking Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-refer enced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To
view the location of the ab breviated m ark o n th e de vic e, refer to customer ser vice note
CSN-11, “Product Mark/Label,” at www.micron.com/csn.
Table 2: 152-Ball Production Marketing Part Numbers
Part Numbers LPDDR Product Physical Part Marking
MT46H16M32LFCG-5:B 512Mb DDR, x32, 200 MHz D9KTK
MT46H16M32LFCG-5 IT:B 512Mb DDR, x32, 200 MHz D9KTL
MT46H16M32LFCG-54:B 512Mb DDR, x32, 185 MHz D9KTM
MT46H16M32LFCG-54 IT:B 512Mb DDR, x32, 185 MHz D9KTN
MT46H16M32LFCG-6:B 512Mb DDR, x32, 166 MHz D9KGX
MT46H16M32LFCG-6 IT:B 512Mb DDR, x32, 166 MHz D9KGZ
MT46H32M32LFCG-5:A 1Gb DDR, x32, 200 MHz D9KTP
MT46H32M32LFCG-5 IT:A 1Gb DDR, x32, 200 MHz D9KLD
MT46H32M32LFCG-54:A 1Gb DDR, x32, 185 MHz D9KTQ
MT46H32M32LFCG-54 IT:A 1Gb DDR, x32, 185 MHz D9KTR
MT46H32M32LFCG-6:A 1Gb DDR, x32, 166 MHz D9KHL
MT46H32M32LFCG-6 IT:A 1Gb DDR, x32, 166 MHz D9JZJ
MT46H64M32L2CG-5:A 2 x 1Gb DDR, x32, 200 MHz D9KTS
MT46H64M32L2CG-5 IT:A 2 x 1Gb DDR, x32, 200 MHz D9KLF
MT46H64M32L2CG-54:A 2 x 1Gb DDR, x32, 185 MHz D9KTV
MT46H64M32L2CG-54 IT:A 2 x 1Gb DDR, x32, 185 MHz D9KTW
MT46H64M32L2CG-6:A 2 x 1Gb DDR, x32, 166 MHz D9KJV
MT46H64M32L2CG-6 IT:A 2 x 1Gb DDR, x32, 166 MHz D9KFJ
MT46H128M32L4KZ-6 IT ES:A 4 × 1Gb DDR, x32, 166 MHz Z9KZL
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 4©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
General Description
General Description
Micron 152-ball packaged Mobile Low-Power DDR SDRAM (LPDDR) devices contain
either 1Gb LPDDR or 512Mb LPDDR die.
The 1Gb LPDDR die is a high-speed CMOS, dynamic r a ndom-access memory
containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits.
The 512Mb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits.
Figure 2: Functional Block Diagram
RAS#
CAS#
Row-
address
MUX
CK
CS#
WE#
CK#
Control
logic
Column-
address
counter/
latch
Standard mode
register
Extended mode
register
Command
decode
Address,
BA0, BA1
CKE
Address
register
I/O gating
DM mask logic
Bank 0
memory
array
Bank 0
row-
address
latch
and
decoder
Bank
control
logic
Bank 1
Bank 2
Bank 3
Refresh
counter
32
2
2
32
32
4
Input
registers
4
4
4
4
RCVRS
4
64
64
8
64
CK
out
Data
DQS
Mask
Data
CK
CK
in
DRVRS
MUX
DQS
generator
32
32
32
32
32
64
DQ0–
DQ31
DQS0,
DQS1,
DQS2,
DQS3
4
Read
latch
Write
FIFO
and
drivers
1
COL 0
COL 0
Sense amplifiers
DM0,
DM1,
DM2,
DM3
CK
Column
decoder
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 5©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 3: 152-Ball VFBGA Ball Assignments
Notes: 1. Although not bonded to the die, these pins may be connected on the package substrate.
1
NC
NC
V
SSQ
DQ3
DQ0
V
SSQ
DQ4
DM0
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DNU
NC
1
2
NC
NC
DQS0
DQ5
DQ1
V
DDQ
DQ2
V
SS
NC
NC
NC
V
SS
NC
1
NC
V
SS
NC
1
NC
NC
NC
NC
NC
2
3
V
DDQ
DQ6
NC
NC
3
4
DM1
DQ7
NC
NC
4
5
DQ13
V
DDQ
NC
NC
5
6
DQ15
DQ9
V
SS
NC
1
6
7
V
SSQ
DQ14
NC
1
V
SS
7
8
DQ10
DQS1
NC
NC
8
9
DQ12
DQ11
NC
NC
9
10
DQ16
DQ8
NC
NC
10
11
DQ19
DQ17
V
SS
V
DD
11
12
CK
DQ18
RFU
TQ
12
13
V
SS
CK#
CKE1
V
SS
13
14
DM2
V
SSQ
V
DD
V
DDQ
14
15
V
DDQ
DQS2
CKE0
A13
15
16
DQ21
V
DD
A10
V
SSQ
16
17
DQ20
DQ23
V
SS
V
DD
17
18
DM3
DQ22
WE#
BA0
18
19
DQS3
DQ28
V
SSQ
V
DDQ
19
20
NC
NC
DQ24
DQ25
DQ27
V
SSQ
A0
V
SS
A2
A1
V
DDQ
A7
A8
V
SS
A5
CS1#
CAS#
BA1
V
SSQ
NC
NC
20
21
NC
NC
DQ26
DQ29
DQ31
V
DDQ
DQ30
V
DD
A3
A9
V
SSQ
A6
A11
V
DD
A12
CS0#
A4
RAS#
V
DDQ
DNU
NC
21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
Top View – Ball Down LPDDR Supply Ground
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 6©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Ball Assignments and Descriptions
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact factory for details.
Table 3: Ball Assignments
Symbol Type Description
A[13:0] Input Address inputs: Specify the row or column address. Also used to load the mode registers. The
maximum address is determined by density and configuration. Consult the LPDDR product data
sheet for the maximum address for a given density and configuration . Unused address pins become
RFU.1
BA0, BA1 Input Bank address inputs: Specify one of the 4 banks.
CAS# Input Column select: Specif ies th e comman d to execute.
CK, CK# CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are
sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#.
CKE0, CKE1 Input Clock enable.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products, and is considered RFU for single products.
CS0#, CS1# Input Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products, and is considered RFU for single products.
DM[3:0] Input Data mask: Determines which bytes are written during WRITE operations.
RAS# Input Row select: Specifies the command to execute.
WE# Input Write enable: Specifies the command to execute.
DQ[31:0] Input/
output Data bus: Data inputs/outputs.
DQS[3:0] Input/
output Data strobe: Coordinates read/wr it e transfers of data; one DQS per DQ byte.
TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.
VDD Supply VDD: LPDDR power supply.
VDDQ Supply VDDQ: LPDDR I/O power supply.
VSSQ Supply VSSQ: LPDDR I/O ground.
RFU1–Reserved for future use.
Table 4: Non-Device-Specific Ball Ass ignments
Symbol Type Description
VSS Supply VSS: Shared ground.
DNU – Do not use: Must be grounded or left floating.
NC – No connect: Not internally connected.
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 7©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Electrical Specifications
Electrical Specifications
S t resses greater than those li sted under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated i n the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended period s may affe ct reliability.
Notes: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD.
Table 5: Absolute Maximum Ratings
Note 1 applies to all parameters in this table.
Parameters/Conditions Symbol Min Max Unit
VDD, VDDQ Supply voltage relative to VSS VDD, VDDQ –1.0 2.4 V
Voltage on any pin relative to VSS VIN –0.5 2.4 or (VDDQ + 0.3V),
whichever is less V
Storage temperature range –55 +150 °C
Table 6: Recommended Operating Conditions
Parameters Symbol Min Typ Max Unit
Supply voltage VDD 1.70 1.80 1.95 V
I/O supply voltage VDDQ 1.70 1.80 1.95 V
Operating temperature range Commercial 0 – +70 °C
Industrial -40 – +85 °C
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 8©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Device Diagrams
Device Diagrams
Figure 4: 152-Ball VFBGA Functional Block Diagram (non-Quad Die)
CS#
CK
CK#
CKE
RAS#
CAS#
WE#
Address,
BA0, BA1
V
DD
V
DDQ
DM
DQ
DQS
TQ
V
SS
V
SSQ
LPDDR
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 9©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Device Diagrams
Figure 5: 152-Ball VFBGA Functional Block Diagram, Quad Die
CS0#
CK
CK#
CKE0
RAS#
CAS#
WE#
Address,
BA0, BA1
V
DD
V
DDQ
DM
DQ
DQS
TQ
V
SS
V
SSQ
Two x16 LPDDR
in parallel
CS1#
CK
CK#
CKE1
RAS#
CAS#
WE#
Address,
BA0, BA1
V
DD
V
DDQ
DM
DQ
DQS
TQ
V
SS
V
SSQ
Two x16 LPDDR
in parallel
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 10 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Package Dimensions
Package Dimensions
Figure 6: 152-Ball VFBGA Package, 1.0mm (Package Code: CG)
Notes: 1. All dimensions are in millimeters.
Ball A1 ID
0.6 ±0.1
Seating
plane
0.1 A
A
1.0 MAX
Ball A1 ID
0.65 TYP
13 CTR
14 ±0.1
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
152X Ø0.46
0.35 MIN
13 CTR 14 ±0.1
0.65 TYP
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Package Dimensions
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 11 ©2008 Micron Technology, Inc. All rights reserved.
Figure 7: 152-Ball VFBGA Package, 1.2mm (Package Code: KZ)
Notes: 1. All dimensions are in millimeters.
Ball A1 ID
0.78 ±0.1
Seating
plane
0.1 A
A
1.2 MAX
Ball A1 ID
0.65 TYP
0.65 TYP
13 CTR
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
152X Ø0.46
14 ±0.1
0.35 MIN
13
CTR
14 ±0.1
21 2019181716151413121110987654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
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ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 12 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Revision History
Revision History
Rev. E, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/09
• Table 3, “Ball Assignments,” on page 6: Deleted ball numbers.
• Table 4, “Non-Device-Specific Ball Assignments,” on page 6: Deleted ball numbers.
• Table 5, “Absolute M a ximum Ratings,” on page 7: Added note.
• Table 6, “Recommended Operating Conditions,” on page 7: Updated symbol for I/O
supply voltage.
Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/09
• Added 4Gb option and upd a ted these items to r eflect the addition:
– “MT46HxxxMxxLxKZ” on page 1
– “Options” on page 1
– Table 1, “Configuration Addressing,” on page 1, including note 1
– Table 2, “152-Ball Production Marketing Part Numbers,” on page 3, part number
– Figure 1: “Marketing Part Number Example,” on page 2
– Figure 3: “152-Ball VFBGA Ball Assignments,” on page 5
– Table 4, “Non-Device-Specific Ball Assignments,” on page 6
– Added Figure 5: “152-Ball VFBGA Functional Block Diagram, Quad Die,” on page 9
– Added Figure 7: “152-Ball VFBGA Package, 1.2mm (Package Code: KZ),” on page 11.
• Removed references to reduced-page-size devices.
• Figure 4: “152-Ball VFBGA Functional Block Diagr am (non-Quad Die),” on page 8:
Added parenthetic comment to title.
• Figure 6: “152-Ball VFBGA Package, 1.0mm (Package Code: CG),” on page 10 and
Figure 7: “152-Ball VFBGA Package, 1.2mm (Package Code: KZ),” on page 11: Added
package codes to figure titles.
Rev. C, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/08
• Updated template and standards.
• Added Table 2, “152-Ball Production Marketing Part Numbers,” on page 3.
Rev. B, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/08
• Added reduced page-size options (LA and L G) to Table 1, “Config ura tion A ddr es sing,”
on page 1; Figure 1: “M arketing Part Number Example,” on page 2; “General Descrip-
tion” on page 4.
Rev. A, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/08
•Initial release.