This is information on a product in full production.
June 2015 DocID025716 Rev 6 1/25
25
STGIPN3H60T-H
SLLIMM™-nano (small low-loss intelligent molded module)
IPM, 3 A - 600 V 3-phase IGBT inverter bridge
Datasheet
-
production data
Features
•IPM 3 A, 600 V, 3-phase IGBT inverter bridge
including control ICs for gate driving and
freewheeling diodes
•Optimized for low electromagnetic interference
•V
CE(sat)
negative temperature coefficient
•3.3 V, 5 V, 15 V CMOS/TTL inputs
comparators with hysteresis and pull down/pull
up resistors
•Undervoltage lockout
•Internal bootstrap diode
•Interlocking function
•Smart shutdown function
•Comparator for fault protection against
overtemperature and overcurrent
•Op amp for advanced current sensing
•Optimized pin out for easy board layout
•NTC for temperature control (UL 1434 CA 2
and 4)
Applications
•3-phase inverters for motor drives
•Dish washers, refrigerator compre ssors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
This intelligent power module implements a
compact, high pe rformance AC motor d rive in a
simple, rugged design. It is composed of six
IGBTs with freewheeling diodes and three half-
bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics
with optimized switching speed. The package is
optimized for thermal performance and
compactness in built-in motor applications, or
other low power applications where assembly
space is limited. This IPM includes an operational
amplifier, completely uncommitted, and a
comparator that can be used to design a fast and
efficient protection circuit. SLLIMM™ is a
trademark of STMicroelectronics.
NDIP-26L
Table 1. Device summary
Order code Marking Package Packaging
STGIPN3H60T-H GIPN3H60T-H NDIP-26L Tube
www.st.com
Contents STGIPN3H60T-H
2/25 DocID025716 Rev 6
Contents
1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID025716 Rev 6 3/25
STGIPN3H60T-H Internal schematic diagram and pin con figuration
1 Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
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Internal schematic diagram and pin configuration STGIPN3H60T-H
4/25 DocID025716 Rev 6
Table 2. Pin description
Pin Symbol Description
1 GND Ground
2T/SD
/OD NTC thermistor terminal / shut down logic input (active low) / open
drain (comparator output)
3V
CC
W Low voltage power supply W phase
4 HIN W High side logic input for W phase
5 LIN W Low side logic input for W phase
6 OP+ Op amp non inverting input
7OP
OUT
Op amp outpu t
8 OP- Op amp inverting input
9V
CC
V Low voltage power supply V phase
10 HIN V High side logic input for V phase
11 LIN V Low side logic input for V phase
12 CIN Comparator input
13 V
CC
U Low voltage power supply for U phase
14 HIN U High side logic input for U phase
15 T/SD/OD NTC thermistor terminal / shut down logic input (active low) / open
drain (comparator output)
16 LIN U Low side logic input for U phase
17 V
BOOT
U Bootstrap voltage for U phase
18 P Positive DC input
19 U, OUT
U
U phase output
20 N
U
Negative DC input for U phase
21 V
BOOT
V Bootstrap voltage for V phase
22 V, OUT
V
V phase output
23 N
V
Negative DC input for V phase
24 V
BOOT
W Bootstrap voltage for W phase
25 W, OUT
W
W phase output
26 N
W
Negative DC input for W phase
DocID025716 Rev 6 5/25
STGIPN3H60T-H Internal schematic diagram and pin con figuration
Figure 2. Pin layout (top view)
(*) Dummy pin internally connected to P (positive DC input).
Electrical ratings STGIPN3H60T-H
6/25 DocID025716 Rev 6
2 Electrical ratings
2.1 Absolute maximum ratings
Table 3. Inverter part
Symbol Parameter Value Unit
V
CES
Each IGBT collector emitter voltage (V
IN(1)
= 0)
1. Applied between
HIN
i
, LIN
i
and GND for i = U, V, W
600 V
± I
C (2)
2. Calculated according to the iterative formula:
Each IGBT continuous collector current
at T
C
= 25°C 3A
± I
CP (3)
3. Pulse width limited by max junction temperature
Each IGBT pulsed collector current 18 A
P
TOT
Each IGBT total dissipation at T
C
= 25°C 8 W
Table 4. Control part
Symbol Parameter Min. Max. Unit
V
OUT
Output vo ltage a pplie d between OUT
U
, OUT
V
,
OUT
W
- GND V
boot
- 21 V
boot
+ 0.3 V
V
CC
Low voltage power supply - 0.3 21 V
V
CIN
Comparator input voltage - 0.3 V
CC
+0.3 V
V
op+
OPAMP non-inverting input - 0.3 V
CC
+0.3 V
V
op-
OPAMP inverting input - 0.3 V
CC
+0.3 V
V
boot
Bootstrap voltage - 0.3 620 V
V
IN
Logic input voltage applied between HIN, LIN
and GND - 0.3 15 V
V
T/SD/OD
Open drain voltage - 0.3 15 V
ΔV
OUT/dT
Allowed outp ut sle w rate 50 V/ns
Table 5. Total system
Symbol Parameter Value Unit
V
ISO
Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.) 1000 V
T
j
Power chips operating junction temperature -40 to 150 °C
T
C
Module case operation temperature -40 to 125 °C
I
C
T
C
() T
jmax()
T
C
–
R
thj c–
V
CE sat()max()
T
jmax()
I
C
T
C
(),()×
------ ---- ----------- ---------- ----- ---------- ----------- ---- ----------- ---------- ----- ---------- ------=
DocID025716 Rev 6 7/25
STGIPN3H60T-H Electrical ratings
2.2 Thermal data
Table 6. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction-ambient 50 °C/W
Ele ctrical characteristics STGIPN3H60T-H
8/25 DocID025716 Rev 6
3 Electrical characteristics
T
J
= 25 °C unless otherwise specified.
Figure 3. Switching time test circuit
Table 7. Inverter part
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
CES
Collector-cut off current
(V
IN(1)
= 0 “logic state”) V
CE
= 550 V, V
CC
= 15 V ;
V
BS
= 15 V - 250 µA
V
CE(sat)
Collector-emitter
saturati on vol t age
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 - 5 V,
I
C
= 1 A - 2.15 2.6 V
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 - 5 V,
I
C
= 1 A, T
J
= 125 °C -1.65
V
F
Diode forward voltage V
IN(1)
= 0 “logic state”, I
C
= 1 A - 1.7 V
Inductive load switching time and energy
(2)
t
on
Turn-on time
V
DD
= 300 V,
V
CC
= V
boot
= 15 V,
V
IN(1)
= 0 - 5 V,
I
C
= 1 A
(see Figure 4)
-275
ns
t
c(on)
Crossover time (on) - 90
t
off
Turn-off time - 890
t
c(off)
Crossover time (off) - 125
t
rr
Rever se r ec ove r y time - 5 0
E
on
Turn-on switching losses - 18 µJ
E
off
Turn-off switching losses - 13
1. Applied between
HIN
i
, LIN
i
and GND for i = U, V, W.
2. t
on
and t
off
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are the switching time of IGBT itself
under the internally given gate driving condition.
AM06019v2
DocID025716 Rev 6 9/25
STGIPN 3H6 0T- H Electri cal chara ct er ist ics
Note: Figure 4 “Switching time definition” refers to HIN, LIN inputs (active high).
3.1 Control part
Figure 4. Switching time definition
V
CE
I
C
I
C
V
IN
t
ON
t
C(ON)
VIN(ON) 10% IC 90% IC 10% VCE
(a) turn-on (b) turn-off
t
rr
100% IC 100% IC
V
IN
V
CE
t
OFF
t
C(OFF)
VIN(OFF) 10% VCE 10% IC
AM09223V1
Table 8. Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC_hys
V
CC
UV hysteresis 1.2 1.5 1.8 V
V
CC_thON
V
CC
UV turn ON threshold 11.5 12 12.5 V
V
CC_thOFF
V
CC
UV turn OFF threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent
supply current
V
CC
= 10 V
T/SD/OD = 5 V; LIN = 0;
H
IN
= 0, C
IN
= 0 150 µA
I
qcc
Quiescent current V
cc
= 15 V
T/SD/OD = 5 V; LIN = 0;
H
IN
= 0, C
IN
= 0 1mA
V
ref
Internal com p a rato r (CIN)
reference voltage 0.5 0.54 0.58 V
Ele ctrical characteristics STGIPN3H60T-H
10/25 DocID025716 Rev 6
Table 9. Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
BS_hys
V
BS
UV
hysteresis 1.2 1.5 1.8 V
V
BS_thON
V
BS
UV
turn ON threshold 11.1 11.5 12.1 V
V
BS_thOFF
V
BS
UV
turn OFF threshold 9.8 10 10.6 V
I
QBSU
Undervoltage V
BS
quiescent
current
V
BS
< 9 V
T/SD/OD = 5 V; LIN = 0; and
HIN = 5 V; C
IN
= 0 70 110 µA
I
QBS
V
BS
quiescent curr ent V
BS
= 15 V
T/SD/OD = 5 V; LIN = 0; and
HIN = 5 V; C
IN
= 0 200 300 µA
R
DS(on)
Boot s trap driver on res istance LVG ON 120 Ω
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
il
Low logic level voltage 0.8 1.1 V
V
ih
High logic level voltage 1.9 2.25 V
I
HINh
HIN logic “1” input bias current HIN = 15 V 20 40 100 µA
I
HINl
HIN logic “0” input bias current HIN = 0 V 1 µA
I
LINh
LIN logic “1” input bias current LIN = 15 V 20 40 100 µA
I
LINl
LIN logic “0” input bias current LIN = 0 V 1 µA
I
SDh
SD logic “0” input bias current SD = 15 V 220 295 370 µA
I
SDl
SD logic “1” input bias current SD = 0 V 3 µA
Dt Dead time see Figure 9 180 ns
DocID025716 Rev 6 11/25
STGIPN 3H6 0T- H Electri cal chara ct er ist ics
Table 11. OP AMP characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
V
io
Input offset voltage V
ic
= 0 V, V
o
= 7.5 V 6 mV
I
io
Input offset current V
ic
= 0 V, V
o
= 7.5 V 440nA
I
ib
Input bi as current
(1)
100 200 nA
V
icm
Input common mode voltage
range 0V
V
OL
Low level output voltage R
L
= 10 kΩ to V
CC
75 150 mV
V
OH
High level output voltage R
L
= 10 kΩ to GND 14 14.7 V
I
o
Output short-circuit current
Source,
V
id
= +1; V
o
= 0 V 16 30 mA
Sink,
V
id
= -1; V
o
= V
CC
50 80 mA
SR Slew rate V
i
= 1 - 4 V; C
L
= 100 pF;
unity gain 2.5 3.8 V/μs
GBWP Gain bandwidth product V
o
= 7.5 V 8 12 MHz
A
vd
Large signal voltage gain R
L
= 2 kΩ70 85 dB
SVR Supply voltage rejection ratio vs. V
CC
60 75 dB
CMRR Common mode rejection ratio 55 70 dB
1. The direction of input current is out of the IC.
Table 12. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
ib
Input bias curr ent V
CIN
= 1 V 3 µA
V
od
Open drain low level output
voltage I
od
= 3 mA 0.5 V
R
ON_OD
Open drain low level output
resistance I
od
= 3 mA 166 Ω
R
PD_SD
SD pull down resistor
(1)
125 kΩ
t
d_comp
Compar ator delay T/SD/OD pulled to 5 V
through 100 kΩ resistor 90 130 ns
SR Slew rate C
L
= 180 pF; R
pu
= 5 kΩ60 V/µsec
Ele ctrical characteristics STGIPN3H60T-H
12/25 DocID025716 Rev 6
3.1.1 NTC thermistor
Figure 5. Internal structure of SD and NTC
(a)
t
sd
Shutdown to high / low side
driver propagation delay V
OUT
= 0, V
boot
= V
CC
,
V
IN
= 0 to 3.3 V 50 125 200
ns
t
isd
Comparator triggering to high /
low side driver turn-off
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN 50 200 250
1. equivalent value derived from the resistances of three drivers in parallel
Table 12. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 13. Truth table
Condition Logic input (V
I
) Output
T/SD/OD LIN HIN LVG HVG
Shutdown enable
half-brid ge tri-s tate LX
(1)
X
(1)
LL
Interlocking
half-brid ge tri-s tate HHHLL
0 “logic state”
half-brid ge tri-s tate HLLLL
1 “logic state”
low side direct driving HHLHL
1 “logic state”
high side direct driving HLHLH
1. X = don’t care
a. RPD_SD: equivalent value as result of resistances of three drivers in parallel.
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DocID025716 Rev 6 13/25
STGIPN 3H6 0T- H Electri cal chara ct er ist ics
Figure 6. Equivalent resistance (NTC//R
PD
_
SD
)
Figure 7. Equivalent resistance (NTC//R
PD
_
SD
) zoom
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Ele ctrical characteristics STGIPN3H60T-H
14/25 DocID025716 Rev 6
Figure 8. Voltage of T1/SD/OD pin according to NTC temperature
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STGIPN 3H6 0T- H Electri cal chara ct er ist ics
3.2 Waveform definitions
Figure 9. Dead time and interlocking waveform definitions
INTERLOCKING
INTERLOCKING
INTERLOCKING
INTERLOCKING
G
Smart shutdown function STGIPN3H60T-H
16/25 DocID025716 Rev 6
4 Smart shutdown function
The device integrates a comparator for fault sensing purposes. The comparator has an
internal voltage reference V
REF
connected to the inverting input, while the non-inverting
input on pin (CIN) can be connected to an external shunt resistor for simple overcurrent
protection.
When the comparator triggers, the device is set to the Shutdown state and both its outputs
are switched to the low-level setting, causing the half bridge to enter a tri-state.
In common overcurrent protection architectures, the comparator output is usually connected
to the Shutdown input through an RC network that provides a mono-stable circuit which
implements a protection time following a fault condition.
Our smart shutdown architecture immediately turns off the output gate driver in case of
overcurrent along a preferential path for the fault signal which directly switches off the
outputs. The time delay between the fault and output shutdown no longer depends on the
RC values of the external network connected to the shutdown pin. At the same time, the
DMOS connected to the open-drain output (pin T1/SD/OD) is turned on by the internal logic,
which holds it on until the shutdown voltage is lower than the logic input lower threshold
(Vil).
Also, the smart shutdown function allows increasing the real disable time without increasing
the constant time of the external RC network.
An NTC thermistor for temperature monitoring is internally connected in parallel to the SD
pin. To avoid undesired shutdown, keep the voltage V
T1/SD/OD
higher than the high-level
logic threshold by setting the pull-up resistor R
SD
to 1 kΩ or 2.2 kΩ for the 3.3 V or 5 V MCU
power supplies, respectively.
DocID025716 Rev 6 17/25
STGIPN3H60T-H Smart shutdown function
Figure 10. Smart shutdown timing waveforms
Please refer to Table 12 for internal propagation delay time details.
Application information STGIPN3H60T-H
18/25 DocID025716 Rev 6
5 Application information
Figure 11. Typical application circuit
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DocID025716 Rev 6 19/25
STGIPN3H60T-H Application information
5.1 Recommendations
•HIN and LIN are active-high logic input signals, each having an integrated 500 kΩ (typ.)
pull-down resistor. Wire each input as short as possible and use RC filters (R1, C1) on
each to prevent input signal oscillation. The filters should have a time constant of
approximately 100 ns and must be placed as close as possible to the IPM input pins.
•Use a bypass capacitor Cvcc (aluminum or tantalum) to reduce the transient circuit
demand on the power supply and a decoupling capacitor C2 (from 100 to 220 nF,
ceramic with low ESR), placed as close as possible to each Vcc pin and in parallel to
the bypass capacitor, to reduce high frequency switching noise distributed on the
power supply lines.
•To prevent circuit malfunction, place an RC filter (RSF, CSF) with a time constant (RSF
x CSF) of 1µs as close as possible to the CIN pin.
•The SD is an input/output pin (open drain type if used as output). An integrated NTC
thermistor is connected internally between the SD pin and GND. The pull-up resistor
RSD causes the voltage VSD-GND to decrease as the temperature increases. To
always maintain the voltage above the high-level logic threshold, use a 1 kΩ or 2.2 kΩ
pull-up resistor for a 3.3 V or 5 V MCU power supply, respectively. Size the filter on SD
appropriately to obtain the desired re-start time after a fault event, and locate it as close
as possible to the SD pin .
•Filter high-frequency disturbances by placing the decoupling capacitor C3 (from 100 to
220 nF, ceramic with low ESR) in parallel with each Cboot.
•Prevent overvoltage with Zener diodes DZ1 between the V
CC
pins and GND and in
parallel with each Cboot.
•Locate the decoupling capacitor C4 (from 100 to 220 nF, ceramic with low ESR) in
parallel with the electrolytic capacitor Cvdc to prevent surge destruction. Place
capacitors C4 (especially) and Cvdc as close as possible to the IPM.
•By integrating an application-specific type HVIC inside the module, direct coupling to
the MCU terminals without an opto-coupler is possible.
•Use low inductance shunt resistors for phase leg current sensing.
•The wiring between N pins, the shunt resistor and PWR_GND should be as short as
possible.
•Connect SGN_GND to PWR_GND at only one point (near the shunt resistor terminal),
to avoid any malfunction due to power ground fluctuation.
Table 14. Recommended operating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
PN
Supply voltage Applied between P-Nu,
Nv, Nw 300 500 V
V
CC
Control supply voltage Applied between V
CC
-
GND 13.5 15 18 V
V
BS
High side bias voltage Applied between V
BOOTi
-
OUT
i
for i = U, V, W 13 18 V
t
dead
Blanking time to prevent
Arm-short For each input signal 1.5 µs
Application information STGIPN3H60T-H
20/25 DocID025716 Rev 6
f
PWM
PWM input signal -40°C < T
c
< 100°C
-40°C < T
j
< 125°C 25 kHz
T
C
Case operation temperature 100 °C
Table 14. Recommended operating conditions (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID025716 Rev 6 21/25
STGIPN3H60T-H Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 12. NDIP-26L package outline
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Package information STGIPN3H60T-H
22/25 DocID025716 Rev 6
Table 15.NDIP-26L mechanical data
Dim. mm.
Min. Typ. Max.
A4.40
A1 0.80 1.00 1.20
A2 3.00 3.10 3.20
A3 1.70 1.80 1.90
A4 5.70 5.90 6.10
b 0.53 0.72
b1 0.52 0.60 0.68
b2 0.83 1.02
b3 0.82 0.90 0.98
c 0.46 0.59
c1 0.45 0.50 0.55
D 29.05 29.15 29.25
D1 0.50 0.77 1.00
D2 0.35 0.53 0.70
D3 29.55
E 12.35 12.45 12.55
e 1.70 1.80 1.90
e1 2.40 2.50 2.60
eB1 16.10 16.40 16.70
eB2 21.18 21.48 21.78
L 1.24 1.39 1.54
DocID025716 Rev 6 23/25
STGIPN3H60T-H Package information
6.1
Packing info rmation
Figure 13. NDIP-26L tube dimensions (in mm.)
Note: Base quantity 17 pcs, bulk quantity 476 pcs.
ANTIS TATIC S 03 PVC
AM10474v1
8313150_A
Revision history STGIPN3H60T-H
24/25 DocID025716 Rev 6
7 Revision history
Table 16. Document revision history
Date Revision Changes
19-Dec-2013 1Initial releas e.
23-Apr-2014 2 Updated Figure 1: Internal schematic diagram and Section 3:
Electrical characteristics.
Minor text changes.
05-May-2014 3 Updated features in cover page.
04-Nov-2014 4
Updated:
–Figure 1: Internal schematic diagram
–Table 10: Logic inputs (VCC = 15 V unless otherwise
specified)
–Table 12: Sense comparator characteristics (VCC = 15 V
unless otherwise specified)
–Section 3.1.1: NTC thermistor
–Section 4: Smart shutdown function description
–Figure 10: Smart shutdown timing waveforms
–Figure 11: Typical application circuit
–Section 5.1: Recommendations
– minor text changes
07-Nov-2014 5 Minor text and formatting edits throughout document.
08-Jun-2015 6 Updated Section 6: Package information.
Minor text changes.
DocID025716 Rev 6 25/25
STGIPN3H60T-H
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