CAV25640 EEPROM Serial 64-Kb SPI Automotive Grade 1 Description The CAV25640 is a EEPROM Serial 64-Kb SPI Automotive Grade 1 device internally organized as 8Kx8 bits. This features a 64-byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25640 device. The device features software and hardware write protection, including partial as well as full array protection. www.onsemi.com TSSOP-8 Y SUFFIX CASE 948AL SOIC-8 V SUFFIX CASE 751BD Features * * * * * * * * * * * * * * Automotive Temperature Grade 1 (-40C to +125C) 10 MHz SPI Compatible 2.5 V to 5.5 V Supply Voltage Range SPI Modes (0,0) & (1,1) 64-byte Page Write Buffer Self-timed Write Cycle Hardware and Software Protection CAV Prefix for Automotive and Other Applications Requiring Site and Change Control Block Write Protection - Protect 1/4, 1/2 or Entire EEPROM Array Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention SOIC, TSSOP 8-lead and TDFN 8-pad Packages This Device is Pb-Free, Halogen Free/BFR Free, and RoHS Compliant VCC SI TDFN-8 VP2 SUFFIX CASE 511AK PIN CONFIGURATION CS CAV25640 SO HOLD WP SCK VSS SI SOIC (V), TSSOP (Y), TDFN (VP2) PIN FUNCTION Pin Name Chip Select SO Serial Data Output WP Write Protect VSS Ground Serial Data Input HOLD SCK VCC VSS June, 2018 - Rev. 1 Serial Clock Hold Transmission Input Power Supply ORDERING INFORMATION Figure 1. Functional Symbol (c) Semiconductor Components Industries, LLC, 2011 Function CS SCK HOLD VCC SO SI CS WP 1 See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 1 Publication Order Number: CAV25640/D CAV25640 MARKING DIAGRAMS 25640F AYMXXX G (SOIC-8) S6T AXX YM G S64F AYMXXX G (TDFN-8) (TSSOP-8) S6T = Specific Device Code A = Assembly Location XX = Last Two Digits of XXX = Assembly Lot Number Y = Production Year (Last Digit) M = Production Month (1-9, O, N, D) G = Pb-Free Package 25640F = Specific Device Code A = Assembly Location Y = Production Year (Last Digit) M = Production Month (1-9, O, N, D) XXX = Last Three Digits of XXX = Assembly Lot Number G = Pb-Free Package S64F = Specific Device Code A = Assembly Location Y = Production Year (Last Digit) M = Production Month (1-9, O, N, D) XXX = Last Three Digits of XXX = Assembly Lot Number G = Pb-Free Package Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Operating Temperature -45 to +130 C Storage Temperature -65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) -0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Data Retention Min Units 1,000,000 Program / Erase Cycles 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25C. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICCR Supply Current (Read Mode) Read, VCC = 5.5 V, 5 MHz, SO open 2 mA ICCW Supply Current (Write Mode) Write, VCC = 5.5 V, 5 MHz, SO open 3 mA ISB1 Standby Current VIN = GND or VCC, CS = VCC, WP = VCC, VCC = 5.5 V 2 mA ISB2 Standby Current VIN = GND or VCC, CS = VCC, WP = GND, VCC = 5.5 V 5 mA Input Leakage Current VIN = GND or VCC -2 2 mA ILO Output Leakage Current CS = VCC, VOUT = GND or VCC -1 2 mA VIL Input Low Voltage -0.5 0.3 VCC V 0.7 VCC VCC + 0.5 V 0.4 V IL VIH Input High Voltage VOL1 Output Low Voltage IOL = 3.0 mA VOH1 Output High Voltage IOH = -1.6 mA www.onsemi.com 2 VCC - 0.8 V V CAV25640 Table 4. PIN CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = +5.0 V) (Note 2) Test Symbol COUT Conditions Output Capacitance (SO) CIN Input Capacitance (CS, SCK, SI, WP, HOLD) Min Typ Max Units VOUT = 0 V 8 pF VIN = 0 V 8 pF Table 5. A.C. CHARACTERISTICS (TA = -40C to +125C) (Note 4) VCC = 2.5 V - 5.5 V Min Max Units fSCK Clock Frequency DC 10 MHz tSU Data Setup Time 10 ns tH Data Hold Time 10 ns tWH SCK High Time 40 ns tWL SCK Low Time 40 ns tLZ Parameter Symbol HOLD to Output Low Z 25 ns tRI (Note 5) Input Rise Time 2 ms tFI (Note 5) Input Fall Time 2 ms tHD HOLD Setup Time 0 ns tCD HOLD Hold Time 10 ns tV Output Valid from Clock Low tHO Output Hold Time tDIS Output Disable Time tHZ 35 0 HOLD to Output High Z ns ns 20 ns 25 ns tCS CS High Time 40 ns tCSS CS Setup Time 30 ns tCSH CS Hold Time 30 ns tCNS CS Inactive Setup Time 20 ns tCNH CS Inactive Hold Time 20 ns tWPS WP Setup Time 10 ns tWPH WP Hold Time 10 ns tWC (Note 6) Write Cycle Time 5 ms 4. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 5. This parameter is tested initially and after a design or process change that affects the parameter. 6. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. Table 6. POWER-UP TIMING (Notes 5, 7) Symbol Max Units tPUR Power-up to Read Operation Parameter 1 ms tPUW Power-up to Write Operation 1 ms 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. www.onsemi.com 3 CAV25640 Pin Description Functional Description SI: The serial data input pin accepts op-codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAV25640. CS: The chip select input pin is used to enable/disable the CAV25640. When CS is high, the SO output is tri-stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAV25640 must be preceded by a high to low transition and concluded with a low to high transition of the CS input. WP: The write protect input pin will allow all write operations to the device when held high. When WP pin is tied low and the WPEN bit in the Status Register (refer to Status Register description, later in this Data Sheet) is set to "1", writing to the Status Register is disabled. HOLD: The HOLD input pin is used to pause transmission between host and CAV25640, without having to retransmit the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, the HOLD input should be tied to VCC, either directly or through a resistor. The CAV25640 device supports the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8-bit instruction register. The instruction set and associated op-codes are listed in Table 7. Reading data stored in the CAV25640 is accomplished by simply providing the READ command and an address. Writing to the CAV25640, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later. After a high to low transition on the CS input pin, the CAV25640 will accept any one of the six instruction op-codes listed in Table 7 and will ignore all other possible 8-bit combinations. The communication protocol follows the timing from Figure 2. Table 7. INSTRUCTION SET Instruction Op-code WREN 0000 0110 Enable Write Operations Operation WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory tCS CS tCSS tCNH tWH tWL tCNS tCSH SCK tSU tH tRI tFI VALID IN SI tV tV tDIS tHO SO HI-Z VALID OUT Figure 2. Synchronous Data Timing www.onsemi.com 4 HI-Z CAV25640 Status Register allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read-only. The WPEN (Write Protect Enable) bit acts as an enable for the WP pin. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. This condition prevents writing to the status register and to the block protected sections of memory. While hardware write protection is active, only the non-block protected memory can be written. Hardware write protection is disabled when the WP pin is high or the WPEN bit is 0. The WPEN bit, WP pin and WEL bit combine to either permit or inhibit Write operations, as detailed in Table 10. The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non-volatile. The user is Table 8. STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN 0 0 0 BP1 BP0 WEL RDY Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 0 1 1800-1FFF Quarter Array Protection 1 0 1000-1FFF Half Array Protection 1 1 0000-1FFF Full Array Protection Table 10. WRITE PROTECT CONDITIONS WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable www.onsemi.com 5 CAV25640 WRITE OPERATIONS Write Enable and Write Disable The CAV25640 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of the memory location(s) to be written must be outside the protected area, as defined by BP0 and BP1 bits from the status register. The internal Write Enable Latch and the corresponding Status Register WEL bit are set by sending the WREN instruction to the CAV25640. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3. The WREN instruction must be sent prior to any WRITE or WRSR instruction. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write operations by resetting the WEL bit, will protect the device against inadvertent writes. CS SCK SI SO 0 0 0 0 0 1 1 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) Figure 3. WREN Timing CS SCK SI SO 0 0 0 0 0 1 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) Figure 4. WRDI Timing www.onsemi.com 6 0 CAV25640 Byte Write Page Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16-bit address and data as shown in Figure 5. Only 13 significant address bits are used by the CAV25640. The rest are don't care bits, as shown in Table 11. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low). After sending the first data byte to the CAV25640, the host may continue sending data, up to a total of 64 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will "roll over" to the first byte in the page, thus possibly overwriting previously loaded data. Following completion of the write cycle, the CAV25640 is automatically returned to the write disable state. Table 11. BYTE ADDRESS Device Address Significant Bits Address Don't Care Bits # Address Clock Pulses A12 - A0 A15 - A13 16 CAV25640 CS 0 1 2 3 4 5 6 7 21 8 22 23 24 25 26 27 28 29 30 31 SCK OPCODE SI 0 0 0 0 0 0 DATA IN BYTE ADDRESS* 1 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 AN HIGH IMPEDANCE SO * Please check the Byte Address Table (Table 11) Dashed Line = mode (1, 1) Figure 5. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 21 SCK 0 0 0 0 0 0 23 24-31 32-39 24+(N-1)x8-1 .. 24+(N-1)x8 24+Nx8-1 BYTE ADDRESS* OPCODE SI 22 1 0 AN DATA IN A0 Data Data Data Byte 1 Byte 2 Byte 3 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Data Byte N 7..1 0 * Please check the Byte Address Table (Table 11) Figure 6. Page WRITE Timing www.onsemi.com 7 CAV25640 Write Status Register Write Protection The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3 and 7 can be written using the WRSR command. The Write Protect (WP) pin can be used to protect the Block Protect bits BP0 and BP1 against being inadvertently altered. When WP is low and the WPEN bit is set to "1", write operations to the Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit is set to "0". The WP input timing is shown in Figure 8. CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 0 DATA IN 0 0 MSB HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Figure 7. WRSR Timing tWPS tWPH CS SCK WP WP Dashed Line = mode (1, 1) Figure 8. WP Timing www.onsemi.com 8 3 CAV25640 READ OPERATIONS Read from Memory Array address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high. To read from memory, the host sends a READ instruction followed by a 16-bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAV25640 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter "rolls over" to the lowest memory Read Status Register To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAV25640 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the contents of the status register. CS 0 1 2 3 4 5 6 7 8 20 21 10 9 22 23 24 25 26 27 28 29 30 SCK OPCODE SI 0 0 0 0 0 0 BYTE ADDRESS* 1 1 A0 AN DATA OUT HIGH IMPEDANCE SO 7 Dashed Line = mode (1, 1) * Please check the Byte Address Table (Table 11) 6 5 4 3 2 1 0 MSB Figure 9. READ Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 6 5 11 12 13 14 2 1 SCK OPCODE SI SO 0 0 0 0 0 DATA OUT HIGH IMPEDANCE 7 MSB Dashed Line = mode (1, 1) Figure 10. RDSR Timing www.onsemi.com 9 4 3 0 CAV25640 Hold Operation below the POR trigger level. This bi-directional POR behavior protects the device against `brown-out' failure following a temporary loss of power. The CAV25640 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior to any writes to the device. After power up, the CS pin must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the device goes into a write disable mode. The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op-code will be ignored and the serial output pin (SO) will remain in the high impedance state. The HOLD input can be used to pause communication between host and CAV25640. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During the pause, the data output pin (SO) is tri-stated (high impedance) and SI transitions are ignored. To resume communication, HOLD must be taken high while SCK is low. Design Considerations The CAV25640 device incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ Dashed Line = mode (1, 1) Figure 11. HOLD Timing ORDERING INFORMATION (Notes 8 - 10) Specific Device Marking Package Type Shipping CAV25640VE-GT3 25640F SOIC-8 (Pb-Free) 3,000 / Tape & Reel CAV25640YE-GT3 S64F TSSOP-8 (Pb-Free) 3,000 / Tape & Reel CAV25640VP2E-GT3 S6T TDFN-8 (Pb-Free) 3,000 / Tape & Reel Device Order Number For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 8. All packages are RoHS-compliant (Lead-free, Halogen-free). 9. The standard lead finish is NiPdAu. 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TDFN8, 2x3, 0.5P CASE 511AK ISSUE B 1 DATE 18 MAR 2015 SCALE 2:1 PIN ONE REFERENCE 0.10 C B A D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 CC CC CC DETAIL A ALTERNATE CONSTRUCTIONS E EXPOSED Cu 0.10 C TOP VIEW CC CC EE DIM A A1 A3 b D D2 E E2 e L L1 MOLD CMPD DETAIL B A DETAIL B 0.10 C 0.08 C NOTE 4 ALTERNATE CONSTRUCTION A3 A1 SIDE VIEW GENERIC MARKING DIAGRAM* SEATING PLANE C MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.30 1.50 3.00 BSC 1.20 1.40 0.50 BSC 0.20 0.40 --- 0.15 1 DETAIL A 1 D2 XXXXX AWLYWG L 4 XXXXX A WL Y W G E2 8 5 8X e BOTTOM VIEW b 0.10 M C A B 0.05 M C = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 1.56 8X 0.68 1.45 3.40 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: 98AON34336E ON SEMICONDUCTOR STANDARD REFERENCE: (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 TDFN8, 2X3, 0.5P http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON34336E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #TDFN8-008-01 TO ON SEMICONDUCTOR. REQ. BY B. BERGMAN. 19 DEC 2008 A CHANGED DESCRIPTION FROM WDFN TO TDFN. 18 MAR 2009 B REDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD. REQ. BY B. BECKER. 18 MAR 2015 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2015 March, 2015 - Rev. B Case Outline Number: 511AK MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD-01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 0 8 TOP VIEW D h A1 A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: STATUS: 98AON34272E ON SEMICONDUCTOR STANDARD REFERENCE: (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 SOIC 8, 150 MILS http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON34272E PAGE 2 OF 2 ISSUE O REVISION RELEASED FOR PRODUCTION FROM POD #SOIC8-002-01 TO ON SEMICONDUCTOR. REQ. BY B. BERGMAN. DATE 19 DEC 2008 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2008 December, 2008 - Rev. 01O Case Outline Number: 751BD MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O DATE 19 DEC 2008 b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 0.90 e 0.65 BSC L 1.00 REF L1 0.50 0 0.60 1.05 0.75 8 e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. DOCUMENT NUMBER: STATUS: 98AON34428E ON SEMICONDUCTOR STANDARD REFERENCE: (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 TSSOP8, 4.4X3 http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON34428E PAGE 2 OF 2 ISSUE O REVISION RELEASED FOR PRODUCTION FROM POD #TSSOP8-004-01 TO ON SEMICONDUCTOR. REQ. BY B. BERGMAN. DATE 19 DEC 2008 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2008 December, 2008 - Rev. 01O Case Outline Number: 948AL ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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