BD0
 
  
FEATURES DESCRIPTION
APPLICATIONS
ADS1000
Clock
Oscillator
I C
Interface
2
A/D
Converter
PGA
A=1,2,4,or8
VDD
VIN+
VIN-
GND
SDA
SCL
ADS1000
SBAS357 – SEPTEMBER 2006
LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTERwith I
2
C™ INTERFACE
•Complete 12-Bit Data Acquisition System in
The ADS1000 is an I
2
C-compatible serial interfacea Tiny SOT-23 Package
Analog-to-Digital (A/D) converter with differentialinputs and 12 bits of resolution in a tiny SOT23-6•Low Current Consumption: Only 90 µA
package. Conversions are performed ratiometrically,•Integral Nonlinearity: 1LSB Max
using the power supply as the reference voltage. The•Single-Cycle Conversion
ADS1000 operates from a single power supplyranging from 2.7V to 5.5V.•Programmable Gain AmplifierGain = 1, 2, 4 or 8
The ADS1000 performs conversions at a rate of 128•128SPS Data Rate
samples per second (SPS). The onboardprogrammable gain amplifier (PGA), which offers•I
2
C Interface with Two Available Addresses
gains of up to 8, allows smaller signals to be•Power Supply: 2.7V to 5.5V
measured with high resolution. In single-conversion•Pin- and Software-Compatible with 16-Bit
mode, the ADS1000 automatically powers down afterADS1100
a conversion, greatly reducing current consumptionduring idle periods.
The ADS1000 is designed for applications where•Voltage Monitors
space and power consumption are majorconsiderations. Typical applications include portable•Battery Management
instrumentation, consumer goods, and voltage•Industrial Process Control
monitoring.•Consumer Goods•Temperature Measurement
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.I2C is a trademark of Royal Philips Electronics B.V., The Netherlands.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
PACKAGE/ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:Markingtextdirectionindicatespin1.MarkingtextdependsonI Caddress;seePackageOptionAddendum.
2
BD0
VIN-
6
VDD
5
SDA
4
SCL
3
GND
2
VIN+
1
BD1
VIN-
6
VDD
5
SDA
4
SCL
3
GND
2
VIN+
1
I Caddress:1001000
2I Caddress:1001001
2
ADS1000
SBAS357 – SEPTEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
For the most current package and ordering information, see the Package Option Addendum located at the endof this datasheet or see the TI website at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
ADS1000 UNIT
V
DD
to GND –0.3 to +6 VInput Current (Momentary) 100 mAInput Current (Continuous) 10 mAVoltage to GND, V
IN+
, V
IN–
–0.3 to V
DD
to +0.3 VVoltage to GND, SDA, SCL –0.5 to +6 VMaximum Junction Temperature, T
J
+150 °COperating Temperature –40 to +125 °CStorage Temperature –60 to +150 °CLead Temperature (soldering, 10s) +300 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
PIN CONFIGURATION
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ELECTRICAL CHARACTERISTICS
ADS1000
SBAS357 – SEPTEMBER 2006
All specifications at –40 °C to +85 °C, V
DD
= 5V, GND = 0V, and all PGAs, unless otherwise noted.
ADS1000
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-Scale Input Voltage (V
IN+
) – (V
IN–
)±V
DD
/PGA
(1)
VAnalog Input Voltage V
IN+
, V
IN–
to GND GND – 0.2 V
DD
+ 0.2 VDifferential Input Impedance 2.4/PGA M ΩCommon-Mode Input Impedance 8 M Ω
SYSTEM PERFORMANCE
Resolution No Missing Codes 12 BitsData Rate 104 128 184 SPSIntegral Nonlinearity (INL) ±0.1 1 LSBOffset Error 1 ±2 LSBGain Error 0.01 0.1 %
DIGITAL INPUT/OUTPUT
Logic Level
V
IH
0.7 GND 6 VV
IL
GND – 0.5 0.3 V
DD
VV
OL
I
OL
= 3mA GND 0.4 VInput Leakage
I
IH
V
IH
= 5.5V 10 µAI
IL
V
IL
= GND – 10 µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage V
DD
2.7 5.5 VSupply Current Power-Down 0.05 2 µAActive 90 150 µAPower Dissipation µAV
DD
= 5.0V 450 750 µWV
DD
= 3.0V 210 µW
(1) Each input, V
IN+
and V
IN–
, must meet the absolute input voltage specifications.
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TYPICAL CHARACTERISTICS
250
225
200
175
150
125
100
75
50 10 100 1k 10k
I2C Bus Frequency (kHz)
IVDD (µA)
25_C
−40_C
125_C
120
100
80
60
40
IVDD (µA)
−60 −40 −20 0 20 40 60 80 100 120 140
Temperature (_C)
VDD = 5V
VDD = 2.7V
PGA = 8 PGA = 4 PGA = 2 PGA = 1
2.0
1.0
0.0
1.0
2.0
-
-
-40 -20 0 20 40 60 80 100 120 140-60
Temperature(°C)
OffsetError(mV)
VDD = 2.7V
VDD = 5V
160
144
128
112
96
Data Rate (SPS)
−60 −40 −20 0 20 40 60 80 100 120 140
Temperature (_C)
ADS1000
SBAS357 – SEPTEMBER 2006
At T
A
= 25 °C and V
DD
= 5V, unless otherwise indicated.
SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs I
2
C BUS FREQUENCY
Figure 1. Figure 2.
OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE
Figure 3. Figure 4.
DATA RATE vs TEMPERATURE
Figure 5.
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ANALOG-TO-DIGITAL CONVERTER
RESET AND POWER-UP
OUTPUT CODE CALCULATION
I
2
C INTERFACE
Output Code +2048(PGA)ǒVIN)*VIN−
VDD Ǔ
CLOCK GENERATOR
USING THE ADS1000
OPERATING MODES
ADS1000
SBAS357 – SEPTEMBER 2006
THEORY OF OPERATION
places the result in the output register, andThe ADS1000 is a fully differential, 12-bit A/D
immediately begins another conversion. When theconverter. The ADS1000 allows users to obtain
ADS1000 is in continuous conversion mode, theprecise measurements with a minimum of effort, and
ST/BSY bit in the configuration register always readsthe device is extremely easy to design with and
'1'.configure.
In single conversion mode, the ADS1000 waits untilThe ADS1000 consists of an A/D converter core with
the ST/BSY bit in the conversion register is set to '1'.adjustable gain, a clock generator, and an I
2
C
When this happens, the ADS1000 powers up andinterface. Each of these blocks are described in
performs a single conversion. After the conversiondetail in the sections that follow.
completes, the ADS1000 places the result in theoutput register, resets the ST/BSY bit to '0' andpowers down. Writing a '1' to ST/BSY while aconversion is in progress has no effect.The ADS1000 uses a switched-capacitor input stage.To external circuitry, it looks roughly like a
When switching from continuous conversion mode toresistance. The resistance value depends on the
single conversion mode, the ADS1000 will completecapacitor values and the rate at which they are
the current conversion, reset the ST/BSY bit to '0'switched. The switching clock is generated by the
and power-down the device.onboard clock generator, so its frequency, nominally275kHz, is dependent on supply voltage andtemperature. The capacitor values depend on the
When the ADS1000 powers up, it automaticallyPGA setting.
performs a reset. As part of the reset, the ADS1000The common-mode and differential input impedances
sets all of the bits in the configuration register to theirare different. For a gain setting of PGA, the
respective default settings.differential input impedance is typically 2.4M Ω/PGA.
The ADS1000 responds to the I
2
C General CallThe common-mode impedance is typically 8M Ω.
Reset command. When the ADS1000 receives aGeneral Call Reset, it performs an internal reset,exactly as though it had just been powered on.The ADS1000 outputs codes in binary two’scomplement format. The output code is confined tothe range of numbers: –2048 to 2047, and is given
The ADS1000 communicates through an I
2
Cby:
(Inter-Integrated Circuit) interface. The I
2
C interfaceis a two-wire, open-drain interface supportingmultiple devices and masters on a single bus.Devices on the I
2
C bus only drive the bus lines low,by connecting them to ground; they never drive thebus lines high. Instead, the bus wires are pulled highby pull-up resistors, so the bus wires are high whenThe ADS1000 features an onboard clock generator.
no device is driving them low. This way, two devicesThe Typical Characteristics show variations in data
cannot conflict; if two devices drive the busrate over supply voltage and temperature. It is not
simultaneously, there is no driver contention.possible to operate the ADS1000 with an externalclock.
Communication on the I
2
C bus always takes placebetween two devices, one acting as the master andthe other acting as the slave. Both masters andslaves can read and write, but slaves can only do sounder the direction of the master. Some I
2
C devicescan act as masters or slaves, but the ADS1000 canThe ADS1000 operates in one of two modes:
only act as a slave device.continuous conversion and single conversion.
In continuous conversion mode, the ADS1000continuously performs conversions. Once aconversion has been completed, the ADS1000
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ADS1000
SBAS357 – SEPTEMBER 2006
An I
2
C bus consists of two lines, SDA and SCL. SDA 10-bit addresses; see the I
2
C specification forcarries data; SCL provides the clock. All data is details.) The master sends an address in thetransmitted across the I
2
C bus in groups of eight bits. address byte, together with a bit that indicatesTo send a bit on the I
2
C bus, the SDA line is driven whether it wishes to read from or write to the slaveto the bit level while SCL is low (a Low on SDA device.indicates the bit is '0'; a High indicates the bit is '1').
Every byte transmitted on the I
2
C bus, whether it beOnce the SDA line has settled, the SCL line is
address or data, is acknowledged with anbrought high, then low. This pulse on SCL clocks the
acknowledge bit. When a master has finishedSDA bit into the receiver shift register.
sending a byte, eight data bits, to a slave, it stopsThe I
2
C bus is bidirectional: the SDA line is used driving SDA and waits for the slave to acknowledgeboth for transmitting and receiving data. When a the byte. The slave acknowledges the byte by pullingmaster reads from a slave, the slave drives the data SDA low. The master then sends a clock pulse toline; when a master sends to a slave, the master clock the acknowledge bit. Similarly, when a masterdrives the data line. The master always drives the has finished reading a byte, it pulls SDA low toclock line. The ADS1000 never drives SCL, because acknowledge to the slave that it has finished readingit cannot act as a master. On the ADS1000, SCL is the byte. It then sends a clock pulse to clock the bit.an input only. (Remember that the master always drives the clockline.)Most of the time the bus is idle, no communicationtakes place, and both lines are high. When A not-acknowledge is performed by simply leavingcommunication takes place, the bus is active. Only SDA high during an acknowledge cycle. If a device ismaster devices can start a communication. They do not present on the bus, and the master attempts tothis by causing a start condition on the bus. address it, it will receive a not-acknowledge becauseNormally, the data line is only allowed to change no device is present at that address to pull the linestate while the clock line is low. If the data line low.changes state while the clock line is high, it is either
When a master has finished communicating with aastart condition or its counterpart, a stop condition.
slave, it may issue a stop condition. When a stopA start condition is when the clock line is high and
condition is issued, the bus becomes idle again. Athe data line goes from high to low. A stop condition
master may also issue another start condition. Whenis when the clock line is high and the data line goes
a start condition is issued while the bus is active, it isfrom low to high.
called a repeated start condition.After the master issues a start condition, it sends a
A timing diagram for an ADS1000 I
2
C transaction isbyte that indicates with which slave device it wants to
shown in Figure 6 .Table 1 gives the parameters forcommunicate. This byte is called the address byte.
this diagram.Each device on an I
2
C bus has a unique 7-bitaddress to which it responds. (Slaves can also have
6
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t(BUF)
t(HDSTA)
t(LOW) tRtF
t(HDDAT)
t(HIGH) t(SUSTA)
t(SUDAT)
t(HDSTA)
t(SUSTO)
SCL
SDA
P S S P
ADS1000
SBAS357 – SEPTEMBER 2006
Figure 6. I
2
C Timing Diagram
Table 1. Timing Diagram DefinitionsFAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCLK Operating Frequency f
(SCLK)
0.4 3.4 MHz
Bus Free Time Between STOP and START t
(BUF)
600 160 nsCondition
Hold Time After Repeated START Condition. t
(HDSTA)
600 160 nsAfter this period, the first clock is generated.
Repeated START Condition Setup Time t
(SUSTA)
600 160 ns
STOP Condition Setup Time t
(SUSTO)
600 160 ns
Data Hold Time t
(HDDAT)
0 0 ns
Data Setup Time t
(SUDAT)
100 10 ns
SCLK Clock Low Period t
(LOW)
1300 160 ns
SCLK Clock High Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time t
R
300 160 ns
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I
2
C GENERAL CALL
REGISTERS
OUTPUT REGISTER
I
2
C DATA RATES
ADS1000
SBAS357 – SEPTEMBER 2006
ADS1000 in Standard or Fast modes, butHigh-speed mode must be activated. To activateADS1000 I
2
C ADDRESSES
High-speed mode, send a special address byte ofThe ADS1000 I
2
C address is either 1001000 or
00001XXX following the start condition, where the1001001, set at the factory. The address is identified
XXX bits are unique to the Hs-capable master. Thiswith an A0 or an A1 within the orderable name.
byte is called the Hs master code. (Note that this isdifferent from normal address bytes; the low bit doesThe two different I
2
C variants are also marked
not indicate read/write status.) The ADS1000 will notdifferently. Devices with an I
2
C address of 1001000
acknowledge this byte; the I
2
C specification prohibitshave packages marked BD0, while devices with an
acknowledgment of the Hs master code. OnI
2
C address of 1001001 are marked with BD1. See
receiving a master code, the ADS1000 will switch onthe Package/Ordering Information Table for a
its High-speed mode filters, and will communicate atcomplete listing of the ADS1000 I
2
C addresses and
up to 3.4MHz. The ADS1000 switches out of Hstape and reel size.
mode with the next stop condition.
For more information on High-speed mode, consultthe I
2
C specification.The ADS1000 responds to General Call Reset,which is an address byte of 00h followed by a databyte of 06h. The ADS1000 acknowledges both bytes.
The ADS1000 has two registers that are accessibleOn receiving a General Call Reset, the ADS1000
via its I
2
C port. The output register contains theperforms a full internal reset, just as though it had
result of the last conversion; the configurationbeen powered off and then on. If a conversion is in
register allows users to change the ADS1000process, it is interrupted; the output register is set to
operating mode and query the status of the device.zero, and the configuration register returns to itsdefault setting.
The ADS1000 always acknowledges the General
The 16-bit output register contains the result of theCall address byte of 00h, but it does not
last conversion in binary two’s complement format.acknowledge any General Call data bytes other than
Since the port yields 12 bits of data, the ADS100004h or 06h.
outputs right-justified and sign-extended codes. Thisoutput format makes it possible to perform averagingusing a 16-bit accumulator.The I
2
C bus operates in one of three speed modes:
Following reset or power-up, the output register isStandard, which allows a clock frequency of up to
cleared to '0'; it remains zero until the first conversion100kHz; Fast, which allows a clock frequency of up
is completed. Therefore, if a user reads theto 400kHz; and High-speed mode (also called Hs
ADS1000 just after reset or power-up, the outputmode), which allows a clock frequency of up to
register will read '0'.3.4MHz. The ADS1000 is fully compatible with allthree modes.
The output register format is shown in Table 2 .No special action needs to be taken to use the
Table 2. OUTPUT REGISTERBIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME D15
(1)
D14
(1)
D13
(1)
D12
(1)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(1) D15–D12 are sign extensions of 12-bit data.
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CONFIGURATION REGISTER
READING FROM THE ADS1000
WRITING TO THE ADS1000
ADS1000
SBAS357 – SEPTEMBER 2006
Bits 1 - 0: PGAA user controls the ADS1000 operating mode and
Bits 1 and 0 control the ADS1000 gain setting; seePGA settings via the 8-bit configuration register. The
Table 4 .configuration register format is shown in Table 3 .The default setting is 80H.
Table 4. PGA Bits
PGA1 PGA0 GAINTable 3. CONFIGURATION REGISTER
0
(1)
0
(1)
1
(1)7 6543210
012ST/BSY 0 0 SC 0 0 PGA1 PGA0
104118Bit 7: ST/BSY
(1) Default setting.The meaning of the ST/BSY bit depends on whetherit is being written to or read from.
In single conversion mode, writing a '1' to theST/BSY bit causes a conversion to start, and writing
A user can read the output register and the contentsa '0' has no effect. In continuous conversion mode,
of the configuration register from the ADS1000. Tothe ADS1000 ignores the value written to ST/BSY.
do this, address the ADS1000 for reading, and readWhen read in single conversion mode, ST/BSY
three bytes from the device. The first two bytes areindicates whether the A/D converter is busy taking a
the output register contents; the third byte is theconversion. If ST/BSY is read as '1', the A/D
configuration register contents.converter is busy, and a conversion is taking place; if
A user does not always have to read three bytes'0', no conversion is taking place, and the result of
from the ADS1000. If only the contents of the outputthe last conversion is available in the output register.
register are needed, read only two bytes.In continuous mode, ST/BSY is always read as '1'.
Reading more than three bytes from the ADS1000Bits 6 - 5: Reserved
has no effect. All of the bytes beginning with thefourth byte will be FFh. See Figure 7 for a timingBits 6 and 5 must be set to zero.
diagram of an ADS1000 read operation.Bit 4: SC
SC controls whether the ADS1000 is in continuousconversion or single conversion mode. When SC is
A user can write new contents into the configuration'1', the ADS1000 is in single conversion mode; when
register (the contents of the output register cannotSC is '0', the ADS1000 is in continuous conversion
change). To do this, address the ADS1000 formode. The default setting is '0'.
writing, and write one byte to it. This byte is writteninto the configuration register.Bits 3 - 2: Reserved
Writing more than one byte to the ADS1000 has noBits 3 and 2 must be set to zero.
effect. The ADS1000 ignores any bytes sent to itafter the first one, and will only acknowledge the firstbyte. See Figure 8 for a timing diagram of anADS1000 write operation.
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Frame1:I CSlaveAddressByte
2Frame2:OutputRegisterUpperByte
StartBy
Master
ACKBy
ADS1000
ACKBy
Master
From
ADS1000
From
ADS1000
1919
···
···
···
···
SDA
SCL
SDA
(Continued)
SCL
(Continued)
10 0 1A2 A1 A0 R/W D15 D14 D13 D12 D11 D10 D9 D8
Frame3:OutputRegisterLowerByte Frame4:ConfigurationRegister
(Optional)
ACKBy
Master
StopBy
Master
ACKBy
Master
From
ADS1000
19 1
D7 D6 D5 D4 D3 D2 D1 D0
ST/
BSY
0 0 SC 0 0
PGA1 PGA0
9
Frame1:I CSlaveAddressByte
2Frame2:ConfigurationRegister
1
StartBy
Master
ACKBy
ADS1000
ACKBy
ADS1000
1 9 1 9
SDA
SCL
0 0 1 A2 A1 A0 R/W
ST/
BSY
0 0 SC
PGA1 PGA0
StopBy
Master
0 0
ADS1000
SBAS357 – SEPTEMBER 2006
Figure 7. Timing Diagram for Reading from the ADS1000
Figure 8. Timing Diagram for Writing to the ADS1000
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APPLICATION INFORMATION
BASIC CONNECTIONS
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000
PositiveInput
(0Vto5V)
NegativeInput
(0Vto5V)
VDD
VDD
4.7 F(typ.)m
Microcontrolleror
Microprocessor
withI CPort
2
SCL
SDA
I CPull-UpResistors
1k to10k (typ.)W W
2
ADS1000
SBAS357 – SEPTEMBER 2006
The ADS1000 interfaces directly to standard mode,fast mode, and high-speed mode I
2
C controllers. Anymicrocontroller I
2
C peripheral, including master-onlyFor many applications, connecting the ADS1000 is
and non-multiple-master I
2
C peripherals, will workextremely simple. A basic connection diagram for the
with the ADS1000. The ADS1000 does not performADS1000 is shown in Figure 9 .
clock-stretching (that is, it never pulls the clock lineThe fully differential voltage input of the ADS1000 is
low), so it is not necessary to provide for this unlessideal for connection to differential sources with
other devices are on the same I
2
C bus.moderately low source impedance, such as bridge
Pull-up resistors are necessary on both the SDA andsensors and thermistors. Although the ADS1000 can
SCL lines because I
2
C bus drivers are open-drain.read bipolar differential signals, it cannot accept
The size of these resistors depends on the busnegative voltages on either input. It may be helpful to
operating speed and capacitance of the bus lines.think of the ADS1000 positive voltage input as
Higher-value resistors consume less power, butnoninverting, and of the negative input as inverting.
increase the transition times on the bus, limiting theWhen the ADS1000 is converting, it draws current in
bus speed. Lower-value resistors allow higher speedshort spikes. The 0.1 µF bypass capacitor supplies
at the expense of higher power consumption. Longthe momentary bursts of extra current needed from
bus lines have higher capacitance and requirethe supply.
smaller pullup resistors to compensate. The resistorsshould not be too small; if they are, the bus driversmay not be able to pull the bus lines low.
Figure 9. Typical Connections of the ADS1000
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CONNECTING MULTIPLE DEVICES
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000 VDD
Microcontrolleror
Microprocessor
withI CPort
2
SCL
SDA
NOTE:ADS1000power
andinputconnections
omittedforclarity.
1
2
3
6
5
4
SDA
SCL
I CPull-UpResistors
1k to10k (typ.)W W
2
VDD
Microcontrolleror
Microprocessor
withI CPort
2
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000A0
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000A1
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1100A2
NOTE:ADS1000power
andinputconnections
omittedforclarity.
USING GPIO PORTS FOR I
2
C
SINGLE-ENDED INPUTS
ADS1000
SBAS357 – SEPTEMBER 2006
Connecting two ADS1000s to a single bus is almosttrivial. An example showing two ADS1000s and oneADS1100 connected on a single bus is shown inFigure 10 . Multiple devices can be connected to asingle bus (provided that their addresses aredifferent).
Note that only one set of pull-up resistors is neededper bus. A user might find that he or she needs tolower the pull-up resistor values slightly tocompensate for the additional bus capacitancepresented by multiple devices and increased linelength.
Figure 11. Using GPIO with a Single ADS1000
Bit-banging I
2
C with GPIO pins can be done bysetting the GPIO line to zero and toggling it betweeninput and output modes to apply the proper busstates. To drive the line low, the pin is set to output a'0'; to let the line go high, the pin is set to input.When the pin is set to input, the state of the pin canbe read; if another device is pulling the line low, thisdevice will read as a '0' in the port input register.
Note that no pull-up resistor is shown on the SCLline. In this simple case, the resistor is not needed;the microcontroller can simply leave the line onoutput, and set it to '1' or '0' as appropriate. It can dothis because the ADS1000 never drives its clock linelow. This technique can also be used with multipledevices, and has the advantage of lower currentconsumption resulting from the absence of aresistive pull-up.
If there are any devices on the bus that may drivetheir clock lines low, the above method should not beused; the SCL line should be high-Z or zero and apull-up resistor provided as usual. Note also that thiscannot be done on the SDA line in any case,because the ADS1000 does drive the SDA line lowFigure 10. Connecting Multiple ADS1000s
from time to time, as all I
2
C devices do.
Some microcontrollers have selectable strong pull-upcircuits built into the GPIO ports. In some cases,Most microcontrollers have programmable
these can be switched on and used in place of aninput/output pins that can be set in software to act as
external pull-up resistor. Weak pull-ups are alsoinputs or outputs. If an I
2
C controller is not available,
provided on some microcontrollers, but usually thesethe ADS1000 can be connected to GPIO pins, and
are too weak for I
2
C communication. If there is anythe I
2
C bus protocol simulated, or bit-banged, in
doubt about the matter, test the circuit beforesoftware. An example of this for a single ADS1000 is
committing it to production.shown in Figure 11 .
Although the ADS1000 has a fully differential input, itcan easily measure single-ended signals. A simplesingle-ended connection scheme is shown inFigure 12 . The ADS1000 is configured forsingle-ended measurement by grounding either of its
12
www.ti.com
LOW-SIDE CURRENT MONITOR
1
2
3
6
5
4
VIN-
VIN+
SCL
GND VDD
SDA
ADS1000
VDD
Output
Codes
0 2048-
FilterCapacitor
33pFto100pF
(typ.)
0V V
Single-Ended
-DD
NOTES:(1)Pull-downresistortoallowaccurateswingto0V.
(2)R issizedfora50mVdropatfull-scalecurrent.
S
V
Load
RS
(2) 1kW
G=12.5 -5V
OPA335
R
49.9k
3
W
(1)
FS=0.63V
5V
5V
11.5kW
ADS1000 I C
2
(PGAGain=8)
5VFS
ADS1000
SBAS357 – SEPTEMBER 2006
input pins, usually V
IN–
, and applying the input signalto V
IN+
. The single-ended signal can range from
Figure 13 shows a circuit for a low-side shunt-type–0.2V to V
DD
+ 0.3V. The ADS1000 loses no linearity
current monitor. The circuit reads the voltage acrossanywhere in its input range. Negative voltages
a shunt resistor, which is sized as small as possiblecannot be applied to this circuit because the
while still giving a readable output voltage. ThisADS1000 inputs can only accept positive voltages.
voltage is amplified by an OPA335 low-drift op-amp,and the result is read by the ADS1000.
Figure 12. Measuring Single-Ended Inputs
The ADS1000 input range is bipolar differential withrespect to the reference, that is, ±V
DD
. Thesingle-ended circuit shown in Figure 12 covers only
Figure 13. Low-Side Current Measurementhalf the ADS1000 input scale because it does notproduce differentially negative inputs; therefore, one
It is recommended that the ADS1000 be operated atbit of resolution is lost. The DRV134 balanced line
a gain of 8. The gain of the OPA335 can then be setdriver can be employed to regain this bit for
lower. For a gain of 8, the op amp should besingle-ended signals.
configured to give a maximum output voltage of nogreater than 0.75V. If the shunt resistor is sized toNegative input voltages must be level-shifted. A good
provide a maximum voltage drop of 50mV atcandidate for this function is the THS4130 differential
full-scale current, the full-scale input to the ADS1000amplifier, which can output fully differential signals.
is 0.63V.This device can also help recover the lost bit notedpreviously for single-ended positive signals.Level-shifting can also be performed using theDRV134.
13
www.ti.com
ADDITIONAL RECOMMENDATIONS
ADS1000
SBAS357 – SEPTEMBER 2006
stabilized; this momentary spike can damage theADS1000. Sometimes this damage is incrementalThe ADS1000 is fabricated in a small-geometry
and results in slow, long-term failure—which can below-voltage process. The analog inputs feature
distastrous for permanently installed, low-protection diodes to the supply rails. However, the
maintenance systems.current-handling ability of these diodes is limited, andthe ADS1000 can be permanently damaged by If using an op amp or other front-end circuitry withanalog input voltages that remain more than the ADS1000, be sure to take the performanceapproximately 300mV beyond the rails for extended characteristics of this circuitry into account; a chain isperiods. One way to protect against overvoltage is to only as strong as its weakest link.place current-limiting resistors on the input lines. The
Any data converter is only as good as its reference.ADS1000 analog inputs can withstand momentary
For the ADS1000, the reference is the power supply,currents of as large as 10mA.
and the power supply must be clean enough toThe previous paragraph does not apply to the I
2
C achieve the desired performance. If a power-supplyports, which can both be driven to 6V regardless of filter capacitor is used, it should be placed close tothe supply. the V
DD
pin, with no vias placed between thecapacitor and the pin. The trace leading to the pinIf the ADS1000 is driven by an op amp with high
should be as wide as possible, even if it must bevoltage supplies, such as ±12V, protection should be
necked down at the device.provided, even if the op amp is configured so that itwill not output out-of-range voltages. Many op ampsseek to one of the supply rails immediately whenpower is applied, usually before the input has
14
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS1000A0IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A0IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A0IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A0IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A1IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A1IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A1IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1000A1IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Oct-2006
Addendum-Page 1
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