FM31T378-GTR - Ramtron - Product.Network

Preliminary

This is a product that has fixed target specifications but are subject Ramtron International Corporation

to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-FRAM, (719) 481-7000

Rev. 1.1 http://www.ramtron.com

Apr. 2011 Page 1 of 26

FM31T372/374/376/378

System Supervisor & Temperature Compensated RTC

(TCXO) with Embedded Crystal

Features

High Integration Device Replaces Multiple Parts

 Real-time Clock (RTC)

o Embedded 32.768kHz Crystal

o Temperature Compensated

 32.768 kHz Clock Output

 Low-VDD Detection Drives Reset

 Watchdog Timer

 Early Power-Fail Warning/NMI

 Two 16-bit Event Counters with Event Driven

Interrupt Output

 Serial Number with Write-lock for Security

Ferroelectric Nonvolatile RAM

 4Kb, 16Kb, 64Kb, and 256Kb versions

 Unlimited Read/Write Endurance

 10 year Data Retention

 NoDelay™ Writes

Real-time Clock/Calendar

 Temp-Compensated Using On-Chip Sensor

o  5 ppm over -40°C to +85°C

o Accuracy  2 ½ min. per year

 Backup Current 1.4 A (max.) at +25C

 Seconds through Centuries in BCD format

 Tracks Leap Years through 2099

 No External Crystal Required

 Offset Register to Correct for Crystal Aging

 Supports Battery or Capacitor Backup

Processor Companion

 32.768 kHz Clock Output

 Active-low Reset Output for VDD and Watchdog

 Programmable VDD Reset Trip Point

 Manual Reset Filtered and Debounced

 Programmable Watchdog Timer

 Dual Battery-backed Event Counter Tracks

System Intrusions or other Events

 Event Counter Driven Interrupt Output

 Comparator for Early Power-Fail Interrupt

 64-bit Programmable Serial Number with Lock

Fast Two-wire Serial Interface

 Up to 1 MHz Maximum Bus Frequency

 Supports Legacy Timing for 100 kHz & 400 kHz

 Device Select Pins for up to 4 Memory Devices

 RTC, Supervisor Controlled via 2-wire Interface

Easy to Use Configurations

 Operates from 2.7 to 5.5V

 Small Footprint 14-pin “Green” SOIC (-G)

 Low Operating Current

 -40C to +85C Operation

Description

The FM31T37x is a family of integrated devices that

includes the most commonly needed functions for

processor-based systems. Major features include

nonvolatile F-RAM memory available in various

sizes, temperature-compensated real-time clock with

embedded crystal, 32.768kHz clock output,

low-VDD reset, watchdog timer, battery backed

event counter, event driven interrupt output, lockable

64-bit serial number area, general purpose

comparator that can be used for an early power-fail

(NMI) interrupt or other purpose, and 2-wire serial

interface to a host microcontroller. The family

operates from 2.7 to 5.5V.

The real-time clock (RTC) provides time and date

information in BCD format. It can be permanently

powered from external backup voltage source, either

a battery or a capacitor. The timekeeper uses an

internal 32.768 kHz crystal which is factory-

calibrated for excellent timekeeping accuracy over

the industrial temperature range.

The FM31T37x devices integrate 4Kb, 16Kb, 64Kb,

and 256Kb of F-RAM memory. F-RAM offers

superior write speed and unlimited endurance. This

allows the memory to provide system data collection

and as read/write RAM storage. This memory is truly

nonvolatile rather than battery-backed.

The processor companion includes commonly needed

CPU support functions. Supervisory functions

include a reset output signal controlled by either a

low VDD condition or a watchdog timeout. /RST

goes active when VDD drops below a programmable

threshold and remains active for 100 ms after VDD

rises above the trip point. A programmable watchdog

timer runs from 100 ms to 3 seconds. The watchdog

timer is optional, but if enabled it will assert the reset

signal for 100 ms if not restarted by the host before

the timeout. A flag-bit indicates the source of the

reset.

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 2 of 26

A general-purpose comparator compares an external

input pin to the onboard 1.2V reference. This is

useful for generating a power-fail interrupt (NMI) but

can be used for any purpose. The family also includes

a programmable 64-bit serial number that can be

locked making it unalterable. Additionally it offers a

dual battery-backed event counter that tracks the

number of rising or falling edges detected on

dedicated input pins.

Pin Configuration

Pin Name

Function

CNT1, CNT2

Event Counter Inputs

A0, A1

Device Select inputs

CAL/PFO

Clock Calibration and Early

Power-Fail Output

/RST

Reset Input/Output

VSS

Ground

VBAK

Battery-Backup Supply

PFI

Early Power-fail Input

/INT

Event Counter Driven Interrupt

Output

FOUT

32.768 kHz Clock Output

SDA

Serial Data

SCL

Serial Clock

VDD

Supply Voltage

Ordering Information

Base Configuration

Memory Size

Operating Voltage

Reset Threshold

Ordering Part Number

FM31T378

256Kb

2.7-5.5V

2.6V, 2.9, 3.9, 4.4V

FM31T378-G

FM31T376

64Kb

2.7-5.5V

2.6V, 2.9, 3.9, 4.4V

FM31T376-G

FM31T374

16Kb

2.7-5.5V

2.6V, 2.9, 3.9, 4.4V

FM31T374-G

FM31T372

4Kb

2.7-5.5V

2.6V, 2.9, 3.9, 4.4V

FM31T372-G

VDD

VBAK

SCL

SDA

VSS

/INT

FOUT

CAL/PFO

CNT1

PFI

RST

A0

A1

CNT2

1

2

3

4

5

6

7

14

13

12

11

10

9

8

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 3 of 26

Figure 1. Block Diagram

Pin Descriptions

Pin Name

Type

Pin Description

A0, A1

Input

Device select inputs are used to address multiple memories on a serial bus. To select the device

the address value on the two pins must match the corresponding bits contained in the device

address. The device select pins are pulled down internally.

CNT1, CNT2

Input

Event Counter Inputs: These battery-backed inputs increment counters when an edge is detected

on the corresponding CNT pin. The polarity is programmable. These pins should not be left

floating. Tie to ground if pins are not used.

/INT

Output

Event Counter Driven Interrupt Output. This is a battery backed open-drain output. It goes low

for at least 100 ms upon changes on either CNT1 or CNT2 pin. This pin can be left floating if

not used.

CAL/PFO

Output

In normal operation, this is the early power-fail output. In CAL mode, it supplies a 512 Hz

square-wave output for clock calibration.

FOUT

Output

32.768kHz Clock Output. This is a battery backed open-drain output. This pin can be disabled

by setting the FOEN bit to “0”. This pin can be left floating if not used.

/RST

I/O

Active low reset output with weak pull-up. Also input for manual reset.

SDA

I/O

Serial Data & Address: This is a bi-directional line for the two-wire interface. It is open-drain

and is intended to be wire-OR‟d with other devices on the two-wire bus. The input buffer

incorporates a Schmitt trigger for noise immunity and the output driver includes slope control

for falling edges. A pull-up resistor is required.

SCL

Input

Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the device

on the falling edge, and into the device on the rising edge. The SCL input also incorporates a

Schmitt trigger input for noise immunity.

PFI

Input

Early Power-fail Input: Typically connected to an unregulated power supply to detect an early

power failure. This pin should not be left floating.

VBAK

Supply

Backup supply voltage: A 3V battery or a large value capacitor. If no backup supply is used, this

pin should be tied to VDD.

VDD

Supply

Supply Voltage

F-RAM

Array

2-Wire

Interface

SCL

SDA

RST

A1, A0

CAL/PFO

PFI

VDD

VBAK

Temperature

Compensated

RTC

~2.4V

-

+

RTC Registers

Event

Counters

CNT1

CNT2

Special

Function

Registers

S/N

FOUT

/INT

LockOut

+

-

1.2V

Watchdog

LV Detect

Switched Power

512Hz

Battery Backed

Nonvolatile

32.768

kHz

Temp

Sensor

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 4 of 25

Overview

The FM31T37x family combines a serial nonvolatile

F-RAM, a temperature compensated real-time clock

with embedded crystal, and a processor companion.

The companion is a highly integrated peripheral

including a processor supervisor, a comparator used

for early power-fail warning, nonvolatile event

counters, and a 64-bit serial number. The FM31T37x

integrates these complementary but distinct functions

that share a common interface in a single package.

Although monolithic, the product is organized as two

logical devices, the F-RAM memory, and the

RTC/companion. From the system perspective they

appear to be two separate devices with unique IDs on

the serial bus.

The memory is organized as a stand-alone 2-wire

nonvolatile memory with a standard device ID value.

The real-time clock and supervisor functions are

accessed with a separate 2-wire device ID. This

allows clock/calendar data to be read while

maintaining the most recently used memory address.

The clock and supervisor functions are controlled by

21 special function registers. The RTC and event

counter circuits are maintained by the power source

on the VBAK pin, allowing them to operate from

battery or backup capacitor power when VDD drops

below an internally set threshold. Each functional

block is described below.

Memory Operation

The FM31T37x is a family of products available in

different memory sizes including 4Kb, 16Kb, 64Kb,

and 256Kb. The family is software compatible, all

versions use consistent two-byte addressing for the

memory device. This makes the lowest density

device different from its stand-alone memory

counterparts but makes them compatible within the

entire family.

Memory is organized in bytes, for example the 4Kb

memory is 512 x 8 and the 256Kb memory is 32,768

x 8. The memory is based on F-RAM technology.

Therefore it can be treated as RAM and is read or

written at the speed of the two-wire bus with no

delays for write operations. It also offers effectively

unlimited write endurance unlike other nonvolatile

memory technologies. The 2-wire interface protocol

is described further on page 13.

The memory array can be write-protected by

software. Two bits in the processor companion area

(WP0, WP1 in register 0Bh) control the protection

setting as shown in the following table. Based on the

setting, the protected addresses cannot be written and

the 2-wire interface will not acknowledge any data to

protected addresses. The special function registers

containing these bits are described in detail below.

Write protect addresses WP1 WP0

None 0 0

Bottom ¼ 0 1

Bottom ½ 1 0

Full array 1 1

Processor Companion

In addition to nonvolatile RAM, the FM31T37x

family incorporates a highly integrated processor

companion. It includes a low voltage reset, a

programmable watchdog timer, battery-backed event

counters with interrupt output, a comparator for early

power-fail detection or other purposes, and a 64-bit

serial number.

Processor Supervisor

Supervisors provide a host processor two basic

functions: detection of power supply fault conditions

and a watchdog timer to escape a software lockup

condition. All FM31T37x devices have a reset pin

(/RST) to drive the processor reset input during

power faults (and power-up) and software lockups. It

is an open-drain output with a weak internal pull-up

to VDD. This allows other reset sources to be

wire-OR‟d to the /RST pin. When VDD is above the

programmed trip point, /RST output is pulled weakly

to VDD. If VDD drops below the reset trip point

voltage level (VTP) the /RST pin will be driven low. It

will remain low until VDD falls too low for circuit

operation which is the VRST level. When VDD rises

again above VTP, /RST will continue to drive low for

at least 100 ms (tRPU) to ensure a robust system reset

at a reliable VDD level. After tRPU has been met, the

/RST pin will return to the weak high state. While

/RST is asserted, serial bus activity is locked out even

if a transaction occurred as VDD dropped below VTP.

A memory operation started while VDD is above VTP

will be completed internally.

Figure 2 below illustrates the reset operation in

response to the VDD voltage.

Figure 2. Low Voltage Reset

VDD

VTP

tRPU

RST

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Apr. 2011 Page 5 of 26

The bits VTP1 and VTP0 control the trip point of the

low voltage detect circuit. They are located in register

0Bh, bits 1 and 0.

VTP VTP1 VTP0

2.6V 0 0

2.9V 0 1

3.9V 1 0

4.4V 1 1

The watchdog timer can also be used to assert the

reset signal (/RST). The watchdog is a free running

programmable timer. The period can be software

programmed from 100 ms to 3 seconds in 100 ms

increments via a 5-bit nonvolatile register. All

programmed settings are minimum values and vary

with temperature according to the operating

specifications. The watchdog has two additional

controls associated with its operation, a watchdog

enable bit (WDE) and timer restart bits (WR). Both

the enable bit must be set and the watchdog must

timeout in order to drive /RST active. If a reset event

occurs, the timer will automatically restart on the

rising edge of the reset pulse. If WDE=0, the

watchdog timer runs but a watchdog fault will not

cause /RST to be asserted low. The WTR flag will be

set, indicating a watchdog fault. This setting is useful

during software development and the developer does

not want /RST to drive. Note that setting the

maximum timeout setting (11111b) disables the

counter to save power. The second control is a nibble

that restarts the timer preventing a reset. The timer

should be restarted after changing the timeout value.

The watchdog timeout value is located in register

0Ah, bits 4-0, and the watchdog enable is bit 7. The

watchdog is restarted by writing the pattern 1010b to

the lower nibble of register 09h. Writing this pattern

will also cause the timer to load new timeout values.

Writing other patterns to this address will not affect

its operation. Note the watchdog timer is

free-running. Prior to enabling it, users should restart

the timer as described above. This assures that the

full timeout period will be set immediately after

enabling. The watchdog is disabled when VDD is

below VTP. The following table summarizes the

watchdog bits. A block diagram follows.

Watchdog timeout WDT4-0 0Ah, bits 4-0

Watchdog enable WDE 0Ah, bit 7

Watchdog restart WR3-0 09h, bits 3-0

Figure 3. Watchdog Timer

Manual Reset

The /RST pin is bi-directional and allows the

FM31T37x to filter and de-bounce a manual reset

switch. The /RST input detects an external low

condition and responds by driving the /RST signal

low for 100 ms. A manual reset does not set any

flags.

Figure 4. Manual Reset

Note that an internal weak pull-up on /RST

eliminates the need for additional external

components.

Reset Flags

In case of a reset condition, a flag will be set to

indicate the source of the reset. A low VDD reset is

indicated by the POR flag, register 09h bit 6. A

watchdog reset is indicated by the WTR flag, register

09h bit 7. Note that the flags are internally set in

response to reset sources, but they must be cleared by

the user. When the register is read, it is possible that

both flags are set if both have occurred since the user

last cleared them.

Early Power Fail Comparator

An early power fail warning can be provided to the

processor well before VDD drops out of spec. The

comparator is used to create a power fail interrupt

(NMI). This can be accomplished by connecting the

PFI pin to the unregulated power supply via a resistor

divider. An application circuit is shown below.

Timebase

Counter

Watchdog

timeout

100 ms

clock

WDE

/RST

WR3-0

= 1010b to restart

FM31T37x

Reset

Switch

RST

MCU

Switch

Behavior

RST

FM31T37x

drives

100 ms (min.)

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 6 of 26

Figure 5. Comparator as Early Power-Fail Warning

The voltage on the PFI input pin is compared to an

onboard 1.2V reference. When the PFI input voltage

drops below this threshold, the comparator will drive

the CAL/PFO pin to a low state. The comparator has

100 mV (max) of hysteresis to reduce noise

sensitivity, only for a rising PFI signal. For a falling

PFI edge, there is no hysteresis.

The comparator is a general purpose device and its

application is not limited to the NMI function.

The comparator is not integrated into the special

function registers except as it shares its output pin

with the CAL output. When the CAL mode is

invoked by setting the CAL bit (register 00h, bit 2),

the CAL/PFO output pin is driven with a 512 Hz

square wave and the comparator will be ignored.

Since most users only invoke the CAL mode during

production, this should have no impact on system

operations using the comparator.

Event Counter

The FM31T37x offers the user two battery-backed

event counters. Input pins CNT1 and CNT2 are

programmable edge detectors. Each clocks a 16-bit

counter. When an edge occurs, the counters will

increment their respective registers. Counter 1 is

located in registers 0Dh and 0Eh, Counter 2 is

located in registers 0Fh and 10h. These register

values can be read anytime VDD is above VTP, and

they will be incremented as long as a valid VBAK

power source is provided. To read, set the RC bit

register 0Ch bit 3 to 1. This takes a snapshot of all

four counter bytes allowing a stable value even if a

count occurs during the read. The registers can be

written by software allowing the counters to be

cleared or initialized by the system. Counts are

blocked during a write operation. The two counters

can be cascaded to create a single 32-bit counter by

setting the CC control bit (register 0Ch). When

cascaded, the CNT1 input will cause the counter to

increment. CNT2 is not used in this mode.

Figure 6. Event Counter

The control bits for event counting are located in

register 0Ch. Counter 1 Polarity is bit C1P, bit 0;

Counter 2 Polarity is C2P, bit 1; the Cascade Control

is CC, bit 2; and the Read Counter bit is RC bit 3.

The polarity bits must be set prior to setting the

counter value(s). If a polarity bit is changed, the

counter may inadvertently increment. If the counter

pins are not being used, tie them to ground.

Event Counter Driven Interrupt Output

The event counter driven interrupt is a battery backed

open-drain output (/INT). A 100ms active low pulse

generated for the host microcontroller upon changes

on either CNT1 or CNT2 pins. The CNT2 pin will

not generate an interrupt if the CC bit is set to „1‟

(counter set to cascaded 32-bit mode).

Figure 7. Event Counter Driven Interrupt Output

Serial Number

A memory location to write a 64-bit serial number is

provided. It is a writeable nonvolatile memory block

that can be locked by the user once the serial number

is set. The 8 bytes of data and the lock bit are all

accessed via the device ID for the processor

companion. Therefore the serial number area is

separate and distinct from the memory array. The

serial number registers can be written an unlimited

number of times, so these locations are general

purpose memory. However once the lock bit is set the

values cannot be altered and the lock cannot be

removed. Once locked the serial number registers can

still be read by the system.

FM31T37x

INT

MCU

INT

Event occur

100 ms

16-bit Counter

CNT1

CC

CNT2

C1P

C2P

16-bit Counter

+

-

1.2V ref

Regulator

VDD

FM31T37x

To MCU

NMI input

CAL/PFO

PFI

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 7 of 26

The serial number is located in registers 11h to 18h.

The lock bit is SNL, register 0Bh bit 7. Setting the

SNL bit to „1‟ disables writes to the serial number

registers, and the SNL bit cannot be cleared.

Real-Time Clock (TCXO) Operation

The real-time clock is a timekeeping function that

can be battery or capacitor backed for continuous

operation. The RTC is operated by a temperature

compensated crystal oscillator (TCXO) based on an

embedded 32.768 kHz crystal.

The RTC consists of an oscillator, clock divider, and

a register system for user access. It divides down the

32.768 kHz time-base and provides a minimum

resolution of seconds (1Hz). Static registers provide

the user with read/write access to the time values. It

includes registers for seconds, minutes, hours,

day-of-the-week, date, months, and years. A block

diagram (Figure 8) illustrates the RTC function.

The user registers are synchronized with the

timekeeper core using R and W bits in register 00h

described below. Changing the R bit from „0‟ to „1‟

transfers timekeeping information from the core into

holding registers that can be read by the user. If a

timekeeper update is pending when R is set, then the

core will be updated prior to loading the user

registers. The registers are frozen and will not be

updated again until the R bit is cleared to „0‟. R is

used for reading the time.

Setting the W bit to „1‟ locks the user registers.

Clearing it to „0‟ causes the values in the user

registers to be loaded into the timekeeper core. W is

used for writing new time values. Users should be

certain not to load invalid values, such as FFh, to the

timekeeping registers. Updates to the timekeeping

core occur continuously except when locked.

Backup Power

The real-time clock/calendar is intended to be

permanently powered. When the primary system

power fails, the voltage on the VDD pin will drop.

When VDD is less 2.4V the RTC (and event counters)

will switch to the backup power supply on VBAK. The

clock operates at extremely low current in order to

maximize battery or capacitor life. However, an

advantage of combining a clock function with

F-RAM memory is that data is not lost regardless of

the backup power source.

The IBAK current varies with temperature and voltage

(see DC parametric table). The following graph

shows IBAK as a function of VBAK. These curves are

useful for calculating backup time when a capacitor

is used as the VBAK source.

Figure 8. IBAK vs. VBAK Voltage

The minimum VBAK voltage varies linearly with

temperature. The user can expect the minimum VBAK

voltage to be 1.23V at +85°C and 1.90V at -40°C.

The tested limit is 1.55V at +25°C. The minimum

VBAK voltage has been characterized at -40°C and

+85°C but is not 100% tested.

Figure 9. VBAK (min.) vs. Temperature

Trickle Charger

To facilitate capacitor backup, the VBAK pin can

optionally provide a trickle charge current. When the

VBC bit, register 0Bh bit 2, is set to „1‟ the VBAK pin

will source approximately 80µA until VBAK reaches

VDD or 3.75V whichever is less. In 3V systems, this

charges the capacitor to VDD without an external

diode and resistor charger. There is a Fast Charge

mode which is enabled by the FC bit (register 0Bh,

bit 5). In this mode the trickle charger current is set to

approximately 1 mA, allowing a large backup

capacitor to charge more quickly.

In the case where no battery is used, the VBAK pin

should be tied to VDD.

Although VBAK may be connected to VSS, this is not

recommended if the companion is used. None of

the companion functions will operate below

approximately 2.4V.

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 8 of 26

Note: Systems using lithium batteries should clear the

VBC bit to ‘0’ to prevent battery charging. The VBAK

circuitry includes an internal 1 K



series resistor as

a safety element.

32.768 kHz Clock Output

The 32.768 kHz clock (with precision equal to that of

the built-in crystal oscillator) can be output via the

FOUT pin. This output is not temperature

compensated. This clock can be disabled by clearing

the FOEN bit to „0‟.

Figure 8. Real-Time Clock Core Block Diagram

Offset/Aging Compensation

The user can expect the RTC to be accurate from the

factory. The RTC is calibrated at the factory at room

temperature. The CAL bits setting in Register 01h

will likely be a non-zero value. This is the initial

calibration value assigned at the factory prior to

shipment. The device may need re-calibrating after

solder reflow or after some period of time due to

crystal aging.

If the user needs to re-calibrate the RTC, the

following describes the steps to change the

calibration setting. Before making changes to the

CAL bits, the user can read these bits to verify the

current setting is an expected value. To enter

calibration mode, the CAL bit in a register 00h must

be set to „1‟. When the RTC is in calibration mode,

the CAL/PFO output pin is dedicated to the

calibration function and the power fail output is

temporarily unavailable. Calibration operates by

applying a digital correction to the counter based on

the frequency error. In this mode, the CAL/PFO pin

is driven with a 512 Hz (nominal) square wave. Any

measured deviation from 512 Hz translates into a

timekeeping error. The 512Hz calibration output

must be measured at +25°C. This output is not

temperature compensated. The user converts the

measured error in ppm and writes the appropriate

correction value to the calibration register. The

correction factors are listed in the following tables.

Positive ppm errors require a negative adjustment

that removes pulses. Negative ppm errors require a

positive correction that adds pulses. Positive ppm

adjustments have the CALS (sign) bit set to „1‟,

whereas negative ppm adjustments have CALS = 0.

The calibration setting is stored in F-RAM so is not

lost should the backup source fail. It is accessed with

bits CAL.5-0 in register 01h. This value only can be

written when the CAL bit is set to „1‟. To exit the

calibration mode, the user must clear the CAL bit to a

0. When the CAL bit is 0, the CAL/PFO pin will

revert to the power fail output function.

Note: Temperature compensation is disabled when

the CAL bit is set to ‘1’. The user should clear this bit

to allow temperature compensation to activate.

32.768 kHz

crystal

Oscillator

Clock

Divider

Update

Logic

512 Hz

W

R

Seconds

7 bits

Minutes

7 bits

Hours

6 bits

Date

6 bits

Months

5 bits

Years

8 bits

CF

Days

3 bits

User Interface Registers

1 Hz

/OSCEN

32.768kHz

FM31T372/374/376/378-G

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Apr. 2011 Page 9 of 26

Calibration Adjustments for Offset/Aging

Positive Calibration for Slow Measured Clocks

Measured Frequency Range at +25°C

Error Range (PPM)

Min

Max

Min

Max

Program Calibration Register to:

0

512.0000

511.9995

0.00

-1.02

1000000

1

511.9995

511.9984

-1.02

-3.05

1000001

2

511.9984

511.9974

-3.05

-5.09

1000010

3

511.9974

511.9964

-5.09

-7.12

1000011

4

511.9964

511.9953

-7.12

-9.16

1000100

5

511.9953

511.9943

-9.16

-11.19

1000101

6

511.9943

511.9932

-11.19

-13.22

1000110

7

511.9932

511.9922

-13.22

-15.26

1000111

8

511.9922

511.9911

-15.26

-17.29

1001000

9

511.9911

511.9901

-17.29

-19.33

1001001

10

511.9901

511.9891

-19.33

-21.36

1001010

11

511.9891

511.9880

-21.36

-23.40

1001011

12

511.9880

511.9870

-23.40

-25.43

1001100

13

511.9870

511.9859

-25.43

-27.47

1001101

14

511.9859

511.9849

-27.47

-29.50

1001110

15

511.9849

511.9839

-29.50

-31.53

1001111

16

511.9839

511.9828

-31.53

-33.57

1010000

17

511.9828

511.9818

-33.57

-35.60

1010001

18

511.9818

511.9807

-35.60

-37.64

1010010

19

511.9807

511.9797

-37.64

-39.67

1010011

20

511.9797

511.9786

-39.67

-41.71

1010100

21

511.9786

511.9776

-41.71

-43.74

1010101

22

511.9776

511.9766

-43.74

-45.78

1010110

23

511.9766

511.9755

-45.78

-47.81

1010111

24

511.9755

511.9745

-47.81

-49.85

1011000

25

511.9745

511.9734

-49.85

-51.88

1011001

26

511.9734

511.9724

-51.88

-53.91

1011010

27

511.9724

511.9714

-53.91

-55.95

1011011

28

511.9714

511.9703

-55.95

-57.98

1011100

29

511.9703

511.9693

-57.98

-60.02

1011101

30

511.9693

511.9682

-60.02

-62.05

1011110

31

511.9682

511.9672

-62.05

-64.09

1011111

32

511.9672

511.9661

-64.09

-66.12

1100000

33

511.9661

511.9651

-66.12

-68.16

1100001

34

511.9651

511.9641

-68.16

-70.19

1100010

35

511.9641

511.9630

-70.19

-72.22

1100011

36

511.9630

511.9620

-72.22

-74.26

1100100

37

511.9620

511.9609

-74.26

-76.29

1100101

38

511.9609

511.9599

-76.29

-78.33

1100110

39

511.9599

511.9589

-78.33

-80.36

1100111

40

511.9589

511.9578

-80.36

-82.40

1101000

41

511.9578

511.9568

-82.40

-84.43

1101001

42

511.9568

511.9557

-84.43

-86.47

1101010

43

511.9557

511.9547

-86.47

-88.50

1101011

44

511.9547

511.9536

-88.50

-90.54

1101100

45

511.9536

511.9526

-90.54

-92.57

1101101

46

511.9526

511.9516

-92.57

-94.60

1101110

47

511.9516

511.9505

-94.60

-96.64

1101111

48

511.9505

511.9495

-96.64

-98.67

1110000

49

511.9495

511.9484

-98.67

-100.71

1110001

50

511.9484

511.9474

-100.71

-102.74

1110010

51

511.9474

511.9464

-102.74

-104.78

1110011

52

511.9464

511.9453

-104.78

-106.81

1110100

53

511.9453

511.9443

-106.81

-108.85

1110101

54

511.9443

511.9432

-108.85

-110.88

1110110

55

511.9432

511.9422

-110.88

-112.92

1110111

56

511.9422

511.9411

-112.92

-114.95

1111000

57

511.9411

511.9401

-114.95

-116.98

1111001

58

511.9401

511.9391

-116.98

-119.02

1111010

59

511.9391

511.9380

-119.02

-121.05

1111011

60

511.9380

511.9370

-121.05

-123.09

1111100

61

511.9370

511.9359

-123.09

-125.12

1111101

62

511.9359

511.9349

-125.12

-127.16

1111110

63

511.9349

511.9339

-127.16

-129.19

1111111

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 10 of 26

Negative Calibration for Fast Measured Clocks

Measured Frequency Range at +25°C

Error Range (PPM)

Min

Max

Min

Max

Program Calibration Register to:

0

512.0000

512.0005

0.00

1.02

0000000

1

512.0005

512.0016

1.02

3.05

0000001

2

512.0016

512.0026

3.05

5.09

0000010

3

512.0026

512.0036

5.09

7.12

0000011

4

512.0036

512.0047

7.12

9.16

0000100

5

512.0047

512.0057

9.16

11.19

0000101

6

512.0057

512.0068

11.19

13.22

0000110

7

512.0068

512.0078

13.22

15.26

0000111

8

512.0078

512.0089

15.26

17.29

0001000

9

512.0089

512.0099

17.29

19.33

0001001

10

512.0099

512.0109

19.33

21.36

0001010

11

512.0109

512.0120

21.36

23.40

0001011

12

512.0120

512.0130

23.40

25.43

0001100

13

512.0130

512.0141

25.43

27.47

0001101

14

512.0141

512.0151

27.47

29.50

0001110

15

512.0151

512.0161

29.50

31.53

0001111

16

512.0161

512.0172

31.53

33.57

0010000

17

512.0172

512.0182

33.57

35.60

0010001

18

512.0182

512.0193

35.60

37.64

0010010

19

512.0193

512.0203

37.64

39.67

0010011

20

512.0203

512.0214

39.67

41.71

0010100

21

512.0214

512.0224

41.71

43.74

0010101

22

512.0224

512.0234

43.74

45.78

0010110

23

512.0234

512.0245

45.78

47.81

0010111

24

512.0245

512.0255

47.81

49.85

0011000

25

512.0255

512.0266

49.85

51.88

0011001

26

512.0266

512.0276

51.88

53.91

0011010

27

512.0276

512.0286

53.91

55.95

0011011

28

512.0286

512.0297

55.95

57.98

0011100

29

512.0297

512.0307

57.98

60.02

0011101

30

512.0307

512.0318

60.02

62.05

0011110

31

512.0318

512.0328

62.05

64.09

0011111

32

512.0328

512.0339

64.09

66.12

0100000

33

512.0339

512.0349

66.12

68.16

0100001

34

512.0349

512.0359

68.16

70.19

0100010

35

512.0359

512.0370

70.19

72.22

0100011

36

512.0370

512.0380

72.22

74.26

0100100

37

512.0380

512.0391

74.26

76.29

0100101

38

512.0391

512.0401

76.29

78.33

0100110

39

512.0401

512.0411

78.33

80.36

0100111

40

512.0411

512.0422

80.36

82.40

0101000

41

512.0422

512.0432

82.40

84.43

0101001

42

512.0432

512.0443

84.43

86.47

0101010

43

512.0443

512.0453

86.47

88.50

0101011

44

512.0453

512.0464

88.50

90.54

0101100

45

512.0464

512.0474

90.54

92.57

0101101

46

512.0474

512.0484

92.57

94.60

0101110

47

512.0484

512.0495

94.60

96.64

0101111

48

512.0495

512.0505

96.64

98.67

0110000

49

512.0505

512.0516

98.67

100.71

0110001

50

512.0516

512.0526

100.71

102.74

0110010

51

512.0526

512.0536

102.74

104.78

0110011

52

512.0536

512.0547

104.78

106.81

0110100

53

512.0547

512.0557

106.81

108.85

0110101

54

512.0557

512.0568

108.85

110.88

0110110

55

512.0568

512.0578

110.88

112.92

0110111

56

512.0578

512.0589

112.92

114.95

0111000

57

512.0589

512.0599

114.95

116.98

0111001

58

512.0599

512.0609

116.98

119.02

0111010

59

512.0609

512.0620

119.02

121.05

0111011

60

512.0620

512.0630

121.05

123.09

0111100

61

512.0630

512.0641

123.09

125.12

0111101

62

512.0641

512.0651

125.12

127.16

0111110

63

512.0651

512.0661

127.16

129.19

0111111

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 11 of 26

Register Map

The TCXO and processor companion functions are accessed via 25 special function registers mapped to a separate

2-wire device ID. The interface protocol is described below. The registers contain timekeeping data, control bits, or

information flags. A description of each register follows the summary table below.

Register Map Summary Table

Nonvolatile = Battery-backed =

Data

Address D7 D6 D5 D4 D3 D2 D1 D0 Function Range

Serial Number Byte 7 Serial Number 7 FFh

Serial Number Byte 6 Serial Number 6 FFh

Serial Number Byte 5 Serial Number 5 FFh

Serial Number Byte 4 Serial Number 4 FFh

Serial Number Byte 3 Serial Number 3 FFh

Serial Number Byte 2 Serial Number 2 FFh

Serial Number Byte 1 Serial Number 1 FFh

Serial Number Byte 0 Serial Number 0 FFh

10h Counter 2 MSB Event Counter 2 MSB FFh

0Fh Counter 2 LSB Event Counter 2 LSB FFh

0Eh Counter 1 MSB Event Counter 1 MSB FFh

0Dh Counter 1 LSB Event Counter 1 LSB FFh

0Ch RC CC C2P C1P Event Count Control

0Bh SNL FOEN FC WP1 WP0 VBC VTP1 VTP0 Companion Control

0Ah WDE - - WDT4 WDT3 WDT2 WDT1 WDT0 Watchdog Control

09h WTR POR LB - WR3 WR2 WR1 WR0 Watchdog Restart/Flags

08h 10 years years Years 00-99

07h 0 0 0 10 mo months Month 1-12

06h 0 0 10 date date Date 1-31

05h 0 0 0 0 0 day Day 1-7

04h 0 0 10 hours hours Hours 0-23

03h 010 minutes minutes Minutes 0-59

02h 010 seconds seconds Seconds 0-59

01h /OSCEN CALS CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSC/CAL Control

00h reserved CF reserved reserved reserved CAL W R RTC Control

18h

17h

11h

16h

15h

14h

13h

12h

Note: When the device is first powered up and programmed, all registers must be written because the

battery-backed register values cannot be guaranteed. The table below shows the default values of the non-volatile

registers. All other register values should be treated as unknown.

Default Register Values

Address

Hex Value

18h

0x00

17h

0x00

16h

0x00

15h

0x00

14h

0x00

13h

0x00

12h

0x00

11h

0x00

0Bh

0x40

0Ah

0x1F

01h

Factory

programmed

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 12 of 26

Register Description

Address

Description

18h

Serial Number Byte 7

D7

D6

D5

D4

D3

D2

D1

D0

SN.63

SN.62

SN.61

SN.60

SN.59

SN.58

SN.57

SN.56

Upper byte of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

17h

Serial Number Byte 6

D7

D6

D5

D4

D3

D2

D1

D0

SN.55

SN.54

SN.53

SN.52

SN.51

SN.50

SN.49

SN.48

Byte 6 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

16h

Serial Number Byte 5

D7

D6

D5

D4

D3

D2

D1

D0

SN.47

SN.46

SN.45

SN.44

SN.43

SN.42

SN.41

SN.40

Byte 5 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

15h

Serial Number Byte 4

D7

D6

D5

D4

D3

D2

D1

D0

SN.39

SN.38

SN.37

SN.36

SN.35

SN.34

SN.33

SN.32

Byte 4 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

14h

Serial Number Byte 3

D7

D6

D5

D4

D3

D2

D1

D0

SN.31

SN.30

SN.29

SN.28

SN.27

SN.26

SN.25

SN.24

Byte 3 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

13h

Serial Number Byte 2

D7

D6

D5

D4

D3

D2

D1

D0

SN.23

SN.22

SN.21

SN.20

SN.19

SN.18

SN.17

SN.16

Byte 2 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

12h

Serial Number Byte 1

D7

D6

D5

D4

D3

D2

D1

D0

SN.15

SN.14

SN.13

SN.12

SN.11

SN.10

SN.9

SN.8

Byte 1 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

11h

Serial Number Byte 0

D7

D6

D5

D4

D3

D2

D1

D0

SN.7

SN.6

SN.5

SN.4

SN.3

SN.2

SN.1

SN.0

LSB of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.

10h

Counter 2 MSB

D7

D6

D5

D4

D3

D2

D1

D0

C2.15

C2.14

C2.13

C2.12

C2.11

C2.10

C2.9

C2.8

Event Counter 2 MSB. Increments on overflows from Counter 2 LSB. Battery-backed, read/write.

0Fh

Counter 2 LSB

D7

D6

D5

D4

D3

D2

D1

D0

C2.7

C2.6

C2.5

C2.4

C2.3

C2.2

C2.1

C2.0

Event Counter 2 LSB. Increments on programmed edge event on CNT2 input or overflows from Counter 1 MSB

when CC=1. Battery-backed, read/write .

0Eh

Counter 1 MSB

D7

D6

D5

D4

D3

D2

D1

D0

C1.15

C1.14

C1.13

C1.12

C1.11

C1.10

C1.9

C1.8

Event Counter 1 MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write.

0Dh

Counter 1 LSB

D7

D6

D5

D4

D3

D2

D1

D0

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write.

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 13 of 26

0Ch

Event Counter Control

D7

D6

D5

D4

D3

D2

D1

D0

-

RC

CC

C2P

C1P

RC

Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the

values without missing count events. The RC bit will be automatically cleared.

CC

Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by

C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of

Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is

“don‟t care” when CC=1. Battery-backed, read/write.

C2P

CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is “don‟t care” when CC=1. The value

of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write.

C1P

CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may

inadvertently increment if C1P is changed. Battery-backed, read/write.

0Bh

Companion Control

D7

D6

D5

D4

D3

D2

D1

D0

SNL

FOEN

FC

WP1

WP0

VBC

VTP1

VTP0

SNL

Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be

cleared once set to 1. Nonvolatile, read/write.

FOEN

32.768kHz Frequency Output Enable. Default is 1 = “On”. Output FOUT turned off when FOEN = 0.

Temperature compensation is not applied to the 32.768kHz frequency on the FOUT pin.

FC

Fast Charge: Setting FC to „1‟ (and VBC=1) causes a ~1 mA trickle charge current to be supplied on VBAK.

Clearing VBC to „0‟ disables the charge current. Nonvolatile, read/write.

WP1-0

Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write.

Write protect addresses WP1 WP0

None 0 0

Bottom ¼ 0 1

Bottom ½ 1 0

Full array 1 1

VBC

VBAK Charger Control. Setting VBC to 1 causes ~80 µA (FC=0) trickle charge current to be supplied on VBAK.

Clearing VBC to 0 disables the charge current. Nonvolatile, read/write.

VTP1-0

VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write.

VTP VTP1 VTP0

2.6V 0 0

2.9V 0 1

3.9V 1 0

4.4V 1 1

0Ah

Watchdog Control

D7

D6

D5

D4

D3

D2

D1

D0

WDE

-

WDT4

WDT3

WDT2

WDT1

WDT0

WDE

Watchdog Enable. When WDE=1, a watchdog timer fault will cause the /RST signal to go active. When WDE = 0

the timer runs but has no effect on /RST, however the WTR flag will be set when a fault occurs. Note as the timer

is free-running, users should restart the timer using WR3-0 prior to setting WDE=1. This assures a full watchdog

timeout interval occurs. Nonvolatile, read/write.

WDT4-0

Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog

timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.

Watchdog timeout WDT4 WDT3 WDT2 WDT1 WDT0

Invalid – default 100 ms 0 0 0 0 0

100 ms 0 0 0 0 1

200 ms 0 0 0 1 0

300 ms 0 0 0 1 1

.

2000 ms 1 0 1 0 0

2100 ms 1 0 1 0 1

2200 ms 1 0 1 1 0

.

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 14 of 26

.

2900 ms 1 1 1 0 1

3000 ms 1 1 1 1 0

Disable counter 1 1 1 1 1

09h

Watchdog Restart & Flags

D7

D6

D5

D4

D3

D2

D1

D0

WTR

POR

LB

-

WR3

WR2

WR1

WR0

WTR

Watchdog Timer Reset Flag: When a watchdog timer fault occurs, the WTR bit will be set to 1. It must be cleared

by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were

cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).

POR

Power-on Reset Flag: When the /RST pin is activated by a VDD < VTP condition, the POR bit will be set to 1. It

must be cleared by the user. Note that both WTR and POR could be set if the reset source has occurred since the

flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).

LB

Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the RTC and event

counters, this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed.

Read/Write (internally set, user can clear bit).

WR3-0

Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do

not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows

users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Battery-backed, Write-only.

08h

Timekeeping – Years

D7

D6

D5

D4

D3

D2

D1

D0

10 year.3

10 year.2

10 year.1

10 year.0

Year.3

Year.2

Year.1

Year.0

Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains

the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Battery-backed,

read/write.

07h

Timekeeping – Months

D7

D6

D5

D4

D3

D2

D1

D0

0

10 Month

Month.3

Month.2

Month.1

Month.0

Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9; upper

nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12.

Battery-backed, read/write.

06h

Timekeeping – Date of the month

D7

D6

D5

D4

D3

D2

D1

D0

0

10 date.1

10 date.0

Date.3

Date.2

Date.1

Date.0

Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9;

upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Battery-backed,

read/write.

05h

Timekeeping – Day of the week

D7

D6

D5

D4

D3

D2

D1

D0

0

Day.2

Day.1

Day.0

Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts

from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the

date. Battery-backed, read/write.

04h

Timekeeping – Hours

D7

D6

D5

D4

D3

D2

D1

D0

0

10 hours.1

10 hours.0

Hours.3

Hours2

Hours.1

Hours.0

Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates from 0 to

9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23.

Battery-backed, read/write.

03h

Timekeeping – Minutes

D7

D6

D5

D4

D3

D2

D1

D0

0

10 min.2

10 min.1

10 min.0

Min.3

Min.2

Min.1

Min.0

Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble

contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed,

read/write.

FM31T372/374/376/378-G

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02h

Timekeeping – Seconds

D7

D6

D5

D4

D3

D2

D1

D0

0

10 sec.2

10 sec.1

10 sec.0

Seconds.3

Seconds.2

Seconds.1

Seconds.0

Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble

contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write.

01h

OSC/Control

D7

D6

D5

D4

D3

D2

D1

D0

OSCEN

CALS

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

/OSCEN

/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the

oscillator can save battery power during storage. On a power-up without battery, this bit is set to 1.

Battery-backed, read/write.

CALS

Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction from

the time-base. Calibration is explained on page 8. This bit is factory programmed. Nonvolatile, read/write.

CAL.5-0

These six bits control the calibration of the clock. These bits are factory programmed. Nonvolatile, read/write.

00h

Flags/Control

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

CF

Reserved

CAL

W

R

Reserved

Reserved bits. Do not use. Should remain set to 0.

CF

Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to 00. This

indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new

century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user.

Battery-backed.

CAL

When set to 1, the CAL/PFO pin gives a 512 Hz square-wave output for clock audit. When CAL bit set to 0,

the clock operates normally, and the CAL/PFO pin is controlled by the power fail comparator. The CAL bit

must be cleared to enable temperature compensation. Temperature compensation is not applied to the 512Hz

frequency on the CAL/PFO pin. Battery-backed, read/write.

W

Write Time. Setting the W bit to 1 freezes the clock. The user can then write the timekeeping registers with

updated values. Resetting the W bit to 0 causes the contents of the time registers to be transferred to the

timekeeping counters and restarts the clock. Battery-backed, read/write.

R

Read Time. Setting the R bit to 1 copies a static image of the timekeeping core and place it into the user

registers. The user can then read them without concerns over changing values causing system errors. The R bit

going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again.

Battery-backed, read/write.

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Two-wire Interface

The FM31T37x employs an industry standard

two-wire bus that is familiar to many users. This

product is unique since it incorporates two logical

devices in one chip. Each logical device can be

accessed individually. Although monolithic, it

appears to the system software to be two separate

products. One is a memory device. It has a Slave

Address (Slave ID = 1010b) that operates the same

as a stand-alone memory device. The second device

is a real-time clock and processor companion which

have a unique Slave Address (Slave ID = 1101b).

By convention, any device that is sending data onto

the bus is the transmitter while the target device for

this data is the receiver. The device that is

controlling the bus is the master. The master is

responsible for generating the clock signal for all

operations. Any device on the bus that is being

controlled is a slave. The FM31T37x is always a

slave device.

The bus protocol is controlled by transition states in

the SDA and SCL signals. There are four conditions:

Start, Stop, Data bit, and Acknowledge. The figure

below illustrates the signal conditions that specify

the four states. Detailed timing diagrams are shown

in the Electrical Specifications section.

Stop

(Master) Start

(Master)

7

Data bits

(Transmitter)

6 0

Data bit

(Transmitter)Acknowledge

(Receiver)

SCL

SDA

Figure 9. Data Transfer Protocol

Start Condition

A Start condition is indicated when the bus master

drives SDA from high to low while the SCL signal is

high. All read and write transactions begin with a

Start condition. An operation in progress can be

aborted by asserting a Start condition at any time.

Aborting an operation using the Start condition will

ready the FM31T37x for a new operation.

If the power supply drops below the specified VTP

during operation, any 2-wire transaction in progress

will be aborted and the system must issue a Start

condition prior to performing another operation.

Stop Condition

A Stop condition is indicated when the bus master

drives SDA from low to high while the SCL signal is

high. All operations must end with a Stop condition.

If an operation is pending when a stop is asserted,

the operation will be aborted. The master must have

control of SDA (not a memory read) in order to

assert a Stop condition.

Data/Address Transfer

All data transfers (including addresses) take place

while the SCL signal is high. Except under the two

conditions described above, the SDA signal should

not change while SCL is high.

Acknowledge

The Acknowledge (ACK) takes place after the 8th

data bit has been transferred in any transaction.

During this state the transmitter must release the

SDA bus to allow the receiver to drive it. The

receiver drives the SDA signal low to acknowledge

receipt of the byte. If the receiver does not drive

SDA low, the condition is a No-Acknowledge

(NACK) and the operation is aborted.

The receiver might NACK for two distinct reasons.

First is that a byte transfer fails. In this case, the

NACK ends the current operation so that the part can

be addressed again. This allows the last byte to be

recovered in the event of a communication error.

Second and most common, the receiver does not

send an ACK to deliberately terminate an operation.

For example, during a read operation, the FM31T37x

will continue to place data onto the bus as long as the

receiver sends ACKs (and clocks). When a read

operation is complete and no more data is needed,

the receiver must NACK the last byte. If the receiver

ACKs the last byte, this will cause the FM31T37x to

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 17 of 26

attempt to drive the bus on the next clock while the

master is sending a new command such as a Stop.

Slave Address

The first byte that the FM31T37x expects after a

Start condition is the slave address. As shown in

figures below, the slave address contains the Slave

ID, Device Select address, and a bit that specifies if

the transaction is a read or a write.

The FM31T37x has two Slave Addresses (Slave IDs)

associated with two logical devices. To access the

memory device, bits 7-4 should be set to 1010b. The

other logical device within the FM31T37x is the

real-time clock and companion. To access this

device, bits 7-4 of the slave address should be set to

1101b. A bus transaction with this slave address

will not affect the memory in any way. The figures

below illustrate the two Slave Addresses.

The Device Select bits allow multiple devices of the

same type to reside on the 2-wire bus. The device

select bits (bits 2-1) select one of four parts on a

two-wire bus. They must match the corresponding

value on the external address pins in order to select

the device. Bit 0 is the read/write bit. A “1” indicates

a read operation, and a “0” indicates a write

operation.

1 0 1 0 X A1 A0 R/W

Slave ID Device

Select

7 6 5 4 3 2 1 0

Figure 10. Slave Address - Memory

Figure 11. Slave Address – Companion

Addressing Overview – Memory

After the FM31T37x acknowledges the Slave

Address, the master can place the memory address

on the bus for a write operation. The address requires

two bytes. This is true for all members of the family.

Therefore the 4Kb and 16Kb configurations will be

addressed differently from stand alone serial

memories but the entire family will be upwardly

compatible with no software changes.

The first is the MSB (upper byte). For a given

density unused address bits are don‟t cares, but

should be set to 0 to maintain upward compatibility.

Following the MSB is the LSB (lower byte) which

contains the remaining eight address bits. The

address is latched internally. Each access causes the

latched address to be incremented automatically. The

current address is the value that is held in the latch,

either a newly written value or the address following

the last access. The current address will be held as

long as VDD > VTP or until a new value is written.

Accesses to the clock do not affect the current

memory address. Reads always use the current

address. A random read address can be loaded by

beginning a write operation as explained below.

After transmission of each data byte, just prior to the

Acknowledge, the FM31T37x increments the

internal address. This allows the next sequential byte

to be accessed with no additional addressing

externally. After the last address is reached, the

address latch will roll over to 0000h. There is no

limit to the number of bytes that can be accessed

with a single read or write operation.

Addressing Overview – RTC & Companion

The RTC and Processor Companion operate in a

similar manner to the memory, except that it uses

only one byte of address. Addresses 00h to 18h

correspond to special function registers. Attempting

to load addresses above 18h is an illegal condition;

the FM31 xxT37x will return a NACK and abort the

2-wire transaction.

Data Transfer

After the address information has been transmitted,

data transfer between the bus master and the

FM31T37x begins. For a read, the FM31T37x will

place 8 data bits on the bus then wait for an ACK

from the master. If the ACK occurs, the FM31T37x

will transfer the next byte. If the ACK is not sent, the

FM31T37x will end the read operation. For a write

operation, the FM31T37x will accept 8 data bits

from the master then send an Acknowledge. All data

transfer occurs MSB (most significant bit) first.

Memory Write Operation

All memory writes begin with a Slave Address, then

a memory address. The bus master indicates a write

operation by setting the slave address LSB to a 0.

After addressing, the bus master sends each byte of

data to the memory and the memory generates an

Acknowledge condition. Any number of sequential

bytes may be written. If the end of the address range

1

0

1

X

A1

A0

R/W

Slave ID

7

6

5

4

3

2

1

0

Device

Select

1

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 18 of 26

is reached internally, the address counter will wrap

to 0000h. Internally, the actual memory write occurs

after the 8th data bit is transferred. It will be complete

before the Acknowledge is sent. Therefore, if the

user desires to abort a write without altering the

memory contents, this should be done using a Start

or Stop condition prior to the 8th data bit. The figures

below illustrate a single- and multiple-writes to

memory.

S ASlave Address 0 Address MSB A Data Byte A P

By Master

By FM31xxx

Start Address & Data Stop

Acknowledge

Address LSB A

Figure 12. Single Byte Memory Write

S ASlave Address 0 Address MSB A Data Byte A P

By Master

By FM31xxx

Start

Address & Data Stop

Acknowledge

Address LSB A Data Byte A

Figure 13. Multiple Byte Memory Write

Memory Read Operation

There are two types of memory read operations. They

are current address read and selective address read. In

a current address read, the FM31T37x uses the

internal address latch to supply the address. In a

selective read, the user performs a procedure to first

set the address to a specific value.

Current Address & Sequential Read

As mentioned above the FM31T37x uses an internal

latch to supply the address for a read operation. A

current address read uses the existing value in the

address latch as a starting place for the read

operation. The system reads from the address

immediately following that of the last operation.

To perform a current address read, the bus master

supplies a slave address with the LSB set to 1. This

indicates that a read operation is requested. After

receiving the complete device address, the

FM31T37x will begin shifting data out from the

current address on the next clock. The current address

is the value held in the internal address latch.

Beginning with the current address, the bus master

can read any number of bytes. Thus, a sequential read

is simply a current address read with multiple byte

transfers. After each byte the internal address counter

will be incremented.

Each time the bus master acknowledges a byte,

this indicates that the FM31T37x should read

out the next sequential byte.

There are four ways to terminate a read operation.

Failing to properly terminate the read will most likely

create a bus contention as the FM31T37x attempts to

read out additional data onto the bus. The four valid

methods follow.

1. The bus master issues a NACK in the 9th clock

cycle and a Stop in the 10th clock cycle. This is

illustrated in the diagrams below and is

preferred.

2. The bus master issues a NACK in the 9th clock

cycle and a Start in the 10th.

3. The bus master issues a Stop in the 9th clock

cycle.

4. The bus master issues a Start in the 9th clock

cycle.

If the internal address reaches the top of memory, it

will wrap around to 0000h on the next read cycle.

The figures below show the proper operation for

current address reads.

By FM31T37x

FM31T372/374/376/378-G

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Apr. 2011 Page 19 of 26

Selective (Random) Read

There is a simple technique that allows a user to

select a random address location as the starting point

for a read operation. This involves using the first

three bytes of a write operation to set the internal

address followed by subsequent read operations.

To perform a selective read, the bus master sends out

the slave address with the LSB set to 0. This specifies

a write operation. According to the write protocol,

the bus master then sends the address bytes that are

loaded into the internal address latch. After the

FM31T37x acknowledges the address, the bus master

issues a Start condition. This simultaneously aborts

the write operation and allows the read command to

be issued with the slave address LSB set to a 1. The

operation is now a read from the current address.

Read operations are illustrated below.

RTC /Companion Write Operation

All RTC and Companion writes operate in a similar

manner to memory writes. The distinction is that a

different device ID is used and only one byte address

is needed instead of two. Figure 16 illustrates a single

byte write to this device.

RTC/Companion Read Operation

As with writes, a read operation begins with the

Slave Address. To perform a register read, the bus

master supplies a Slave Address with the LSB set to

1. This indicates that a read operation is requested.

After receiving the complete Slave Address, the

FM31T37x will begin shifting data out from the

current register address on the next clock.

Auto-increment operates for the special function

registers as with the memory address. A current

address read for the registers look exactly like the

memory except that the device ID is different.

The FM31T37x contains two separate address

registers, one for the memory address and the other

for the register address. This allows the contents of

one address register to be modified without affecting

the current address of the other register. For example,

this would allow an interrupted read to the memory

while still providing fast access to an RTC register. A

subsequent memory read will then continue from the

memory address where it previously left off, without

requiring the load of a new memory address.

However, a write sequence always requires an

address to be supplied.

S ASlave Address 1 Data Byte 1 P

By Master

By FM31xxx

Start Address Stop

Acknowledge

No

Acknowledge

Data

Figure 14. Current Address Memory Read

S ASlave Address 1 Data Byte 1 P

By Master

By FM31xxx

Start Address Stop

Acknowledge

No

Acknowledge

Data

Data ByteA

Acknowledge

Figure 15. Sequential Memory Read

By FM31T37x

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 20 of 26

S ASlave Address 1 Data Byte 1 P

By Master

By FM31xxx

Start Address Stop

No

Acknowledge

Data

S ASlave Address 0 Address MSB A

Start Address

Acknowledge

Address LSB A

Figure 16. Selective (Random) Memory Read

Figure 17. Byte Register Write

NOTE: It is required that Register Address bits A7-A5 are cleared (zeroes).

Addressing F-RAM Array in the FM31T37x Family

The FM31T37x family includes 256Kb, 64Kb, 16Kb, and 4Kb memory densities. The following 2-byte address field

is shown for each density.

Table 4. Two-Byte Memory Address

Part #

1st Address Byte

2nd Address Byte

FM31T378

x

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

FM31T376

x

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

FM31T374

x

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

FM31T372

x

A8

A7

A6

A5

A4

A3

A2

A1

A0

S

A

Slave Address

0

Address

A

Data Byte

A

P

By Master

Start

Address & Data

Stop

Acknowledge

0

By FM31T37x

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 21 of 26

Electrical Specifications

Absolute Maximum Ratings

Symbol

Description

Ratings

VDD

Power Supply Voltage with respect to VSS

-1.0V to +7.0V

VIN

Voltage on any signal pin with respect to VSS

-1.0V to +7.0V and

VIN ≤ VDD+1.0V *

VBAK

Backup Supply Voltage

-1.0V to +4.5V

TSTG

Storage Temperature

-55C to + 125C

TLEAD

Lead Temperature (Soldering, 10 seconds)

260 C

VESD

Electrostatic Discharge Voltage

- Human Body Model (AEC-Q100-002 Rev. E)

- Charged Device Model (AEC-Q100-011 Rev. B)

- Machine Model (AEC-Q100-003 Rev. E)

2kV

1.25kV

100V

Package Moisture Sensitivity Level

MSL-1

* The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs which do not employ a diode to VDD.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only,

and the functional operation of the device at these or any other conditions above those listed in the operational section of this

specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified)

Symbol

Parameter

Min

Typ

Max

Units

Notes

VDD

Main Power Supply

2.7

5.5

V

7

IDD

VDD Supply Current

@ SCL = 100 kHz

@ SCL = 400 kHz

@ SCL = 1 MHz

500

900

1500

A

1

ISB

Standby Current

For VDD < 5.5V

For VDD < 3.6V

150

120

A

2

VBAK

RTC Backup Supply Voltage

@ TA = +25ºC to +85ºC

@ TA = -40ºC to +25ºC

1.55

1.9

3.75

V

9

IBAK

RTC Backup Supply Current

@ TA = +25ºC, VBAK = 3.0V

@ TA = +85ºC, VBAK = 3.0V

@ TA = +25ºC, VBAK = 2.0V

@ TA = +85ºC, VBAK = 2.0V

1.4

2.1

1.15

1.75

A

4

IBAKTC

Trickle Charge Current with VBAK=0V

Fast Charge Off (FC = 0)

Fast Charge On (FC = 1)

50

200

120

2500

A

10

VTP0

VDD Trip Point Voltage, VTP(1:0) = 00b

2.55

2.6

2.70

V

5

VTP1

VDD Trip Point Voltage, VTP(1:0) = 01b

2.80

2.9

3.00

V

5

VTP2

VDD Trip Point Voltage, VTP(1:0) = 10b

3.80

3.9

4.00

V

5

VTP3

VDD Trip Point Voltage, VTP(1:0) = 11b

4.25

4.4

4.50

V

5

VRST

VDD for valid /RST @ IOL = 80 A at VOL

VBAK > VBAK min

VBAK < VBAK min

0

1.6

V

6

ILI

Input Leakage Current

1

A

3

ILO

Output Leakage Current

1

A

3

VIL

Input Low Voltage

All inputs except those listed below

CNT1-2 battery backed (VDD < 2.4V)

CNT1-2 (VDD > 2.4V)

-0.3

0.3 VDD

0.5

0.8

V

8

continued

»

FM31T372/374/376/378-G

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Apr. 2011 Page 22 of 26

DC Operating Conditions, continued (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified)

Symbol

Parameter

Min

Typ

Max

Units

Notes

VIH

Input High Voltage

All inputs except those listed below

PFI (comparator input)

CNT1-2 battery backed (VDD < 2.4V)

CNT1-2 VDD > 2.4V

0.7 VDD

-

VBAK – 0.5

0.7 VDD

VDD + 0.3

3.75

VBAK + 0.3

VDD + 0.3

V

VOL

Output Low Voltage (IOL = 3 mA),

FOUT, /INT, /RST

-

0.4

V

VOH

Output High Voltage (IOH = -2 mA)

2.4

-

V

RRST

Pull-up Resistance for /RST Inactive

50

400

K

RIN

Input Resistance (pulldown)

A1-A0 for VIN = VIL max

A1-A0 for VIN = VIH min

20

1

K

M

VPFI

Power Fail Input Reference Voltage

1.175

1.20

1.225

V

VHYS

Power Fail Input (PFI) Hysteresis (Rising)

-

100

mV

Notes

1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.

2. All inputs at VSS or VDD, static. Stop command issued.

3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, PFI, or /RST pins.

4. VBAK = 3.0V, VDD < 2.4V, oscillator running, CNT1-2 at Vss or VBAK.

5. /RST is asserted low when VDD < VTP.

6. The minimum VDD to guarantee the level of /RST remains a valid VOL level.

7. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified.

8. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM31T37x.

9. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications.

10. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max.

AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V, CL = 100 pF unless otherwise specified)

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

Notes

fSCL

SCL Clock Frequency

0

100

0

400

0

1000

kHz

tLOW

Clock Low Period

4.7

1.3

0.6

s

tHIGH

Clock High Period

4.0

0.6

0.4

s

tAA

SCL Low to SDA Data Out Valid

3

0.9

0.55

s

tBUF

Bus Free Before New Transmission

4.7

1.3

0.5

s

tHD:STA

Start Condition Hold Time

4.0

0.6

0.25

s

tSU:STA

Start Condition Setup for Repeated

Start

4.7

0.6

0.25

s

tHD:DAT

Data In Hold Time

0

ns

tSU:DAT

Data In Setup Time

250

100

ns

tR

Input Rise Time

1000

300

ns

1

tF

Input Fall Time

300

100

ns

1

tSU:STO

Stop Condition Setup Time

4.0

0.6

0.25

s

tDH

Data Output Hold (from SCL @ VIL)

0

ns

tSP

Noise Suppression Time Constant

on SCL, SDA

50

ns

All SCL specifications as well as start and stop conditions apply to both read and write operations.

RTC Frequency Characteristics

Symbol

Parameter

Min

Typ

Max

Units

FOUT

FOUT Clock Frequency

-

32.768

-

kHz

Δf/f

Frequency Stability

vs. Temperature

0 C to +45 C

±3

ppm

-40 C to +85 C

±5

ppm

FM31T372/374/376/378-G

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Apr. 2011 Page 23 of 26

Data Retention (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V)

Symbol

Parameter

Min

Units

Notes

TDR

Data Retention

10

Years

Supervisor Timing (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V)

Symbol

Parameter

Min

Max

Units

Notes

tRPU

/RST Active (low) after VDD>VTP

100

200

ms

tINTP

Pulse Width of /INT Active

100

200

ms

tRNR

VDD < VTP noise immunity

10

25

s

1

tVR

VDD Rise Time

50

-

s/V

1,2

tVF

VDD Fall Time

100

-

s/V

1,2

tWDP

Pulse Width of /RST for Watchdog Reset

100

200

ms

tWDOG

Timeout of Watchdog

tDOG

2*tDOG

ms

3

fCNT

Frequency of Event Counters

0

10

MHz

Notes

1 This parameter is characterized but not tested.

2 Slope measured at any point on VDD waveform.

3 tDOG is the programmed time in register 0Ah, VDD > VTP and tRPU satisfied.

/RST Timing

/INT Pulse Width

CNT1,

CNT2

tINTP

INT

VDD

VTP

VRST

RST

t

RPU

t

RNR

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 24 of 26

AC Test Conditions Equivalent AC Load Circuit

Input Pulse Levels 0.1 VDD to 0.9 VDD

Input rise and fall times 10 ns

Input and output timing levels 0.5 VDD

Diagram Notes

All start and stop timing parameters apply to both read and write

cycles. Clock specifications are identical for read and write cycles.

Write timing parameters apply to slave address, word address, and

write data bits. Functional relationships are illustrated in the relevant

data sheet sections. These diagrams illustrate the timing parameters

only.

Read Bus Timing

tSU:STA

Start

tR`tF

Stop Start

tBUF

tHIGH

1/fSCL

tLOW tSP tSP

Acknowledge

tHD:DAT

tSU:DAT

tAA tDH

SCL

SDA

Write Bus Timing

tSU:STO

Start Stop Start Acknowledge

tAA

tHD:DAT

tHD:STA tSU:DAT

SCL

SDA

5.5V

Output

1700



100 pF

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 25 of 26

Mechanical Drawing

14-pin SOIC (JEDEC Standard)

Pin 1

3.90 ±0.13

6.00 ±0.20

8.64 ±0.10

0.10

0.25

1.35

1.75

0.33

0.51

1.27 0.10 mm

0.25

0.50

45

0.40

1.27

0.19

0.25

0 - 8

Recommended PCB Footprint

7.70

0.65

1.27

2.00

3.70

Refer to JEDEC MS-012 for complete dimensions and notes.

All dimensions in millimeters.

SOIC Package Marking Scheme

Legend:

XXXXXX= part number, P= package type (-G)

LLLLLLL= lot code

RIC=Ramtron Int‟l Corp, YY=year, WW=work week

Example: FM31T378, “Green” SOIC package, Year 2010, Work Week 20

FM31T378-G

A00003G

RIC 1020

XXXXXXX-P

LLLLLLL

RIC YYWW

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011 Page 26 of 26

Revision History

Revision

Date

Summary

1.0

6/14/2010

Preliminary status.

1.1

4/18/2011

Documentation updates and clarifications. Changed IBAK limits.