FEBRUARY 2009
DSC-5281/09
1
©2006 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
Features
◆◆
◆◆
◆128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates the
need to control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
◆◆
◆◆
◆Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
A
0
-A
17
A d dre s s Inp uts Inp ut S yn chro no us
CE
1
, CE
2
, CE
2
Chip Enab le s Input S ync hro nous
OE Output Enable Input Asy nchro no us
R/WRead /Write Sig nal Input Sy nchro no us
CEN Clock Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
Indiv id ual By te Write Se le cts Input S ync hro nous
CLK Clock Input N/A
ADV/LD Advance b urst address / Load new address Input Synchronous
LBO Linear / Inte rle ave d Burs t Ord er Input Static
TMS Te s t Mo d e S e le c t Inp ut S y nc hro no us
TDI Te st Data Input Input S ync hro nous
TCK Test Clock Input N/A
TDO Te s t Data Outp ut Outp ut S ync hro no us
TRST JTAG Reset (Optional) Input Asynchronous
ZZ Sleep Mode Input Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/ O S yn chro no us
V
DD
, V
DDQ
Co re P o we r, I/ O P o we r Sup p l y S tatic
V
SS
Ground Supply Static
5281 tbl 01
IDT71V3556S/XS
IDT71V3558S/XS
IDT71V3556SA/XSA
IDT71V3558SA/XSA
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
6.42
2
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definition(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
17
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD lo w, CEN lo w, and true chip e nable s.
ADV/LD Ad vanc e / Load I N/A
ADV/LD is a synchro no us inp ut that is us ed to lo ad the internal re g isters with ne w ad dre s s and co ntrol whe n it
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD i s s am p led h ig h the n th e in te rna l b u rs t c o un te r
is ad vanc ed for any burst that was in p rog ress . The e xte rna l ad d re ss es are ig nore d when ADV/LD is sampled
high.
R/WRe ad / Wri te I N/ A R/W sig nal is a synchro nous inp ut that id entifie s whe ther the c urre nt load cy cle initiated is a Re ad or Write
access to the memory array. The data bus activity fo r the current cycle takes place two clock cycles late r.
CEN Clock Enable I LOW Sync hronous Clock Enable Input. When CEN is samp le d hig h, al l o the r s ynchrono us inp uts , includ ing c lo ck are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
BW
1
-BW
4
Ind iv id ual Byte
Write Enables ILOW
Sync hro nous b yte write e nabl es. Eac h 9-b it by te has its o wn ac tive lo w b yte write e nab le . On lo ad write cycle s
(Whe n R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW
4
) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appro priate byte(s) of data are written into the de vice two cycles later. BW
1
-BW
4
can all be
tied low if always doing write to the entire 36-bit word.
CE
1
, CE
2
Chip Enab le s I LOW Synchronous activ e lo w c hip enable. CE
1
and CE
2
are used with CE
2
to e nable the IDT71V 3556/58. (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZB T
TM
has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiate d.
CE
2
Chip Enable I HIGH Sy nc hro no us activ e hig h c hip enab le . CE
2
is used with CE
1
and CE
2
to enable the chip. CE
2
has inv e rte d
polarity but otherwise identical to CE
1
and CE
2
.
CLK Clock I N/A This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Inp ut/ Outp ut I/O N/ A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LBO Li near Burs t Orde r I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
OE Output Enab le I LOW Asy nchro nous o utp ut e nab le . OE mus t b e lo w to re ad d ata fro m the 71V3556/58. When OE is high the I/O pins
are in a hig h-imp edance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Te s t Data Inp ut I N/ A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured o n rising edge of TCK,
while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
TDO Te s t Data Outp ut O N/ A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
TRST JTAG Reset
(Optional) ILOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset
o cc urs auto matic ally at po we r up and als o re se ts us ing TMS and TCK per IEEE 1149.1. If no t use d TRST can
b e l eft flo ating . This p in has an internal p ul lup . Onl y av ailab le in BGA p ack age .
ZZ Sleep Mode I HIGH Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to
its lowest power consum ption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
V
DD
Po we r Sup p ly N/ A N/A 3. 3V c o re p owe r s up ply.
V
DDQ
Power Supply N/A N/A 3.3V I/O Supply.
V
SS
Ground N/A N/A Ground.
5281 tbl 02
The IDT71V3556/58 has an on-chip burst counter. In the burst
mode, the IDT71V3556/58 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V3556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Description continued
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
InputRegister
5281 drw 01a
Clock
Data I/O [0:31],
I/O P[1:4]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 128Kx36 BIT
MEMORY ARRAY
,
JTAG
(SA Version)
TMS
TDI
TCK TDO
TRST
(optional)
6.42
4
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:17]
Control Logic
Address
Control
DI DO
InputRegister
5281 drw 01b
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 256x18 BIT
MEMORY ARRAY
,
JTAG
(SA Version)
TMS
TDI
TCK TDO
TRST
(optional)
Symbol Parameter Min. Typ. Max. Unit
V
DD
Co re Sup p ly Vo ltag e 3.135 3. 3 3. 465 V
V
DDQ
I/O S up pl y Vo ltage 3.135 3. 3 3. 465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 2.0
____
V
DDQ
+0.3
(2)
V
V
IL
Inp u t Lo w Vo l tag e -0. 3
(1)
____
0.8 V
5281 tbl 04
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage
Pin Configuration - 128K x 36
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
Top View
100 TQFP
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5281 drw 02
V
DD
(1)
I/O
15
I/O
P3
V
DD
(1)
I/O
P4
A
15
A
16
I/O
P1
V
DD
(1)
I/O
P2
V
SS
/ZZ
(3)
,
NC
NC
NC
NC
Grade Temperature
(1)
V
SS
V
DD
V
DDQ
Comme rcial 0°C to +70°C 0V 3.3V±5% 3.3V±5%
Industrial -40°C to +85°C 0V 3.3V±5% 3. 3V±5%
5 281 t bl 05
NOTES:
1. TA is the "instant on" case temperature.
6.42
6
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings (1)
Pin Configuration - 256K x 18
100 Pin TQFP Capacitance(1)
(TA = +25° C, f = 1.0MHz)
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Commercial &
Industrial Values Unit
V
TERM
(2)
Terminal Voltage with
Re s p e c t to GND -0.5 to +4.6 V
V
TERM
(3,6)
Terminal Voltage with
Re s p e c t to GND -0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Re s p e c t to GND -0. 5 to V
DD
+0.5 V
V
TERM
(5,6)
Terminal Voltage with
Re s p e c t to GND -0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature -0 to +70 oC
Industrial
Operating Temperature -40 to +85 oC
T
BIAS
Temperature
Under Bias -55 to +125 oC
T
STG
Storage
Temperature -55 to +125 oC
P
T
Po we r Dis s ip atio n 2. 0 W
I
OUT
DC Outp ut Curre nt 50 mA
5281 t bl 06
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5281 drw 02a
V
DD
(1)
NC
NC
V
DD
(1)
NC
A
16
A
17
NC
V
DD
(1)
A
10
V
SS
/ZZ
(3)
,
NC
NC
NC
NC
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 5 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
5281 tbl 07
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
CIN Inp ut Cap ac itanc e V IN = 3dV 7 pF
CI/O I/ O Cap ac i tanc e V OUT = 3dV 7 pF
5281 tbl 07a
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV TBD pF
C
I/O
I/O Cap ac itanc e V
OUT
= 3dV TBD pF
5281 tb l 07b
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
7
1234567
AV
DDQ
A
6
A
4
A
8
A
16
V
DDQ
BNC CE
2
A
3
ADV/LD A
9
CE
2
NC
CA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
R/WV
SS
I/O
9
I/O
8
JV
DDQ
V
DD
V
DD
V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
CEN V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
RNC A
5
LBO V
DD
A
13
TNC NC A
10
A
11
A
14
NC NC/ZZ(5)
UV
DDQ
V
DDQ
5281 drw 13A
V
DD(1)
NC
NC(2)
CE
1
NC(2)
V
DD(1)
V
DD(1)
,
NC/TMS
(3)
NC/TDI
(3)
NC/TCK
(3)
NC/TDO
(3)
NC/TRST
(3,4)
NC
1234567
AVDDQ A6A4NC(2) A8A16 VDDQ
BNC CE2 A3ADV/LD A9CE2NC
CA7A2VDD A13 A17 NC
DI/O8NC VSS NC VSS I/OP1 NC
ENC I/O9VSS VSS NC I/O7
FVDDQ NC VSS OE VSS I/O6VDDQ
GNC I/O10 BW2NC I/O5
HI/O11 NC VSS R/WVSS I/O4NC
JVDDQ VDD VDD VDD VDDQ
KNC I/O12 VSS CLK VSS NC I/O3
LI/O13 NC NC BW1I/O2NC
MVDDQ I/O14 VSS CEN VSS NC VDDQ
NI/O15 NC VSS A1VSS I/O1NC
PNC I/OP2 VSS A0VSS NC I/O0
RNC A5LBO VDD A12
TNC A10 A15 NC A14 A11 NC/ZZ(5)
UVDDQ VDDQ
5281drw 13B
NC
DD(1)V
VSS
VSS
CE1
NC(2)
VDD(1) VDD(1)
,
NC/TMS(3) NC/TRST(3,4)
NC/TDO(3)
NC/TCK(3)
NC/TDI(3)
NC
Pin Configuration - 128K x 36, 119 BGA
Pin Configuration - 256K x 18, 119 BGA
Top View
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
8
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
Pin Configuration - 256K x 18, 165 fBGA
1234567891011
ANC
(2)
A
7
CE1 BW
3
BW
2
CE
2
CEN ADV/LD NC
(2)
A
8
NC
BNC A
6
CE
2
BW
4
BW
1
CLK R/WOE NC
(2)
A
9
NC
(2)
CI/O
P3
NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P2
DI/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
EI/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
FI/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
GI/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
HV
DD
(1)
V
DD
(1)
NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC NC/ZZ
(5)
JI/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
KI/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
LI/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
MI/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
NI/O
P4
NC V
DDQ
V
SS NC/TRST
(3,4)
NC V
DD
(1)
V
SS
V
DDQ
NC I/O
P1
PNCNC
(2)
A
5
A
2
NC/TDI
(3)
A
1
NC/TDO
(3)
A
10
A
13
A
14
NC
RLBO NC
(2)
A
4
A
3
NC/TMS
(3)
A
0
NC/TCK
(3)
A
11
A
12
A
15
A
16
5281 tb l 25
1234567891011
ANC
(2)
A
7
CE
1
BW
2
NC CE
2
CEN ADV/LD NC
(2)
A
8
A
10
BNC A
6
CE
2
NC BW
1
CLK R/WOE NC
(2)
A
9
NC
(2)
CNC NCV
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P1
DNC I/O
8
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
7
ENC I/O
9
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
6
FNCI/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
5
GNC I/O
11
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
4
HV
DD
(1)
V
DD
(1)
NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC NC/ZZ
(5)
JI/O
12
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
KI/O
13
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
NC
LI/O
14
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
NC
MI/O
15
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
NC
NI/O
P2
NC V
DDQ
V
SS NC/TRST
(3,4)
NC V
DD
(1)
V
SS
V
DDQ
NC NC
PNC NC
(2)
A
5
A
2
NC/TDI
(3)
A
1
NC/TDO
(3)
A
11
A
14
A
15
NC
RLBO NC
(2)
A
4
A
3
NC/TMS
(3)
A
0
NC/TCK
(3)
A
12
A
13
A
16
A
17
5281 tb l 25a
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
9
Synchronous Truth Table (1)
Partial T ruth T able for Writes (1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
CEN R/WChip
(5)
Enable ADV/LD BWxADDRESS
USED PRE VI OUS CYCLE CURRENT CYCLE I /O
(2 cycles l ater)
L L Sele ct L Valid External X LOAD WRITE D
(7)
L H Select L X External X LOAD READ Q
(7)
L X X H Valid Internal LOA D WRITE /
BURST WRITE BURST WRITE
(Advance burst counter)
(2)
D
(7)
L X X H X Internal LOA D READ /
BURS T RE AD BURST READ
(Advance burst counter)
(2)
Q
(7)
L X Deselect L X X X DESELECT or STOP
(3)
HiZ
L X X H X X DE SE LE CT / NOOP NOOP HiZ
H X X X X X X SUSPEND
(4)
Pre vious Value
5 281 t bl 08
OPERATION R/WBW1BW2BW3
(3)
BW4
(3)
READ HXXXX
WRITE ALL BYTES LLLLL
WRITE BYTE 1 (I/O[0:7], I/OP1)
(2)
LLHHH
WRITE BYTE 2 (I/O[8:15], I/OP2)
(2)
LHLHH
WRITE BYTE 3 (I/O[16:23], I/OP3)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/OP4)
(2,3)
LHHHL
NO WRITE L HHHH
5 281 t bl 09
6.42
10
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Functional Timing Diagram (1)
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 000 110 11
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11000110
5281 tbl 11
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 000 110 11
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11100100
5 281 t bl 10
n+29
A29
C29
D/Q27
ADDRESS
(2)
(A0 - A16)
CONTROL
(2)
(R/W,ADV/LD,BWx)
DATA
(2)
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
5281 drw 03 ,
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
11
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation (1)
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
nA
0HL LLXXXLoad read
n+1 X X H X L X X X B urst re ad
n+2 A1HL LLXLQ0Lo ad re ad
n+3 X X L H L X L Q0+1 Deselect or STOP
n+4 X X H XLXLQ
1NOOP
n+5 A2HL LLXXZLoad read
n+6 X X H X L X X Z B urst re ad
n+7 X X L H L X L Q2Deselect or STOP
n+8 A3L L LLLLQ2+1 Load write
n+9 X X H X L L X Z Burst write
n+10 A4L L LLLXD3Load write
n+11 X X L H L X X D3+1 Deselect or STOP
n+12 X X H X L X X D4NOOP
n+13 A5L L L L L X Z Lo ad write
n+14 A6HL LLXXZLoad read
n+15 A7L L LLLXD5Load write
n+16 X X H XLLLQ
6Burst write
n+17 A8HL LLXXD7Load read
n+18 X X H X L X X D7+1 B urst re ad
n+19 A9L L LLLLQ8Load write
5 281 t bl 12
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0H L L L X X X Address and Control meet setup
n+1 X X X X L X X X Clock Setup Valid
n+2 X X X XXXLQ
0Contents of Address A0 Re ad Out
5 281 t bl 13
6.42
12
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Write Operation (1)
Burst Read Operation (1)
Write Operation (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid , Ad vance Counter
n+2 X X H XLXLQ
0
Address A
0
Re ad Out, Inc . Co unt
n+3 X X H XLXLQ
0+1
Address A
0+1
Re ad Out, Inc . Co unt
n+4 X X H XLXLQ
0+2
Address A
0+2
Re ad Out, Inc . Co unt
n+5 A
1
HL LLXLQ
0+3
Address A
0+3
Read Out, Load A
1
n+6 X X H XLXLQ
0
Address A
0
Re ad Out, Inc . Co unt
n+7 X X H XLXLQ
1
Address A
1
Re ad Out, Inc . Co unt
n+8 A
2
HL LLXLQ
1+1
Address A
1+1
Read Out, Lo ad A
2
5281 tbl 14
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0L L L L L X X Address and Control meet setup
n+1 X X X X L X X X Clock Setup Valid
n+2 X X X X L X X D0Write to Address A0
5 281 t bl 15
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clock Setup Valid, Inc. Co unt
n+2 X X H X L L X D
0
Address A
0
Write , Inc . Co unt
n+3 X X H X L L X D
0+1
Address A
0+1
Write, Inc . Co unt
n+4 X X H X L L X D
0+2
Address A
0+2
Write , Inc . Co unt
n+5 A1 L L LLLXD
0+3
Address A
0+3
Write, Lo ad A
1
n+6 X X H X L L X D
0
Address A
0
Write, Inc . Co unt
n+7 X X H X L L X D
1
Address A
1
Write , Inc . Co unt
n+8 A
2
L L LLLXD
1+1
Address A
1+1
Write , Lo ad A
2
5281 tbl 16
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used (1)
Write Operation with Clock Enable Used (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clo ck n+1 Igno red
n+2 A
1
HL LLXXXClock Valid
n+3 X X X X H X L Q
0
Cl o ck Igno re d . Data Q
0
is on the bus.
n+4 X X X X H X L Q
0
Cl o ck Igno re d . Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
0
Address A
0
Read out (bus trans. )
n+6 A
3
HL LLXLQ
1
Address A
1
Read out (b us trans. )
n+7 A
4
HL LLXLQ
2
Address A
2
Read out (bus trans. )
5 281 t bl 17
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Clo ck n+1 Ig nore d.
n+2 A
1
L L LLLXXClock Valid.
n+3 X X X X H X X X Clo ck Igno red .
n+4 X X X X H X X X Clo ck Igno red .
n+5 A
2
L L LLLXD
0
Write Data D
0
n+6 A
3
L L LLLXD
1
Write Data D
1
n+7 A
4
L L LLLXD
2
Write Data D
2
5 281 t bl 18
6.42
14
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with CHIP Enable Used (1)
Write Operation with Chip Enable Used (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O(3) Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A0H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A1HL LLXLQ0Address A0 Re ad out. Lo ad A 1.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q1Address A1 Read out. Deselected.
n+7 A2H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q2Address A2 Read o ut. Dese le c te d .
5281 tbl 19
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O(3) Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
L L LLLXD
0
Address D
0
Write in. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
1
Address D
1
Write in. Deselected.
n+7 A
2
L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D
2
Address D
2
Write in. Deselected.
5281 tbl 20
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
(VDDQ = 3.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
Figure 1. AC Test Load
AC Test Loads
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5281 drw 04 ,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5281 drw 05
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD ___
5µA
|I
LI
|L BO, J TAG and ZZ Inp ut Le akag e Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD ___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Lo w Vo ltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Vo ltag e I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5281 tbl 21
Symbol Parameter Test Conditions
200MHz 166MHz 133MHz 100MHz
UnitCom'l Only Com'l Ind Com'l Ind Com'l Ind
I
DD
Op erating Po we r
Supply Current Device Selected, Outputs Open,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
400 350 360 300 310 250 255 mA
I
SB1
CMOS Standby
Power Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
, f
= 0
(2,3)
40 40 45 40 45 40 45 mA
I
SB2
Clo ck Runni ng Po we r
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
, f
= f
MAX
(2.3)
130 120 130 110 120 100 110 mA
I
SB3
Id l e P o we r
Supply Current Device Selected, Outputs Open,
CEN > V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
40 40 45 40 45 40 45 mA
5281 tbl 22
Input Pulse Levels
Inp ut Ris e /Fall Tim e s
Inp ut Tim ing Re fe re nc e Le v e ls
Output Timing Re fe renc e Leve ls
AC Test Lo ad
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5 281 t bl 23
6.42
16
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only.
200MHz
(6)
166MHz 133MHz 100MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time 5
____
6
____
7.5
____
10
____
ns
t
F
(1)
Clo ck Fre que nce
____
200
____
166
____
133
____
100 MHz
t
CH
(2)
Clock High Pulse Width 1.8
____
1.8
____
2.2
____
3.2
____
ns
t
CL
(2)
Clock Low Pulse Width 1.8
____
1.8
____
2.2
____
3.2
____
ns
Output Parameters
t
CD
C lo c k Hig h to Valid Data
____
3.2
____
3.5
____
4.2
____
5ns
t
CDC
Clo ck Hig h to Data Chang e 1
____
1
____
1
____
1
____
ns
t
CLZ
(3,4,5)
Clo ck Hi g h to Outp ut A ctive 1
____
1
____
1
____
1
____
ns
t
CHZ
(3,4,5)
Clock High to Data High-Z 13131313.3ns
t
OE
Output Enable Access Time
____
3.2
____
3.5
____
4.2
____
5ns
t
OLZ
(3,4)
Outp ut E na b l e Lo w to Data A ctiv e 0
____
0
____
0
____
0
____
ns
t
OHZ
(3,4)
Output Enable High to Data High-Z
____
3.5
____
3.5
____
4.2
____
5ns
Set Up Times
t
SE
Clo ck Enable Se tup Time 1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SA
Address Setup Time 1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SD
Data In Se tup Ti me 1. 5
____
1.5
____
1.7
____
2.0
____
ns
t
SW
Re ad /Write (R/ W) Se tup Time 1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SADV
Ad vanc e /Lo ad (ADV/ LD) Se tup Time 1. 5
____
1.5
____
1.7
____
2.0
____
ns
t
SC
Chip Enable/Select Setup Time 1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SB
Byte Write Enable (BWx) Setup Time 1.5
____
1.5
____
1.7
____
2.0
____
ns
Hold Times
t
HE
Clo ck Enable Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Ho l d Tim e 0. 5
____
0.5
____
0.5
____
0.5
____
ns
t
HW
Re ad /Write (R/ W) Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HADV
Ad vanc e /Lo ad (ADV/ LD) Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enab le/Se lec t Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write Enable (BWx) Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
5281 tbl 24
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle (1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
ADV/LD
(CENhigh,eliminates
currentL-Hclockedge)
t
CD
t
HADV
Pipeline
Read
(BurstWrapsaround
toinitialstate)
t
CDC
t
CLZ
t
CHZ
t
CD
t
CDC
R/W
CLK
CEN
ADDRESS
OE
DATA
OUT
t
HE
t
SE
A1A2
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
BurstPipelineRead
Pipeline
Read
BW
1
-BW
4
5281drw06
CE
1
,
CE
2
(2)
Q(A
2+3
)Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)
Q(A
2+1
)
Q(A
2
)
Q(A
1
)
,
,
6.42
18
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Wa veform of Write Cyc les (1,2,3,4,5)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
OE
DATA
IN
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
BurstPipelineWrite
Pipeline
Write
Pipeline
Write
t
HB
t
SB
(BurstWrapsaround
toinitialstate)
t
HD
t
SD
(CENhigh,eliminates
currentL-Hclockedge)
(2)
D(
A2+2
)D(
A2+3
)
D(A
1
)D(A
2
)D(A
2
)
5281drw07
BW1-BW4
CE1,CE2
D(A
2+1
)
,
,
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
19
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles (1,2,3)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)Q(A
6
)Q(A
7
)
t
CD
Read
t
CHZ
5281drw08
Write
t
CLZ
D(A
2
)D(A
4
)
t
CDC
D(A
5
)
Write
t
CH
t
CL
t
CYC
t
HW
t
SW
t
HA
t
SA
A
4
A
3
t
HC
t
SC
t
SD
t
HD
t
HADV
t
SADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
t
HB
t
SB
OE
Read
Read
,,
,
6.42
20
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
Timing Waveform of CEN Operation (1,2,3,4)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
BW1-BW4
OE
DATA
OUT
Q(A
3
)
t
CD
t
CLZ
t
CHZ
t
CH
t
CL
t
CYC
t
HC
t
SC
D(A
2
)
t
SD
t
HD
t
CDC
A
4
A
5
t
HADV
tSADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
Q(A
1
)
5281drw09
Q(A
1
)
B(A
2
)
CE
1
,CE
2
(2)
,
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation (1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATA
OUT
Q(A
1
)
t
CD
t
CLZ
t
CHZ
t
CDC
t
CH
t
CL
t
CYC
t
HC
t
SC
t
SD
t
HD
A
5
A
3
t
SB
DATA
IN
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
CEN
t
HADV
t
SADV
5281drw10
Q(A
2
)Q(A
4
)
D(A
3
)
BW1-BW4
CE1,CE2
(2)
,
6.42
22
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(3)
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M5281 drw 01
x
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
J TAG Cl o ck HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
5
(1)
ns
t
JF
JTAG Clock Fall Time
____
5
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
JTAG Data Output
____
20 ns
t
JDC
J TAG Data O utp ut Hol d 0
____
ns
t
JS
JTAG Setup 25
____
ns
t
JH
JTAG Hold 25
____
ns
I5 2 81 tb l 01
Regi ster Name Bi t S ize
Ins truc tio n (IR) 4
Bypass (BYR) 1
J TA G Id e nti fic ati o n (J IDR) 32
Boundary Scan (BSR) Note (1)
I5281 tbl 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JT AG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instructi on Fiel d Value Descripti on
Revision Number (31:28) 0x2 Reserved for version number.
IDT Devic e ID (27:12) 0x 208, 0x20A Defines IDT p art numbe r 71V3556SA and 71V3558SA, res pective ly.
IDT J EDEC ID (11: 1) 0x33 Allo ws u niq ue id e ntifi catio n o f d evice ve nd or as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.
I5281 tbl 02
JTAG Identification Register Definitions (SA Version only)
Instruction Description OPCODE
EXTEST Forces contents of the bound ary scan cells onto the device outputs
(1)
.
Places the boundary scan registe r (BSR) between TDI and TDO. 0000
SAMPLE/PRELOAD
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
and outputs
(1)
to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the bo undary scan cells via the TDI.
0001
DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO. 0010
HIGHZ Places the bypass register (BYR) be tween TDI and TDO. Forces all
device o utput drivers to a High-Z state. 0011
RESERVED
Se ve ral c ombinatio ns are re serve d . Do n ot use co d es o the r than tho se
ide ntifie d fo r EXTE ST, SAMPLE/PRELOA D, DEV ICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructio ns.
0100
RESERVED 0101
RESERVED 0110
RESERVED 0111
CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO. 1000
RESERVED
Same as above.
1001
RESERVED 1010
RESERVED 1011
RESERVED 1100
VALIDATE Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated b y the IEEE std. 1149. 1 sp e cific atio n. 1101
RESERVED Same as above. 1110
BYPASS The BYPASS instruction is used to truncate the boundary scan register
as a s ing le bit in le ng th. 1111
I5281 tbl 04
Available JTAG Instructions
6.42
24
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
25
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
26
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
27
Timing Wa veform of OE Operation (1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA
OUT
t
OHZ
t
OLZ
t
OE
Valid
5281 drw 11
,
6.42
28
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Datasheet Document History
6/30/99 Updated to new format
8/23/99 Added Smart ZBT functionality
Pg. 4, 5 Added Note 4 and changed Pins 38, 42, and 43 to DNU
Pg. 6 Changed U2–U6 to DNU
Pg. 14 Added Smart ZBT AC Electrical Characteristics
Pg. 15 Improved tCD and tOE(MAX) at 166MHz
Revised tCHZ(MIN) for f ≤ 133 MHz
Revised tOHZ (MAX) for f ≤ 133 MHz
Improved tCH, tCL for f ≤ 166 MHz
Improved setup times for 100–200 MHz
Pg. 22 Added BGA package diagrams
Pg. 24 Added Datasheet Document History
10/4/99 Pg. 14 Revised AC Electrical Characteristics table
Pg. 15 Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz
12/31/99 Removed Smart functionality
Added Industrial Temperature range offerings at the 100 to 166MHz speed grades.
04/30/00 Pg. 5, 6 Insert clarification note to Recommended Operating Temperature and Absolute Max
Ratings tables
Pg. 6 Add BGA capacitance table
Pg. 5,6, 7 Add note to TQFP and BGA Pin Configurations; corrected typo in pinout
Pg. 21 Add 100pinTQFP package Diagram Outline
05/26/00 Add new package offering, 13 x 15mm 165 fBGA
Pg. 23 Correct 119BGA Package Diagram Outline
07/26/00 Pg. 5-8 Add ZZ sleep mode reference note to BG119, PK100 and BQ165 pinouts
Pg. 8 Update BQ165 pinout
Pg. 23 Update BG119 package diagram outline dimensions
10/25/00 Remove Preliminary status
Pg. 8 Add note to pin N5 on BQ165, reserved for JTAG TRST
1/24/02 Pg. 1-8, 15,22,23,27 Added JTAG "SA" version functionality
9/30 /04 Pg. 7 Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Pg. 27 Adding "Restricted hazardous substance device" to ordering information.
10/18/06 Pg. 1, 26 Added X generation die step to data sheet.
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ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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