RT8073GSP - Richtek Technology

RT8073

DS8073-02 August 2014 www.richtek.com

Ordering Information

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

General Description

The RT8073 is a high efficiency PWM step-down converter

and capable of delivering 6A output current over a wide

input voltage ra nge from 2.9V to 5.5V.

The RT8073 provides a ccurate regulation for a variety of

loads with an ±1% reference voltage at room temperature.

For reducing inductor size, it provides up to 2MHz

switching frequency . The efficiency is maximized through

the integrated 50mΩ for high side, 35mΩ for low side

MOSFETs a nd 250μA typical supply current.

The RT8073 features over current protection, frequency

fold back function in shorted circuit, hiccup mode under

voltage protection and over temperature protection.

The RT8073 is available in SOP-8 (Exposed Pad) and

W DFN-12L 3x3 packages.

6A, 2MHz, High Efficiency Synchronous Step-Down Converter

Features



Integrated 50mΩΩ

ΩΩ

Ω and 35mΩΩ

ΩΩ

Ω MOSFETs



6A Output Current



High Efficiency Up to 95%



2.9V to 5.5V Input Range



Adjustable PWM Frequency : 300kHz to 2MHz



0.8V ±±

±±

±1% Reference Voltage



Adjustable External Soft-Start



Power Good Indicator (WDFN-12L 3x3 only)



Over Current Protection



Under Voltage Protection



Over Temperature Protection



SOP-8 (Exposed Pad) a nd 12-Lea d WDFN Pa ckage s

RoHS Compliant and Halogen Free

Applications

Low Voltage, High Density Power System s

Distributed Power Systems

Point-of-Load Conversions

Simplified Application Circuit

VIN RT8073

BOOT

COMP VOUT

EN L

CBOOT

COUT RFB1

RFB2

CIN

VIN

GND

Marking Information

RT8073GSP RT8073GSP : Product Number

YMDNN : Date Code

RT8073GQW 5C= : Product Code

YMDNN : Date Code

RT8073

GSPYMDNN

5C=YM

DNN

RT8073

Package Type

SP : SOP-8 (Exposed Pad-Option 2)

QW : WDFN-12L 3x3 (W-Type)

(Exposed Pad-Option 1)

Lead Plating System

G : Green (Halogen Free and Pb Free)

RT8073

2DS8073-02 August 2014www.richtek.com

Functional Pin Description

Pin Configurations (TOP VIEW)

SOP-8 (Exposed Pad) WDFN-12L 3x3

COMP

GND

VIN

BOOT

PGND

COMP

PGOOD

VIN

VIN BOOT

PGND

Pin No.

SOP-8

(Exposed Pad) WDFN-12L 3x3 Pin Name Pin Function

1 1 COMP Compensation Node.

2 -- GND Analog Ground.

3 4 EN

Chip Enable. Externally pulled high to enable and pulled low to

disable this c hip, and it is internally pulled up to high when the

pin is floating.

4 5, 6 VIN Power Input.

5 7 BOOT Bootstrap Supply for High Side Gate Driver.

6 8, 9, 10 LX Switch Node.

7 11 RT Frequency Setting.

8 1 2 FB Fe edb ack Voltage Input .

9 13

(Ex posed Pad) PGND Power Ground. The exposed pad must be shouldered to a

large PCB and connected to PGND for maximum power

dissipation.

-- 2 PGOOD

Power Good Indicator with Open Drain Output. It is high

impedance when the output voltage is regulated. It is internally

pulled low when the chip is shutdown, thermal shutdown or

VIN is under U VLO threshold.

-- 3 SS Soft-Start Control.

RT8073

DS8073-02 August 2014 www.richtek.com

Function Block Diagram

For SOP-8 (Exposed Pad) Package

For WDFN-12L 3x3 Package

VIN

Oscillator

Current

Sense

Shutdown

Control UVLO

Driver

Control

Logic

PGND

PWM

Comparator

Error

Amplifier

Voltage

Reference

Soft-Start

BOOT

Slope

Compensation

EN Threshold

COMP

GND

Over Temperature

Protection

VIN

Internal

pull up

current

VIN

Oscillator

Current

Sense

Shutdown

Control UVLO

Driver

Control

Logic

PGND

PWM

Comparator

Error

Amplifier

Voltage

Reference

Soft-

Start

BOOT

Slope

Compensation

Over Temperature

Protection

EN Threshold

PGOOD

COMP

VIN

Internal

pull up

current

VIN

Power Good

Threshold

RT8073

4DS8073-02 August 2014www.richtek.com

Operation

The RT8073 is a current mode synchronous step-down

DC/DC converter with two integrated power MOSFETs. It

can deliver up to 6A output current from a 2.9V to 5.5V

input supply. The RT8073's current mode architecture

allows the transient response to be optimized over a wide

input voltage a nd load range. Cycle-by-cycle current limit

provides protection against shorted outputs a nd soft-start

eliminates input current surge during start-up.

Error Amplifier

The error amplifier adjusts COMP voltage by comparing

the feedback signal (VFB) from the output voltage with the

internal 0.8V reference. When the load current increa ses,

it causes a drop in the feedback voltage relative to the

reference, the COMP voltage then rises to allow higher

inductor current to match the load current.

Oscillator (OSC)

The frequency of the oscillator is adjustable by an external

resistor connected between the RT pin and GND. The

available switching frequency range is from 300kHz to

2MHz.

PGOOD Comparator

When the feedback voltage (VFB) rises above 94% or falls

below 106% of reference voltage, the PGOOD open drain

output will be high impedance. The PGOOD open drain

output will be internally pulled low when the feedback

voltage (VFB) falls below 90% or rises above 110% of

reference voltage.

Soft-Start (SS)

An internal current source charges a n external capa citor

to build the soft-start ra mp voltage (VSS). The VFB voltage

will track the VSS during soft-start interval. The chip will

use internal soft-start if the SS pin is floating. The nominal

internal soft-start time is 800μs.

Over Temperature Protection (OTP)

The RT8073 implements an internal over temperature

protection. When junction temperature is higher than

165°C, it will stop switching operation. Once the junction

temperature decreases below 145°C, the RT8073 will

automatically resume switching.

RT8073

DS8073-02 August 2014 www.richtek.com

Recommended Operating Conditions (Note 4)

Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- 2.9V to 5.5V

Junction T emperature Range-------------------------------------------------------------------------------------- −40°C to 125°C

Ambient T emperature Range-------------------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

Supply Input V oltage, VIN ----------------------------------------------------------------------------------------- −0.3V to 6.5V

BOOT to LX ----------------------------------------------------------------------------------------------------------- −0.3V to 6V

Other Pins------------------------------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)

 Power Dissipation, PD @ TA = 25°C

SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------- 2.041W

WDFN-12L 3x3------------------------------------------------------------------------------------------------------- 1.667W

Pa ckage Thermal Resista nce (Note 2)

SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 49°C/W

SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------- 15°C/W

WDFN-12L 3x3, θJA ------------------------------------------------------------------------------------------------- 60°C/W

WDFN-12L 3x3, θJC ------------------------------------------------------------------------------------------------- 7.5°C/W

Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------- 260°C

Junction T emperature----------------------------------------------------------------------------------------------- 150°C

Storage T emperature Range -------------------------------------------------------------------------------------- −65°C to 150°C

ESD Susceptibility (Note 3)

HBM (Human Body Model)---------------------------------------------------------------------------------------- 2kV

Parameter Symbol Test Conditions Min Typ Max Unit

Input Power Supply

Under Voltage Lockout Threshold VUVLO V

IN Rising -- 2.6 2.8 V

Quiescent Current IQ Active, VFB = 0.9 V, Not switchi ng -- 250 -- A

Shutdown Current ISHDN -- 2 5 A

Voltage Reference

Voltage Reference VREF 0.792 0.8 0.808 V

Enable Logic-High VIH 1.5 -- 5.5

EN Input Voltage Logic-Low VIL -- -- 0.4

Switching Frequency Setting 300 -- 2000

RT = 28.7k  -- 1400 --

Sw itching Frequency fOSC RT pin is floating - - 300 -- kHz

Minimum On-Time -- 80 -- ns

Minimum Off-Time -- 60 -- ns

(VIN = 5V, CIN = 10μF, TA = 25°C, unless otherwise specified)

Electrical Characteristics

RT8073

6DS8073-02 August 2014www.richtek.com

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Parameter Symbol Test Conditions Min Typ Max Unit

MOSFET

High Side MOSFET On-resi stance VIN = 5V, BOOT  LX = 5V -- 50 -- m

Low Side MOSFET On-res is tance VIN = 5V -- 35 -- m

Curren t Lim it

Current Lim it Threshold 7 9 -- A

Power Goo d V

FB Ris ing (Good) -- 94 --

FB Falling (F ault ) -- 9 0 --

FB Ris ing (Fault) -- 110 --

Power Good Range

(WDFN-12L 3x3 only)

FB Falling (Good) -- 106 --

% VREF

Over Temperature Protection

Thermal Shutdown Rising -- 165 -- C

Thermal Shutdown Hysteresis -- 20 -- C

RT8073

DS8073-02 August 2014 www.richtek.com

Typical Application Circuit

VOUT (V) RFB (k) RFB2 (k) RC (k) CC (nF) L (H) COUT

3.3 75 24 33 0.33 0.47 Cer. 20F + E-Cap 100F

2.5 51 24 24 0.47 0.47 Cer. 20F + E-Cap 100F

1.8 30 24 18 0.56 0.47 Cer. 20F + E-Cap 100F

1.5 21 24 15 0.68 0.33 Cer. 20F + E-Cap 100F

1.2 12 24 12 1 0.33 Cer. 20F + E-Cap 100F

1 6 24 10 1 0.33 Cer. 20F + E-Cap 100F

Table 1. Recommended Component Selection

RT8073

BOOT

COMP

VOUT

CBOOT

0.1µF

RFB1

RFB2

28.7k

CSS

10nF

CHF* FB

PGND

GND

COUT1

10µF COUT3

47µF to

100µF

COUT2

10µF

* : Option

VIN

PGOOD

RPG

100k

CIN2

CIN1

10µF

VIN

10µF

Chip Enable

RT8073

8DS8073-02 August 2014www.richtek.com

Output Voltage vs. Output Current

1.02

1.04

1.06

1.08

1.10

1.12

1.14

1.16

1.18

0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0

Output Current (A)

Output V oltage ( V )

VOUT = 1.1V

VIN = 5V

VIN = 4V

VIN = 3.3V

Efficiency vs. Load Current

100

0.001 0.01 0.1 1 10

Load Curren t (A)

Eff iciency (%)

VOUT = 1.1V

VIN = 3.3V

VIN = 4V

VIN = 5V

Output Voltage vs. Input Voltage

1.00

1.02

1.04

1.06

1.08

1.10

1.12

1.14

1.16

1.18

1.20

2.5 3 3.5 4 4.5 5 5.5

In put Voltage (V)

Output V oltage ( V )

VOUT = 1.1V

Output Voltage vs. Temperature

1.06

1.07

1.08

1.09

1.10

1.11

1.12

1.13

1.14

1.15

1.16

-50 -25 0 25 50 75 100 125

Temperature (°C)

Output Vol tage (V)

VIN = 5V, VOUT = 1.1V, IOUT = 1.5A

Typical Operating Characteristics

Frequency vs. Input Voltage

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

2.5 3 3.5 4 4.5 5 5.5

Input Voltage (V)

Fr equency (MH z) 1

VOUT = 1.1V, IOUT = 1.3A

Switching Frequency vs. Te m perature

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

-50 -25 0 25 50 75 100 125

Temper ature (°C)

Swit ching Fr equency (MH z) 1

VOUT = 1.1V, IOUT = 1.3A

RT8073

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VIN = 5V, VOUT = 3.3V, IOUT = 6A

Time (250ns/Div)

Output Ripple Voltage

VOUT

(20mV/Div)

VLX

(5V/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 0A to 3A

Time (100μs/Div)

Load Transient Response

VOUT

(100mV/Div)

IOUT

(2A/Div)

VIN = 5V, VOUT = 1.1V, I OUT = 0A to 6A

Time (100μs/Div)

Load Transient Response

VOUT

(100mV/Div)

IOUT

(2A/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 6A

Time (250ns/Div)

Output Ripple Voltage

VOUT

(20mV/Div)

VLX

(5V/Div)

Currrent Limit vs. Tem pe rature

7.0

7.5

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

Currrent Limit (A)

VIN = 5V, VOUT = 1.1V

Currrent Limit vs. Input Voltage

7.0

7.5

8.0

8.5

9.0

9.5

10.0

2.5 3 3.5 4 4.5 5 5.5

Input Vo ltage (V)

Currrent Limit (A)

VOUT = 1.1V

RT8073

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Time (10ms/Div)

Power Off from EN

VOUT

(2V/Div)

VEN

(5V/Div)

ILX

(5A/Div)

VIN = 12V, VOUT = 1.05V, IOUT = 3A

Time (250μs/Div)

Power On from EN

VOUT

(2V/Div)

VEN

(5V/Div)

ILX

(5A/Div)

VIN = 5V, VOUT = 3.3V, IOUT = 6A

Time (10ms/Div)

Power Off from VIN

VOUT

(2V/Div)

VIN

(5V/Div)

ILX

(5A/Div)

VIN = 5V, VOUT = 3.3V, IOUT = 6A

Time (1ms/Div)

Power On from VIN

VOUT

(2V/Div)

VIN

(5V/Div)

ILX

(5A/Div)

VIN = 5V, VOUT = 3.3V, IOUT = 6A

RT8073

DS8073-02 August 2014 www.richtek.com

Application Information

The basic RT8073 application circuit is shown in Typical

Application Circuit. External component selection is

determined by the maximum load current and begins with

the selection of the inductor value and operating frequency

followed by CIN and COUT.

Output Voltage Setting

The output voltage is set by a n external re sistive divider

a ccording to the following equation :

FB1

OUT REF FB2

VV1









RT8073

GND

FB RFB1

VOUT

RFB2

Figure 1. Setting the Output Voltage

Soft-Start (SS)

An internal current source charges a n external capa citor

to build the soft-start ra mp voltage (VSS). The VFB voltage

will track the VSS during soft-start interval. The chip will

use internal soft-start if the SS pin is floating. The nominal

internal soft-start time is 800μs.

With external soft-start, the typical soft-start ti me ca n be

calculated a s f ollowing equation :

tSS (ms) = 0.1 x CSS (nF)

For example, if CSS = 10nF, the soft-start time is 1ms.

Operating Frequency

Selection of the operating frequency is a tradeoff between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequency improves efficiency by

reducing internal gate charge and switching losses but

requires larger inductance and/or capacitance to maintain

low output ripple voltage.

The operating frequency of the RT8073 is determined by

an external resistor that is connected between the SHDN/

RT pin a nd GND. The value of the resistor sets the ra m p

current that is used to charge and discharge an internal

timing ca pacitor within the oscillator . The RT resistor value

can be determined by examining the frequency vs. RT

curve. Although frequency as high as 2MHz is possible,

the minimum on-time of the RT8073 imposes a minimum

limit on the operating duty cycle. The minimum on-time

is typically 80ns. Therefore, the minimum duty cycle is

equal to 100 x 80ns x f (Hz).

Figure 2

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 20 40 60 80 100 120 140 160 180 200

RT (k )

Swit ching Frequency (MHz) 1

Chip Enable Operation

The EN pin is the chip enable input. Pulling the EN pin

low (<0.4V) will shut down the device. During shutdown

mode, the RT8073 quiescent current drops to lower than

2μA. Driving the EN pin high (>1.5V, 5.5V) will turn on the

device again. For external ti ming control, the EN pin ca n

also be externally pulled high by adding a REN resistor

a nd CEN ca pa citor from the VIN pin (see Figure 3).

where VREF equals to 0.8V (typical)

The resistive divider allows the FB pin to sense a fra ction

of the output voltage a s shown in Figure 1.

Figure 3. Enable Timing Control

RT8073

GND

VIN REN

CEN

RT8073

12 DS8073-02 August 2014www.richtek.com

An external MOSFET can be added to implement digital

control on the EN pin when no system voltage above 1.5V

is available, a s shown in Figure 4. In this ca se, the pull-up

resistor, REN, is connected between VIN and the EN pin.

MOSFET Q1 will be under logic control to pull down the

EN pin.

Figure 4. Digital Ena ble Control Circuit

RT8073

GND

VIN REN

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant

frequency architectures by preventing sub-harmonic

oscillations at duty cycles greater than 50%. It is

a ccomplished internally by adding a compensating ra mp

to the inductor current signal. Normally, the maximum

inductor peak current is reduced when slope compensation

is added. In the RT8073, however, separated inductor

current signals are used to monitor over current condition.

This keeps the maximum output current relatively constant

regardless of duty cycle.

Hiccup Mode

For the RT8073, it provides Hiccup Mode U nder Voltage

Protection (UVP). When the output is shorted to ground,

the UVP function will be triggered to shut down switching

operation. If the under voltage condition remains for a

period, the RT8073 will retry automatically . When the under

voltage condition is removed, the converter will resume

operation. The UVP is disabled during soft-start period.

Figure 5. Hiccup Mode U nder Voltage Protection

Inductor Selection

The inductor value and operating frequency determine the

ripple current according to a specific input and output

voltage. The ripple current ΔIL increases with higher VIN

and decrea ses with higher inductance.

OUT OUT

LIN

I = 1

fL V

 



 



 

OUT OUT

L(MAX) IN(MAX)

L = 1

fI V

 



 



 

Having a lower ripple current ca n reduce not only the ESR

losses in the output ca pacitors but also the output voltage

ripple. However , it requires a large inductor to achieve this

goal.

For the ripple current selection, the value of ΔIL = 0.4(IMAX)

will be a rea sonable starting point. The largest ripple current

occurs at the highest VIN. To guarantee that the ripple

current stays below the specified maximum, the inductor

value should be chosen according to the following

equation :

The inductor's current rating (caused a 40°C temperature

rising from 25°C ambient) should be greater than the

maximum load current and its saturation current should

be greater tha n the short circuit pe ak current limit.

Time (1ms/Div)

Hiccup Mode

VOUT

(500mV/Div)

ILX

(5A/Div)

VOUT short to GND

RT8073

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Layout Considerations

Follow the PCB layout guidelines for optimal performa nce

of RT8073.

A ground plane is recommended. If a ground plane layer

is not used, the signal and power grounds should be

segregated with all small-signal components returning

to the GND pin at one point that is then connected to

the PGND pin close to the IC. The exposed pad should

be connected to GND.

Connect the terminal of the input capacitor(s), CIN, as

close a s possible to the VIN pin. This ca pacitor provides

the AC current into the internal power MOSFETs.

LX node is with high frequency voltage swing and should

be kept within small area. Keep all sensitive small-signal

nodes away from the LX node to prevent stray capacitive

noise pick-up.

Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of power components.

Connect the FB pin directly to the feedback resistors.

The resistor divider must be connected between VOUT

and GND.

Figure 6. Derating Curve of Maximum Power Dissipation

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the a mbient temperature, and θJA is the junction to a mbient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

a mbient thermal resistance, θJA, is layout dependent. For

SOP-8 (Exposed Pad) pa ckages, the thermal resistance,

θJA, is 49°C/W on a standard JEDEC 51-7 four-layer

thermal test board. For WDFN-12L 3x3 packages, the

thermal resistance, θJA, is 60°C/W on a sta ndard JEDEC

51-7 four-layer thermal test board. The maximum power

dissipation at TA = 25°C can be calculated by the following

formulas :

PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.041W for

SOP-8 (Exposed Pad) pa ckage

PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for

W DFN-12L 3x3 pa ckage

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. The derating curves in Figure 6 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0 25 50 75 100 125

Ambient Tempera tur e (°C)

Maximum Powe r Dissi pati on (W

)

WDFN-12L 3x3

Four-Layer PCB

SOP-8 (Exposed Pad)

RT8073

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Figure 7. PCB Layout Guide for W D FN-12L 3x3

Figure 8. PCB Layout Guide f or SOP-8 (Exposed Pad)

COMP

PGOOD

VIN

VIN BOOT

PGND

VOUT

GND

RFB1

RFB2

RTL

CBOOT

COUT

GND

CIN

GND

REN

CSS

RGOOD

GND

LX should be connected to

inductor by wide and short t rac e,

keep sensitive components away

from this trace.

Output capacitor

must be near RT8073

Connect the FB pin directly to feedback resistors. The

resistor divider mus t be connec ted between VOUT and GND.

CIN must be placed

between VIN and GND

as closer as pos sible.

COMP

GND

VIN

BOOT

PGND

VOUT

RFB1

RFB2

GND

CBOOT COUT

CIN

REN

GND

GND Output capacitor

must be near RT8073

LX should be connected to

inductor by wide and short trace,

keep sensitive components away

from this trace.

CIN must be placed

between VIN and GND

as closer as possible.

Connect the FB pin directly to f eedbac k resistors. The resistor

divider must be connected between V OUT and GND.

Table 2. Inductors

Component Suppli er Series Inductance (H) DCR (m) Curren t Rat ing (A) Case Si z e

Wurth Elektronik No.744308033 0.33 0.37 27 1070

Wurth Elektronik No.744355147 0.47 0.67 30 1365

Table 3. Capaci tors f or CIN an d COUT

Component Suppli er Part No . Capacitance (F) Case Size

TDK C3225X5R0J226M 22 1210

TDK C2012X5R0J106M 10 0805

Panasonic ECJ4YB0J226M 22 1210

Panasonic ECJ4YB1A106M 10 1210

TAIYO YUDEN LMK325BJ226ML 22 1210

TAIYO YUDEN JMK316BJ226ML 22 1206

TAIYO YUDEN JMK212BJ106ML 10 0805

Recommended component selection for T ypical Application

RT8073

DS8073-02 August 2014 www.richtek.com

Outline Dimension

EXPOSED THERMAL PAD

(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dime nsio ns In Millime ters Dimensions In Inches

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1 Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2 Y 3.000 3.500 0.118 0.138

RT8073

16 DS8073-02 August 2014www.richtek.com

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Min. Max. Min. Max.

0.700 0.800 0.028 0.031

0.000 0.050 0.000 0.002

0.175 0.250 0.007 0.010

0.150 0.250 0.006 0.010

2.950 3.050 0.116 0.120

Option1 2.300 2.650 0.091 0.104

Option2 1.970 2.070 0.078 0.081

2.950 3.050 0.116 0.120

Option1 1.400 1.750 0.055 0.069

Option2 1.160 1.260 0.046 0.050

0.350 0.450 0.014 0.018

0.450 0.018

Symbol Dim e nsions In Millime te rs Dime nsions In Inches

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar M ark Options

W-Type 12L DFN 3x3 Package