Home > Products > Intellectual Property > Lattice IP Cores > 32 Bit PCI Master/Target
32 Bit PCI Master/Target
Overview
Peripheral Component Interconnect (PCI) is a widely accepted bus standard
that is used in many applications including te lecommunications, embedded
systems, high performance peripheral cards, and networking.
Lattice's PCI IP core provides an ideal solution that meets the needs of today's
high performance PCI applications. It is fully compliant with the PCI Local Bus
Specification, revision 2.2 for speeds up to 66MHz. The PCI core provides a customizable 32/64-bit master/target or
target solution. The core bridges the gap between the PCI interface and a specific design application, providing an
integrated PCI solution. The PCI solution allows designers to focus on the application rather than on the PCI specification,
resulting in a faster time-to-market.
The Lattice PCI offering is available in a number of configurations covering 32-bit
PCI, 64-bit PCI, 32-bit local bus, 64-bit local bus, master/target and target
applications. In this document, details of 64-bit operation and master operation
only apply when relevant. The appendix to the user's guide shows what cores are
available on which devices.
Features
Available as 32/64-Bit PCI Bus and 32/64-Bit Local Bus
PCI SIG Local Bus Specification, Revision 3.0 Compliant
64-Bit Addressing Support (Dual Address Cycle)
Fast Back-to-Back Transaction Support
Supports Zero Wait State Transactions
Special Cycle Transaction Support
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Capabilities List Pointer Support
Parity Error Detection
Up to Six Base Address Registers (BARs)
Customizable Configuration Space
Up to 66MHz PCI
Fully Synchronous Design
Performance and Resource Utilization
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 683 1059 640 - 50 33
32-bit Master/Target 66 MHz 1076 1691 661 - 50 66
LatticeECP31
1. Performance and utilization data are generated using an LFE3-95EA-7FN1156CES device with Lattice Diamond 1.0 software.
Performance may vary when using a different software version or targeting a different device density or speed grade within the
LatticeECP3 family.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 856 1068 642 - 50 33
32-bit Master/Target 66 MHz 1086 1700 663 - 50 66
LatticeECP2M1
1. Performance and utilization data are generated using an LFE2M-35E-6F672C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M fam il y.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 856 1068 642 - 50 33
32-bit Master/Target 66 MHz 1086 1700 663 - 50 66
LatticeECP21
1. Performance and utilization data are generated using an LFE2-20E-6F672C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 family.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 846 1060 642 - 50 33
32-bit Master/Target 66 MHz 1083 1690 663 - 50 66
LatticeEC/P1
1. Performance and utilization data are generated usi n g an LFEC33E-5F672C device with Lattice Diamond 1.0 software. Perfor mance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC
family.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 724 1050 640 - 50 33
32-bit Master/Target 66 MHz 1085 1722 663 - 50 66
LatticeSC1
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Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master /Target 33 MHz 406 803 582 - 50 33
MachXO21
1. Prelimina r y in f o rm a tio n . Pe rfor m ance and utilizati o n
data are generated using an LCMXO2-1200HC-6TG144CES device with Lattice
Diamond 1.0 software. Performance may vary when using a different software version or targeting a different device density or speed
g
rade within the MachXO2 family.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 542 1060 642 - 50 33
MachXO1
1. Performance and uti lization data are generated using an
LCMXO2280C-5FT324C device with Lattice Diamond 1.0 software.
Performance may vary when using a different software version or targeting a different device density or speed grade within the
MachXO family.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 851 1060 640 - 50 33
32-bit Master/Target 66 MHz 1081 1692 661 - 50 66
LatticeXP21
1. Performance and uti lization data are generated using an
LFXP2-17E-6F484C device with Lattice Diamond 1.0 software. Performance
may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.
Bus Width IPexpress Mode Slices LUTs Registers sysMEM EBRs External
Pins fMAX (MHz)
32-bit Master/Target 33 MHz 846 1060 642 - 50 33
32-bit Master/Target 66 MHz 1083 1690 663 - 50 66
LatticeXP1
1. Performance and uti lization data are generated using an
LFXP20C-5F484C device with Lattice Diamond 1.0 software. Performance
may vary when usin
g
a different software version or tar
g
etin
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a different
device density or speed
g
rade within the LatticeXP
family
Ordering In formation
Family Bus Width Bus Speed Master/Target
Part Number
LatticeECP3 32-bit 33MHz, 66MHz PCI-MT32-E3-U6
LatticeECP2M 32-bit 33MHz, 66MHz PCI-MT32-PM-U6
LatticeECP2 32-bit 33MHz, 66MHz PCI-MT32-P2-U6
LatticeECP/EC 32-bit 33MHz, 66MHz PCI-MT32-E2-U6
LatticeSC 32-bit 33MHz, 66MHz PCI-MT32-SC-U6
MachXO2 32-bit 33MHz PCI-MT32-M2-U1
MachXO 32-bit 33MHz PCI-MT32-XO-U6
LatticeXP2 32-bit 33MHz, 66MHz PCI-MT32-X2-U6
LatticeXP 32-bit 33MHz, 66MHz PCI-MT32-XM-U6
IP Version: PCI Master/Target 33MHz = 6.6, PCI Master/Target 66MHz = 6.4
Evaluate: To download a full evaluation version of this IP, go to the Lattice IP Server tab in the IPexpress Main Window.
All ispLeverCORE IP cores and modules available for download are visible on this tab. *PCI cores for ORCA and
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ispXPGA,devices are supported by the Lattice factory-conf igurable design flow.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.
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