© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. 3 1Publication Order Number:
NB3V1102C/D
NB3V110xC Series
3.3V/2.5V/1.8V LVCMOS
Low Skew Fanout Buffer
Family
Description
The NB3V110xC are a modular, high−performance, low−skew,
general purpose LVCMOS clock buffer family. The family of devices
is designed with a modular approach. Four different fan−out
variations, 1:2, 1:3, 1:4, 1:6 and 1:8, are available. All of the devices
are pin compatible to each other for easy handling. All family
members share the same high performing characteristics like low
additive jitter, low skew, and wide operating temperature range. The
NB3V110xC supports an asynchronous output enable control (OE)
which switches the outputs into a low state when OE is low. The
NB3V110xC devices operate in a 3.3 V, 2.5 V and 1.8 V environment
and are characterized for operation from −40°C to 105°C.
Features
•Operating Temperature Range: –40°C to 105°C
•High−Performance 1:2, 1:3, 1:4, 1:6, 1:8 LVCMOS Clock Buffer
•Available in 8−, 14−, 16−Pin TSSOP and WDFN8 Packages
•Very Low Output−to−Output Skew < 50 ps
•Very Low Additive Jitter < 200 fs
•Supply Voltage: 3.3 V, 2.5 V or 1.8 V
•fmax = 250 MHz for 3.3 V; fmax = 180 MHz for 2.5 V;
fmax = 133 MHz for 1.8 V
•These Devices are Pb−Free and are RoHS Compliant
BLOCK DIAGRAM
Q0
Q1
Q2
Q3
Qn
CLKIN LV
CMOS
OE
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
S
S
S
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See detailed ordering, marking and shipping information on
page 9 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
A = Assembly Location
M = Date Code
L = Wafer Lot
Y = Year
W, WW = Work Week
G= Pb−Free Package
TSSOP−14
TSSOP−8
1106
V
ALYWG
G
1
14
(Note: Microdot may be in either location)
TSSOP−16
DT SUFFIX
CASE 948F
TSSOP−8
DT SUFFIX
CASE 948S
10x
YWW
AG
1
8
WDFN8, 2x2
MT SUFFIX
CASE 511AT
0X MG
G
1
WDFN8
TSSOP−14
DT SUFFIX
CASE 948G
1108
V
ALYWG
G
1
16
TSSOP−16
NB3V110xC Series
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2
NB3V1102C
NB3V1103C
NB3V1104C NB3V1106C
Figure 1. Pin Configuration
TSSOP−14
TSSOP−8 and WDFN8
1
2
3
4
8
7
6
5
CLKIN
OE
Q0
GND
Q1
NC/Q3
VDD
NC/Q2
CLKIN
OE
Q0
GND
VDD
Q4
GND
Q1
Q3
VDD
Q2
GND
Q5
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NB3V1108C
TSSOP−16
CLKIN
OE
Q0
GND
VDD
Q4
GND
Q1
Q3
VDD
Q2
GND
Q5
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
15
Q6 Q7
8
16
Table 1. PIN DESCRIPTION
Devices
LVCMOS Clock
Input LVCMOS Clock
Output Enable LVCMOS Clock Output Device
Supply Voltage Device
Ground
CLKIN OE Q0, Q1, ... Q7 VDD GND
NB3V1102C 1 2 3, 8 6 4
NB3V1103C 1 2 3, 8, 5 6 4
NB3V1104C 1 2 3, 8, 5, 7 6 4
NB3V1106C 1 2 3, 14, 11, 13, 6, 9 5, 8, 12 4, 7, 10
NB3V1108C 1 2 3, 16, 13, 15, 6, 11, 8, 9 5, 10, 14 4, 7, 12
NOTE: Pins not mentioned in the table are NC.
Table 2. OUTPUT LOGIC TABLE
INPUTS OUTPUTS
CLKIN OE Qn
X L L
L H L
H H H
Table 3. ATTRIBUTES
Characteristic Value Unit
ESD Protection Human Body Model (HBM) per ANSI/ESDA/JEDEC JS−001−2014
Charged Device Model (CDM) per ANSI/ESDA/JEDEC JS−002−2014 5000
1500 V
V
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1) Level 1 −
Meets or exceeds JEDEC Spec JESD78D (LU) IC Latchup Test
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm2, 2 oz.)
NB3V110xC Series
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3
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 2)
Over operating free−air temperature range (unless otherwise noted)
Symbol Condition Value Unit
VDD Supply Voltage Range –0.5 to 4.6 V
VIN Input Voltage Range (Note 3) –0.5 to VDD + 0.5 V
VOOutput Voltage Range (Note 3) –0.5 to VDD + 0.5 V
IIN Input Current ±20 mA
IOContinuous Output Current ±50 mA
qJA Thermal Resistance (Junction−to−Ambient) TSSOP−8 151.2* °C/W
TSSOP−14 104*
TSSOP−16 32*
110**
WDFN8 190**
qJC Thermal Resistance (Junction−to−Case top) TSSOP−8 35 °C/W
TSSOP−14 8.6
TSSOP−16 10
WDFN8 10
TJMaximum Junction Temperature 125 °C
TSTG Storage Temperature Range –65 to 150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
2. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm2, 2 oz.)
3. For additional information, see Application Note AND8003/D.
*JEDEC51.7 four layer PCB with 100 sqmm, 2 oz with two 80x80x1oz ground planes.
**JEDEC51.3 two layer PCB with 100 sqmm, 2 oz.
NB3V110xC Series
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Table 5. RECOMMENDED OPERATING CONDITIONS
Over operating free−air temperature range (unless otherwise noted)
Symbol Condition Min Typ Max Unit
VDD Supply voltage range 3.3 V supply 3.0 3.3 3.6 V
2.5 V supply 2.3 2.5 2.7
1.8 V supply 1.71 1.8 1.89
VIL Low−level input voltage VDD = 3.0 V to 3.6 V VDD/2 –
600 mV
VDD = 2.3 V to 2.7 V VDD/2 –
400
VDD = 1.71 V to 1.89 V 0.3xVDD V
VIH High−level input voltage VDD = 3.0 V to 3.6 V VDD/2 +
600 mV
VDD = 2.3 V to 2.7 V VDD/2 +
400
VDD = 1.71 V to 1.89 V 0.7xVDD V
Vth Input threshold voltage VDD = 2.3 V to 3.6 V VDD/2 V
VDD = 1.71 V to 1.89 V VDD/2 V
tr / tfInput slew rate (Note 4) 1 4 V/ns
twMinimum pulse width at CLKIN VDD = 3.0 V to 3.6 V 1.8 ns
VDD = 2.3 V to 2.7 V 2.75
VDD = 1.71 V to 1.89 V 3.75
fCLK LVCMOS clock Input Frequency VDD = 3.0 V to 3.6 V DC 250 MHz
VDD = 2.3 V to 2.7 V DC 180
VDD = 1.71 V to 1.89 V DC 133
TAOperating free−air temperature –40 105 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Guaranteed by Design.
NB3V110xC Series
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Table 6. DEVICE CHARACTERISTICS Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol Parameter Condition Min Typ Max Unit
OVERALL PARAMETERS FOR ALL VERSIONS
IDD Static device current OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V 0.2 mA
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
2.7 V 0.2
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
1.89 V 0.2
IPD Power down current OE = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V, 2.7 V or 1.89 V (For 1102C, 1103C, 1104C) 60 mA
OE = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V, 2.7 V or 1.89 V (For 1106C, 1108C) 75
CPD Power dissipation capacitance per out-
put (Note 6) VDD = 3.3 V; f = 10 MHz 9pF
VDD = 2.5 V; f = 10 MHz 9
VDD = 1.8 V; f = 10 MHz 9
IIInput leakage current at OE VI = 0 V or VDD, VDD = 3.6 V or 2.7 V ± 8 mA
Input leakage current at CLKIN ± 8
Input leakage current at OE, CLKIN VI = 0 V or VDD, VDD = 1.89 V ± 8
ROUT Output impedance VDD = 3.3 V 40 W
VDD = 2.5 V 45
VDD = 1.8 V 60
fOUT Output frequency VDD = 3.0 V to 3.6 V DC 250 MHz
VDD = 2.3 V to 2.7 V DC 180
VDD = 1.71 V to 1.89 V DC 133
OUTPUT PARAMETERS FOR VDD = 3.3 V + 0.3 V
VOH High−level output voltage VDD = 3 V, IOH = –0.1 mA 2.9 V
VDD = 3 V, IOH = –8 mA 2.5
VDD = 3 V, IOH = –12 mA 2.2
VOL Low−level output voltage VDD = 3 V, IOL = 0.1 mA 0.1 V
VDD = 3 V, IOL = 8 mA 0.5
VDD = 3 V, IOL = 12 mA 0.8
tPLH, tPHL Propagation delay (Note 7) CLKIN to Qn 0.8 2.0 ns
tsk(o) Output skew (Note 7) Equal load of each output 85°C 50 ps
Equal load of each output 105°C 60
tr/tfRise and fall time 20%–80% (VOH − VOL) 0.12 0.8 ns
tDIS Output disable time (Note 7) OE to Qn 6 ns
tEN Output enable time (Note 7) OE to Qn 6 ns
tsk(p) Pulse skew; tPLH(Qn) – tPHL(Qn) (Note 8) To be measured with input duty cycle of 50% 180 ps
tsk(pp) Part−to−part skew Under equal operating conditions for two parts 0.5 ns
Tjit(f)Additive jitter rms 12 kHz...20 MHz fOUT = 100 MHz 100 fs
12 kHz...20 MHz fOUT = 156.25 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 W to VDD/2 (see Figure 2).
6. This is the formula for the power dissipation calculation.
Ptot = Pstat + Pdyn + PCload [W] Pstat = VDD x IDD [W]
Pdyn = CPD x VDD2 x ƒ x n [W]
PCload = Cload x VDD2 x ƒ x n [W]
n = Number of switching output pins
7. With rail to rail input clock.
8. tsk(p) depends on output rise− and fall−time (tr/tf). The output duty−cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse−width of ideal output waveform and tperiod is 1/fOUT.
NB3V110xC Series
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Table 7. DEVICE CHARACTERISTICS (continued)
Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol Parameter Condition Min Typ Max Unit
OUTPUT PARAMETERS FOR VDD = 2.5 V + 0.2 V
VOH High−level output voltage VDD = 2.3 V, IOH = –0.1 mA 2.2 V
VDD = 2.3 V, IOH = –8 mA 1.7
VOL Low−level output voltage VDD = 2.3 V, IOL = 0.1 mA 0.1 V
VDD = 2.3 V, IOL = 8 mA 0.5
tPLH, tPHL Propagation delay (Note 10) CLKIN to Qn 1.8 ns
tsk(o) Output skew (Note 10) Equal load of each output 85°C 50 ps
Equal load of each output 105°C 60
tr/tfRise and fall time 20%–80% (VOH − VOL) 0.12 1.2 ns
tDIS Output disable time (Note 10) OE to Qn 10 ns
tEN Output enable time (Note 10) OE to Qn 10 ns
tsk(p) Pulse skew ; tPLH(Qn) – tPHL(Qn)
(Note 9) To be measured with input duty cycle of 50% 220 ps
tsk(pp) Part−to−part skew Under equal operating conditions for two
parts 1.2 ns
tjit(f)Additive jitter rms 12 kHz...20 MHz fOUT = 100 MHz 150 fs
12 kHz...20 MHz fOUT = 156.25 MHz 100
OUTPUT PARAMETERS FOR VDD = 1.8 V + 5%
VOH High−level output voltage VDD = 1.71 V, IOH = –0.1 mA 1.6 V
VDD = 1.71 V, IOH = –4 mA 0.75xVDD
VOL Low−level output voltage VDD = 1.71 V, IOL = 0.1 mA 0.1 V
VDD = 1.71 V, IOL = 4 mA 0.25xVDD
tPLH, tPHL Propagation delay (Note 10) CLKIN to Qn 1.8 3.5 ns
tsk(o) Output skew (Note 10) Equal load of each output 75 ps
tr/tfRise and fall time 20%–80% (VOH − VOL) 0.17 1.2 ns
tDIS Output disable time (Note 10) OE to Qn 10 ns
tEN Output enable time (Note 10) OE to Qn 10 ns
tsk(p) Pulse skew ; tPLH(Qn) – tPHL(Qn)
(Note 9) To be measured with input duty cycle of 50% 450 ps
tsk(pp) Part−to−part skew Under equal operating conditions for two
parts 1.2 ns
tjit(f)Additive jitter rms 12 kHz...20 MHz, fOUT = 100 MHz 200 fs
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. tsk(p) depends on output rise− and fall−time (tr/tf). The output duty−cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse−width of ideal output waveform and tperiod is 1/fOUT.
10.With rail to rail input clock.
NB3V110xC Series
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PARAMETERS MEASUREMENT INFORMATION
Figure 2. Test Load Circuit
Figure 3. Application Load with 50 W Line Termination
Figure 4. Application Load with Series Line Termination
Figure 5. tDIS and tEN for Disable Low Figure 6. Output Skew tSk(o)
Z= 50
OΩ
R=50 W
from Measurement Equipment
V/2
DD
LVCMOS
Output
V = 3.3 V, 2.5 V or 1.8 V
DD
C=2pF
parasitic capacitance
LVCMOS
Output
VDD
R=100 W
R=100 W
Z= 50
OΩ
parasitic input capacitance
V = 3.3 V, 2.5V or 1.8 V
DD
LVCMOS
Output Z= 50
OΩ
RS = 10 Ohms (VDD = 3.3 V)
RS = 5 Ohms (VDD = 2.5 V)
RS = 0 Ohms (VDD = 1.8 V)
parasitic input capacitance
V = 3.3 V, 2.5 V or 1.8 V
DD
tDIS tEN
VIN /2
OE
Qn VIN /2
tsk(o)
VDD /2
Qn+1 VDD /2
Qn
tsk(o)
NB3V110xC Series
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8
tr
Qn
80% VOH −VOL
CLKIN
tf
20% VOH −VOL
VOH
VOL
tPLH
VDD/2
QnVDD/2
CLKIN
tPHL
Figure 7. Pulse Skew tsk(p) and Propagation Delay
tPLH/tPHL
Figure 8. Rise/Fall Times tr /tf
Note: tsk(p) = |tPLH − tPHL|
Figure 9. Typical NB3V110xC Phase Noise Plot at fCarrier = 100 MHz, VDD = 3.3 V, 255C
r
Output
F_carrier = 100 MHz
Output (DUT + Source)
Input Source
Integration Range: 12 kHz − 20 MHz
DUT + Source Phase Jitter = 66.92 fs
Input Source Phase Jitter = 36.72 fs
Input Source 100 MHz
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 55.94 fs. The additive RMS phase jitter
performance o f the fan out buffer is highly dependent on the
phase noise of the input source.
To obtain the most precise additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is greater than the noise floor of the device under test,
the source noise will dominate the additive phase jitter
calculation and lead to an incorrect negative result for the
additive phase noise within the integration range. The
Figure above is a good example of the NB3V110xC source
generator phase noise having a significantly lower floor than
the DUT and results in an additive phase jitter of 55.94 fs.
Additive RMS phase jitter +RMS phase jitter of output2*RMS phase jitter of input2
Ǹ
55.94 fs +66.92 fs2*36.72 fs2
Ǹ
NB3V110xC Series
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9
Figure 10. Typical NB3V110xC Phase Noise Plot at fCarrier = 156.25 MHz, VCC = 3.3 V V, 255C
u
n
I
r
Input Source
Output (DUT + Source)
Output
Input Source 156.25 MHz
F_carrier = 156.25 MHz Integration Range: 12 kHz − 20 MHz
DUT + Source Phase Jitter = 51.76 fs
Input Source Phase Jitter = 23.5 fs
The additive RMS phase jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 46.11 fs.
Additive RMS phase jitter +RMS phase jitter of output2*RMS phase jitter of input2
Ǹ
46.11 fs +51.76 fs2*23.5 fs2
Ǹ
Figures 9 and 10 were created with measured data from
Agilent−E5052A/B Signal Source Analyzer using ON
Semiconductor Phase Noise Explorer web tool. This free
application enables an interactive environment for advanced
phase noise and jitter analysis of timing devices and clock
tree designs. To see the performance of NB3V110xC
beyond conditions outlined in this datasheet, please visit the
ON Semiconductor Green Point Design Tools homepage.
Table 8. ORDERING INFORMATION
Device Marking Package Shipping†
NB3V1102CDTR2G 102 TSSOP−8
(Pb−Free) 2500 / Tape & Reel
NB3V1103CDTR2G 103
NB3V1104CDTR2G 104
NB3V1102CMTTBG 02 WDFN8
(Pb−Free) 3000 / Tape & Reel
NB3V1104CMTTBG 04
NB3V1106CDTR2G 1106
VTSSOP−14
(Pb−Free) 2500 / Tape & Reel
NB3V1108CDTR2G 1108
VTSSOP−16
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Please contact your ON Semiconductor sales representative for availability of parts in tube.
ÍÍ
ÍÍ
ÍÍ
C
A
SEATING
PLANE
D
E
0.10 C
A3
A
A1
0.10 C
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
DATE 26 FEB 2010
SCALE 4:1
DIM
A
MIN MAX
MILLIMETERS
0.70 0.80
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D
E
e
L
PIN ONE
REFERENCE
0.05 C
0.05 C
A0.10 C
NOTE 3
L2
e
b
B
4
8
8X
1
5
0.05 C
L1
2.00 BSC
2.00 BSC
0.50 BSC
0.40 0.60
--- 0.15
BOTTOM VIEW
L
7X
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÉÉÉ
ÉÉÉ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
DETAIL A
L2 0.50 0.70
B
TOP VIEW
SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.78
7X
DIMENSIONS: MILLIMETERS
0.30 PITCH
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
8X
1
PACKAGE
OUTLINE
RECOMMENDED
XX = Specific Device Code
M = Date Code
G= Pb−Free Device
XXMG
G
1
0.88
(Note: Microdot may be in either location)
2X
2X
8X
e/2
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON48654E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
WDFN8, 2X2, 0.5 P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP−16
CASE 948F−01
ISSUE B
DATE 19 OCT 2006
SCALE 2:1
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
1
16
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYW
1
16
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G or G= Pb−Free Package
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASH70247A
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP−14 WB
CASE 948G
ISSUE C
DATE 17 FEB 2016
SCALE 2:1
1
14
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYWG
G
1
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASH70246A
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP−14 WB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP−8
CASE 948S−01
ISSUE C
DATE 20 JUN 2008
GENERIC
MARKING DIAGRAM*
XXX
YWW
A G
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B4.30 4.50 0.169 0.177
C--- 1.10 --- 0.043
D0.05 0.15 0.002 0.006
F0.50 0.70 0.020 0.028
G0.65 BSC 0.026 BSC
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
L
2X L/2
−U−
S
U0.20 (0.008) TS
U
M
0.10 (0.004) V S
T
0.076 (0.003)
−T−
−V−
−W−
8x REFK
SCALE 2:1
IDENT
K0.19 0.30 0.007 0.012
S
U0.20 (0.008) T
DETAIL E
F
M
0.25 (0.010)
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
K1
K
JJ1
SECTION N−N
J0.09 0.20 0.004 0.008
K1 0.19 0.25 0.007 0.010
J1 0.09 0.16 0.004 0.006
N
N
XXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON00697D
ON SEMICONDUCTOR STANDARD
TSSOP−8
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON00697D
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. 18 APR 2000
AADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS. 13 JAN 2006
BCORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C.
REBELLO.
13 MAR 2006
CREMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED
MARKING INFORMATION. REQ. BY C. REBELLO.
20 JUN 2008
© Semiconductor Components Industries, LLC, 2008
June, 2008 − Rev. 01C
Case Outline Number:
948S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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