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P/N:PM1129 REV. 1.1, JUL. 14, 2005
MX29LV320MT/B
32M-BIT [4M x 8/2M x 16] SINGLE VOLTAGE 3V
ONLY FLASH MEMORY
FEATURES
GENERAL FEA TURES
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• 4,194,304 x 8 / 2,097,152 x 16 switchable
• Secto r structure
- 8KB (4KW) x 8 and 64KB(32KW) x 63
• Sector Protection/Chip Unprotect
- Pro vides sector group protect functio n to prevent pro-
gram o r erase o peratio n in the pro tected sector group
- Pro vides chip unprotect function to allow code changes
- Provides tempo rary sector g ro up unprotect functio n
for co de changes in previo usly protected sector groups
• Secured Silico n Sector
- Provides a 128-word OTP area for per manent, se-
cure identificatio n
- Can be pro grammed and lo cked at f actory o r by cus-
tomer
• Latch-up pro tected to 250mA fro m -1V to VCC + 1V
• Lo w VCC write inhibit is equal to o r less than 1.5V
• Co mpatible with JEDEC standard
- Pin-o ut and software compatible to single power sup-
ply Flash
PERFORMANCE
• High Performance
- F ast access time: 70R/90ns
- Page read time: 25ns
- Sector erase time: 0.5s (typ.)
- Effectiv e write buffer wo rd pro gramming time: 22us
- 4 wo rd/8 byte page read buffer
- 16 wo rd/ 32 byte write buff er: reduces pro gramming
time for multiple-wo rd/byte updates
• Low Power Consumption
- Active read current: 18mA(typ.)
- Active write current: 50mA(typ.)
- Standby current: 20uA(typ.)
• Minimum 100,000 erase/pro gram cycle
• 20-year data retentio n
SOFTW ARE FEA TURES
• Suppo rt Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access
• Program Suspend/Resume
- Suspend program operatio n to read other sectors
• Erase Suspend/Erase Resume
- Suspends secto r erase operatio n to read data from
or pro g ram data to another secto r which is not being
erased
• Status Reply
- Data# po lling & To ggle bits pro vide detectio n o f pro-
gram and erase o peration completio n
HARDWARE FEATURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program
and erase o peratio n completio n
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the inter nal
state machine to read mo de
• WP#/ACC input
- Write pro tect (WP#) function allows pro tection of two
outer most boot sectors, regardless of sector protect
status
- ACC (high voltage) accelerates programming time
fo r higher thro ughput during system
PACKAGE
• 44-pin SOP
• 48-pin TSOP
• 48-ball CSP
GENERAL DESCRIPTION
The MX29LV320MT/B is a 32-mega bit Flash memory
organized as 4M bytes of 8 bits or 2M bytes of 16 bits.
MXIC's Flash memo ries offer the mo st co st-effective and
reliable read/write no n-v o latile random access memo ry .
The MX29LV320MT/B is packaged in 44-pin SOP, 48-
pin TSOP and 48-ball CSP. It is designed to be repro-
gr ammed and erased in system o r in standard EPR OM
programmers.
The standard MX29LV320MT/B of fers access time as
fast as 70ns, allowing o peratio n of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV320MT/B has separate chip enable
(CE#) and o utput enable (OE#) co ntrols.
MXIC's Flash memo ries augment EPROM functio nality
with in-circuit electrical erasure and pro gramming. The
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P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
MX29LV320MT/B uses a command register to manage
this functio nality.
MXIC Flash techno lo gy reliably sto res memory co ntents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program mecha-
nisms. In additio n, the combination of adv anced tunnel
oxide processing and low internal electric fields fo r erase
and programming operations produces reliable cycling.
The MX29LV320MT/B uses a 2.7V to 3.6V VCC supply
to perf o rm the High Reliability Erase and auto Pro gram/
Erase algo rithms.
The highest degree o f latch-up protection is achieved with
MXIC's pro prietary non-epi process. Latch-up protectio n
is pro ved fo r stresses up to 100 milliamperes o n address
and data pin fro m -1V to VCC + 1V.
AUTOMATIC PROGRAMMING
The MX29LV320MT/B is b yte/word/page programmable
using the A uto matic Programming algo rithm. The Auto-
matic Programming algor ithm makes the external sys-
tem do no t need to have time o ut sequence nor to verify
the data programmed. The typical chip programming time
at ro om temperature o f the MX29L V320MT/B is less than
31.5 seco nds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to o nly write pro gram set-up co mmands (including 2 un-
lo ck write cycle and A0H) and a program co mmand (pro-
gram data and address). The device auto matically times
the pro gramming pulse width, pro vides the program veri-
ficatio n, and co unts the number of sequences. A status
bit similar to D ATA# po lling and a status bit toggling be-
tween co nsecutiv e read cycles, pro vide f eedback to the
user as to the status o f the pro gramming o peratio n.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at ro o m temperature is acco mplished in
less than 32 seconds. The Automatic Erase algor ithm
auto matically programs the entire arra y prior to electrical
erase. The timing and verificatio n o f electrical erase are
co ntro lled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV320MT/B is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. Sector erase modes
allow sectors o f the array to be erased in o ne erase cycle.
The Auto matic Sector Erase algo rithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electr ical erase are con-
tro lled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard micro processo r write timings. The device will auto-
matically pre-program and verify the entire arra y. Then
the device automatically times the erase pulse width,
pro vides the erase verificatio n, and counts the number of
sequences. A status bit toggling between consecutive
read cycles pro vides f eedback to the user as to the sta-
tus o f the programming o peratio n.
Register contents ser ve as inputs to an inter nal state-
machine which co ntro ls the erase and pro gramming cir-
cuitry. During write cycles, the co mmand register inter-
nally latches address and data needed f o r the pro gram-
ming and erase o perations. During a system write cycle,
addresses are latched o n the falling edge, and data are
latched o n the rising edge o f WE# .
MXIC's Flash technology combines years of EPROM
e xperience to produce the highest levels o f quality, reli-
ability, and cost effectiveness. The MX29LV320MT/B
electrically erases all bits simultaneously using Fo wler-
No rdheim tunneling. The bytes are pro grammed by us-
ing the EPROM programming mechanism o f hot electron
injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend co mmand. After Erase Suspend is co mpleted,
the de vice sta ys in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full co mmand set.
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MX29LV320MT/B
PIN CONFIGURATION
48 TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV320MT/B
44 SOP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
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MX29LV320MT/B
SYMBOL PIN NAME
A0~A20 Address Input
Q0~Q14 Data Inputs/Outputs
Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode)
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
RESET# Hardware Reset Pin, Active Low
WP#/ACC Hardware Write Protect/Programming
Acceleratio n input
R Y/BY# Read/Busy Output
BYTE# Selects 8 bit or 16 bit mo de
VCC +3.0V single power supply
GND Device Ground
N C Pin No t Connected Internally
PIN DESCRIPTION LOGIC SYMBOL
16 or 8
Q0-Q15
(A-1)
RY/BY#
A0-A20
CE#
OE#
WE#
RESET#
WP#/ACC
BYTE#
21
48 Ball CSP (Top View, Ball Do wn)
A13
A9
WE#
RY/
BY#
A7
A3
A
6
5
4
3
2
1
BCDEF GH
A12
A8
RES-
ET#
WP#/
ACC
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
Q7
Q5
Q2
Q0
A0
BYTE#
Q14
Q12
Q10
Q8
CE#
Q15/
A-1
Q13
VCC
Q11
Q9
OE#
GND
Q6
Q4
Q3
Q1
GND
8.0 mm
6.0 mm
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MX29LV320MT/B
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTA GE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15
A0-A20
CE#
OE#
WE#
WP#
BYTE#
RESET#
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MX29LV320MT/B
Sector Sector Sector Address Sector Size (x8) (x16)
Group A20-A12 (Kbytes/Kwords) Address Range Address Range
1 SA0 000000xxx 64/32 000000h-00FFFFh 000000h-07FFFh
1 SA1 000001xxx 64/32 010000h-01FFFFh 008000h-0FFFFh
1 SA2 000010xxx 64/32 020000h-02FFFFh 010000h-17FFFh
1 SA3 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh
2 SA4 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh
2 SA5 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh
2 SA6 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh
2 SA7 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh
3 SA8 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh
3 SA9 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh
3 SA10 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh
3 SA11 001011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh
4 SA12 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh
4 SA13 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh
4 SA14 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh
4 SA15 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh
5 SA16 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh
5 SA17 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh
5 SA18 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh
5 SA19 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh
6 SA20 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh
6 SA21 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh
6 SA22 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh
6 SA23 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh
7 SA24 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh
7 SA25 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh
7 SA26 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh
7 SA27 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
8 SA28 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh
8 SA29 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh
8 SA30 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh
8 SA31 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh
9 SA32 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh
9 SA33 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh
9 SA34 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh
9 SA35 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh
10 SA36 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh
10 SA37 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh
BLOCK STRUCTURE
MX29LV320MT SECTOR GROUP ARCHITECTURE
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MX29LV320MT/B
Sector Sector Sector Address Sector Size (x8) (x16)
Group A20-A12 (Kbytes/Kwords) Address Range Address Range
10 SA38 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh
10 SA39 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh
11 SA40 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh
11 SA41 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh
11 SA42 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh
11 SA43 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh
12 SA44 101100xxx 64/32 2C0000h-2CFFFFh 160000h-147FFFh
12 SA45 101101xxx 64/32 2D0000h-2DFFFFh 168000h-14FFFFh
12 SA46 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh
12 SA47 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh
13 SA48 110000xxx 64/32 300000h-30FFFFh 180000h-187FFFh
13 SA49 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh
13 SA50 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh
13 SA51 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh
14 SA52 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh
14 SA53 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh
14 SA54 110110xxx 64/32 360000h-36FFFFh 1B0000h-1B7FFFh
14 SA55 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh
15 SA56 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh
15 SA57 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh
15 SA58 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh
15 SA59 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh
16 SA60 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh
16 SA61 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh
16 SA62 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh
17 SA63 111111000 8/4 3F0000h-3F1FFFh 1F8000h-1F8FFFh
18 SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h-1F9FFFh
19 SA65 111111010 8/4 3F4000h-3F5FFFh 1FA000h-1FAFFFh
20 SA66 111111011 8/4 3F6000h-3F7FFFh 1FB000h-1FBFFFh
21 SA67 111111100 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh
22 SA68 111111101 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh
23 SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h-1FEFFFh
24 SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h-1FFFFFh
No te:The address range is A20:A-1 in byte mo de (BYTE#=VIL) o r A20:A0 in wo rd mode (BYTE#=VIH)
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MX29LV320MT/B
Sector Sector Sector Address Sector Size (x8) (x16)
Group A20-A12 (Kbytes/Kwords) Address Range Address Range
1 SA0 000000000 8/4 000000h-001FFFh 000000h-000FFFh
2 SA1 000000001 8/4 002000h-003FFFh 001000h-001FFFh
3 SA2 000000010 8/4 004000h-005FFFh 002000h-002FFFh
4 SA3 000000011 8/4 006000h-007FFFh 003000h-003FFFh
5 SA4 000000100 8/4 008000h-009FFFh 004000h-004FFFh
6 SA5 000000101 8/4 00A000h-00BFFFh 005000h-005FFFh
7 SA6 000000110 8/4 00C000h-00DFFFh 006000h-006FFFh
8 SA7 000000111 8/4 00E000h-00FFFFh 007000h-007FFFh
9 SA8 000001xxx 64/32 010000h-01FFFFh 008000h-00FFFFh
9 SA9 000010xxx 64/32 020000h-02FFFFh 010000h-017FFFh
9 SA10 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh
10 SA11 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh
10 SA12 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh
10 SA13 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh
10 SA14 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh
11 SA15 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh
11 SA16 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh
11 SA17 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh
11 SA18 001011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh
12 SA19 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh
12 SA20 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh
12 SA21 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh
12 SA22 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh
13 SA23 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh
13 SA24 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh
13 SA25 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh
13 SA26 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh
14 SA27 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh
14 SA28 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh
14 SA29 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh
14 SA30 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh
15 SA31 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh
15 SA32 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh
15 SA33 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh
15 SA34 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
16 SA35 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh
16 SA36 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh
16 SA37 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh
16 SA38 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh
MX29LV320MB SECTOR GROUP ARCHITECTURE
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MX29LV320MT/B
Sector Sector Sector Address Sector Size (x8) (x16)
Group A20-A12 (Kbytes/Kwords) Address Range Address Range
17 SA39 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh
17 SA40 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh
17 SA41 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh
17 SA42 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh
18 SA43 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh
18 SA44 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh
18 SA45 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh
18 SA46 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh
19 SA47 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh
19 SA48 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh
19 SA49 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh
19 SA50 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh
20 SA51 101100xxx 64/32 2C0000h-2CFFFFh 160000h-167FFFh
20 SA52 101101xxx 64/32 2D0000h-2DFFFFh 168000h-16FFFFh
20 SA53 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh
20 SA54 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh
21 SA55 110000xxx 64/32 300000h-30FFFFh 180000h-187FFFh
21 SA56 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh
21 SA57 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh
21 SA58 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh
22 SA59 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh
22 SA60 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh
22 SA61 110110xxx 64/32 360000h-36FFFFh 1B0000h-1B7FFFh
22 SA62 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh
23 SA63 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh
23 SA64 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh
23 SA65 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh
23 SA66 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh
24 SA67 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh
24 SA68 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh
24 SA69 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh
24 SA70 111111xxx 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh
No te:The address range is A20:A-1 in byte mode (BYTE#=VIL) o r A20:A0 in wo rd mo de (BYTE#=VIH)
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MX29LV320MT/B
Q8~Q15
Operation CE# OE# WE# RE- WP# ACC Address Q0~Q7 BYTE# BYTE#
SET# =VIH =VIL
Read L L H H X X AIN DOUT DOUT Q8-Q14=
High Z
Q15=A-1
Write (Program/Erase) L H L H (Note 3) X AIN (Note 4) (Note 4) Q8-Q14=
High Z
Q15=A-1
Accelerated Pro gram L H L H (No te 3) VHH AIN (Note 4) (Note 4) Q8-Q14=
High Z
Q15=A-1
Standby VCC±X X VCC±X H X High-Z High-Z High-Z
0.3V 0.3V
Output Disable L H H H X X X High-Z High-Z High-Z
Reset X X X L X X X High-Z High-Z High-Z
Secto r Group Protect L H L VID H X Secto r Addresses, (Note 4) X X
(No te 2) A6=L,A3=L, A2=L,
A1=H,A0=L
Chip unprotect L H L VID H X Secto r Addresses, (No te 4) X X
(Note 2) A6=H, A3=L, A2=L,
A1=H, A0=L
Temporary Sector X X X VID HX A
IN (Note 4) (Note 4) High-Z
Group Unprotect
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,
DOUT=Data OUT
Notes:
1. Addresses are Amax:A0 in wo rd mo de; Amax:A-1 in b yte mo de. Sector address are Amax:A15 in bo th mo des.
2. The secto r gro up protect and chip unpro tect functions may also be implemented via pro gramming equipment. See
the "Secto r Group Pro tection and Chip Unpro tect" section.
3. If WP#=VIL, the two o utermost bo o t secto rs remain pro tected. If WP#=VIH, the two o utermo st bo o t secto r pro tec-
tion depends o n whether they were last pro tected o r unprotect using the method described in "Secto r/ Sector Blo ck
Protection and Unprotect".
4. DIN or DOUT as required by co mmand sequence, Data# po lling o r secto r protect algo rithm (see Figure 15).
Table 1. BUS OPERATION (1)
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MX29LV320MT/B
Table 2. AUTOSELECT CODES (High Voltage Method)
A20 A14 A8 A5 A3 Q8 to Q15 Q7 to Q0
Description CE# OE# WE# to to A9 to A6 to to A1 A0 BYTE# BYTE#
A15 A10 A7 A4 A2 =VIH =VIL
Manufacturer ID L L H X X VID X L X L L L 00 X C2 h
Cycle 1 L L H 22 X 7Eh
Cycle 2 L L H X X VID X L X H H L 22 X 1Ah
Cycle 3 H H H 22 X 00(bottom boot)
01h(top boot)
Sector Protection L L H SA X VID X L X L H L X X 01h (protected),
Verification 00h (unprotected)
Secured Silicon
Sector Indicator 98h
Bit (Q7), WP# L L H X X VID X L X L H H X X (f acto ry lock ed),
protects to p two 18h
address sector (not factor y locked)
Secured Silicon
Sector 88h
Indicator Bit (Q7), (factor y locked),
WP# protects L L H X X VID X L X L H H X X
botto m two 08h
address sector (not factor y locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address , X = Don't care.
Device ID
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MX29LV320MT/B
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
co ntrol and selects the device . OE# is the o utput co ntro l
and gates arra y data to the o utput pins . WE# should re-
main at VIH.
The internal state machine is set for reading arra y data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No co mmand is
necessary in this mode to obtain array data. Standard
micro processor read cycles that assert valid address o n
the device address inputs produce valid data o n the de-
vice data outputs. The device remains enabled f or read
access until the co mmand register co ntents are altered.
PAGE MODE READ
The MX29LV320MT/B o ffers "fast page mo de read" func-
tion. This mode provides faster read access speed for
rando m lo cations within a page. The page size o f the de-
vice is 4 wo rds/8 bytes. The appropriate page is selected
by the higher address bits A0~A1(Word Mode)/A-
1~A1(Byte Mo de) This is an asynchro no us operatio n; the
micro processo r supplies the specific word lo cation.
The system performance could be enhanced by initiating
1 normal read and 3 fast page read (fo r w ord mo de A0-
A1) or 7 fast page read (for byte mode A-1~A1). When
CE# is deasserted and reasserted for a subsequent ac-
cess, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the "read-page ad-
dresses" constant and changing the "intra-read page"
addresses.
WRITING COMMANDS/COMMAND SE-
QUENCES
To program data to the device or erase sectors of memory ,
the system must drive WE# and CE# to VIL, and OE# to
VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table indicates the address
space that each sector occupies. A "sector address"
co nsists of the address bits required to uniquely select a
sector. The "Writing specific address and data commands
o r sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values o r
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, o r suspending/resuming the erase
operation.
After the system writes the Automatic Select co mmand
sequence, the de vice enters the Auto matic Select mode.
The system can then read A uto matic Select co des fro m
the internal register (which is separate fro m the memo ry
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Auto matic Select Mode and Au-
to matic Select Command Sequence section f or mo re in-
formation.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" sectio n contains timing specification table
and timing diagrams fo r write o perations.
WRITE BUFFER
Write Buffer Programming allows the system to write a
maximum o f 16 wo rds/32 b ytes in o ne pro gramming o p-
eratio n. This results in faster eff ective pro gramming time
than the standard programming algorithms. See "Write
Buffer" fo r mo re info rmatio n.
ACCELERATED PROGRAM OPERATION
The device offers accelerated pro gram operations through
the ACC function. This is one of two functions provided
by the ACC pin. This function is primarily intended to
allow faster manufacturing throughput at the facto ry.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass mo de,
temporarily unpro tects an y pro tected sectors, and uses
the higher vo ltage o n the pin to reduce the time required
for program operations. The system would use a two-cycle
pro gram co mmand sequence as required by the Unlo c k
Bypass mo de. Remo ving VHH fro m the ACC
pin must no t be at VHH fo r operatio ns other than acceler-
ated pro gramming, o r device damage may result.
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MX29LV320MT/B
STANDBY MODE
When using bo th pins o f CE# and RESET#, the de vice
enter CMOS Standby with bo th pins held at VCC ± 0.3V.
If CE# and RESET# are held at VIH, but not within the
range o f VCC ± 0.3V, the device will still be in the standby
mo de, but the standby current will be larger . During Auto
Algorithm operation, VCC active current (ICC2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either o f these standby mo des, befo re it is ready to read
data.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device en-
ergy co nsumption. The device auto matically enables this
mode when address remain stable fo r tACC+30ns. The
auto matic sleep mo de is independent o f the CE#, WE#,
and OE# co ntrol signals. Standard address access tim-
ings pro vide new data when addresses are changed. While
in sleep mode, output data is latched and always a vail-
able to the system. ICC4 in the DC Characteristics table
represents the auto matic sleep mo de current specifica-
tion.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
fro m the devices are disabled. This will cause the output
pins to be in a high impedance state.
RESET# OPERATION
The RESET# pin provides a hardware metho d of reset-
ting the device to reading array data. When the RESET#
pin is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write co m-
mands for the duration of the RESET# pulse. The device
also resets the internal state machine to reading array
data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
co mmand sequence, to ensure data integrity
Current is reduced for the duration o f the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS±0.3V, the standby current will be
greater.
The RESET# pin may be tied to system reset circuitry.
A system reset wo uld that also reset the Flash memo ry,
enabling the system to read the boot-up fir m ware from
the Flash memo ry .
If RESET# is asserted during a program o r erase opera-
tio n, the R Y/BY# pin remains a "0" (busy) until the inter-
nal reset o peratio n is co mplete, which requires a time o f
tREAD Y (during Embedded Algorithms). The system can
thus monitor R Y/BY# to determine whether the reset op-
eration is complete. If RESET# is asserted when a pro-
gram or erase operation is completed within a time of
tREAD Y (no t during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 3 f or the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29L V320MT/B features hardware sector group pro-
tectio n. This feature will disable bo th program and erase
operations for these sector group protected. In this de-
vice, a sector group consists of four adjacent sectors
which are pro tected o r unpro tected at the same time. To
activate this mo de, the programming equipment must fo rce
VID on address pin A9 and control pin OE#, (suggest
VID = 12V) A6 = VIL and CE# = VIL. (see Table 2) Pro-
gramming o f the pro tection circuitry begins on the falling
edge of the WE# pulse and is terminated on the rising
edge. Please refer to sector group pro tect algorithm and
waveform.
MX29LV320MT/B also pro vides ano ther metho d. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equip-
ment. This method uses standard microprocessor bus
cycle timing.
To verify pro gramming o f the protection circuitry, the pro-
gramming equipment must fo rce VID o n address pin A9
(with CE# and OE# at VIL and WE# at VIH). When A1=1,
it will produce a logical "1" co de at device o utput Q0 fo r a
pro tected sector. Otherwise the device will pro duce 00H
f o r the unpro tected secto r . In this mo de, the addresses ,
e xcept fo r A1, are do n't care . Address lo catio ns with A1
= VIL are reserved to read manufacturer and device codes.
(Read Silico n ID)
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MX29LV320MT/B
It is also possible to determine if the gro up is protected
in the system by writing a Read Silicon ID command.
P erfo rming a read o peration with A1=VIH, it will pro duce
a logical "1" at Q0 for the pro tected sector .
CHIP UNPROTECT OPERATION
The MX29LV320MT/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
co de. It is reco mmended to protect all secto rs before ac-
tivating chip unpro tect mo de.
To activate this mo de, the pro gramming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. (see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The unprotect
mechanism begins o n the falling edge o f the WE# pulse
and is terminated on the rising edge.
MX29LV320MT/B also provides ano ther metho d. Which
requires VID on the RESET# only. This method can be
implemented either in-system o r via programming equip-
ment. This method uses standard microprocessor bus
cycle timing.
It is also po ssib le to determine if the chip is unpro tect in
the system by writing the Read Silicon ID command.
P erfo rming a read o peration with A1=VIH, it will pro duce
00H at data o utputs (Q0-Q7) for an unprotect sector. It is
noted that all sectors are unprotected after the chip
unpro tect algo rithm is completed.
WRITE PROTECT (WP#)
The write protect functio n provides a hardware method to
pro tect bo ot secto rs without using VID.
If the system asserts VIL on the WP# pin, the device
disables program and er ase functio ns in the two "outer-
most" 8 Kbyte bo ot sectors independently of whether those
sectors were protected or unprotect using the method
described in Sector "Sector Group Protection and Chip
Unprotect". The two o utermo st 8 Kb yte bo ot secto rs are
the two sectors containing the lowest addresses in a
bottom-boot-configured device, or the two sectors con-
taining the highest addresses in a top-boot-configured
device.
If the system asser ts VIH on the WP# pin, the device
reverts to whether the two outermo st 8K Byte boo t sec-
tors were last set to be protected or unprotect. That is,
sector protection or unprotection for these two sectors
depends on whether they were last pro tected or unprotect
using the method described in "Sector/Sector Group Pro-
tectio n and Chip Unprotect".
No te that the WP# pin must no t be left floating o r unco n-
nected; inconsistent behavior o f the de vice ma y result.
TEMPORARY SECTOR GROUP UNPROTECT
OPERATION
This feature allows temporary unprotect of previo usly pro-
tected secto r to change data in-system. The Tempo rary
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID(11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as unprotect sector. Once VID is remove from the RE-
SET# pin, all the previously protected sectors are pro-
tected again.
SILICON ID READ OPERATION
Flash memories are intended fo r use in applications where
the lo cal CPU alters memo ry co ntents. As such, man u-
f acturer and device co des m ust be accessible while the
device resides in the target system. PROM program-
mers typically access signature co des by raising A9 to a
high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design prac-
tice.
MX29LV320MT/B pro vides hardware metho d to access
the silico n ID read operation. Which metho d requires VID
on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which
apply VIL on A0 pin, the device will output MXIC's manu-
facture code.. Which apply VIH o n A0 pin, the device will
o utput MX29L V320MT/B de vice code.
VERIFY SECTOR GROUP PROTECT STATUS
OPERATION
MX29LV320MT/B pro vides hardw are method f or secto r
group protect status verify. Which method requires VID
on A9 pin, VIH o n WE# and A1 pins, VIL o n CE#, OE#,
A6, and A0 pins, and secto r address on A16 to A20 pins.
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MX29LV320MT/B
Which the identified sector is protected, the device will
o utput 01H. Which the identified secto r is not pro tect, the
de vice will o utput 00H.
DATA PROTECTION
The MX29LV320MT/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transitio n. During power up the de vice auto matically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memor y contents only occurs after successful comple-
tion of specific command sequences. The device also
inco rpo rates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.
SECURED SILICON SECTOR
The MX29LV320MT/B features a OTP memor y region
where the system ma y access through a co mmand se-
quence to create a permanent part identification as so
called Electronic Serial Number (ESN) in the device.
Once this regio n is programmed, any further modification
o n the regio n is impossible. The secured silicon sector is
a 128 wo rds in length, and uses a Secured Silicon Secto r
Indicato r Bit (Q7) to indicate whether o r not the Secured
Silicon Sector is locked when shipped from the factory.
This bit is permanently set at the factory and canno t be
changed, which prevent duplication of a factor y locked
part. This ensures the security o f the ESN once the pro d-
uct is shipped to the field.
The MX29LV320MT/B of fers the device with Secured
Silico n Secto r either facto ry lo cked or custo mer lockable.
The factory-locked version is always protected when
shipped from the factory , and has the Secured Silicon
Sector Indicator Bit permanently set to a "1". The cus-
to mer-lo c kable v ersio n is shipped with the Secured Sili-
co n Sector unprotected, allowing customers to utilize that
secto r in any fo rm they prefer. The customer-lockable ver-
sion has the secured sector Indicator Bit permanently
set to a "0". Theref ore, the Secured Silicon Secto r Indi-
cator Bit prev ents customer , lockab le de vice fro m being
used to replace de vices that are f actory lo c k ed.
The system access the Secured Silicon Sector thro ugh
a command sequence (ref er to "Enter Secured Silicon/
Exit Secured Silico n Secto r co mmand Sequence). After
the system has written the Enter Secured Silicon Sector
command sequence, it may read the Secured Silicon
Sector by using the address nor mally occupied by the
first secto r SA0. Once entry the Secured Silico n Secto r
the o peration of bo ot secto rs is disabled but the o peration
of main sectors is as nor mally. This mode of operation
continues until the system issues the Exit Secured Sili-
con Sector command sequence, o r until power is remo ved
from the device. On power-up, or following a hardware
reset, the de vice re v erts to sending command to secto r
SA0.
Secured Silicon ESN factory Customer
Sector address locked lockable
range
000000h-000007h ESN Determined by
000008h-00007Fh Unavailable Customer
FACTORY LOCKED:Secured Silicon Sector
Programmed and Protected At the Factory
In device with an ESN, the Secured Silicon Sector is
protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any
wa y . A factory locked device has an 8-wo rd random ESN
at address 000000h-000007h.
CUSTOMER LOCKABLE:Secured Silicon Sec-
tor NOT Programmed or Protected At the Fac-
tory
As an alternative to the factor y-locked version, the de-
vice may be ordered such that the customer may pro-
gr am and protect the 128-word Secured Silicon Sector.
Pro gramming and pro tecting the Secured Silicon Sector
must be used with caution since, once protected, there
is no procedure available for unprotected the Secured
Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any way .
The Secured Silicon Sector area can be protected using
o ne of the fo llowing pro cedures:
Write the three-cycle Enter Secured Silicon Sector Re-
gio n command sequence, and then f ollow the in-system
sector protect algor ithm as shown in Figure 15, except
that RESET# may be at either VIH o r VID . This allows in-
16
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MX29LV320MT/B
system protection o f the Secured Silicon Secto r without
raising any device pin to a high vo ltage. Note that method
is o nly applicab le to the Secured Silico n Secto r.
Write the three-cycle Enter Secured Silicon Sector Re-
gio n co mmand sequence, and then alternate metho d o f
secto r pro tection described in the :Secto r Group Protec-
tio n and Unpro tect" section.
Once the Secured Silico n Sector is programmed, lo cked
and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to retur n to
reading and writing the remainder of the array .
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and all
internal pro gram/erase circuits are disabled, and the de-
vice resets. Subsequent writes are igno red until VCC is
greater than VLKO. The system must pro vide the proper
signals to the control pins to prev ent unintentional write
when VCC is greater than VLK O.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL, CE#
= VIH or WE# = VIH. To initiate a write cycle CE# and
WE# must be a logical zero while OE# is a lo gical one.
POWER-UP SEQUENCE
The MX29LV320MT/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful co mpletio n of the predefined command
sequences.
POWER-UP WRITE INHIBIT
If WE#=CE#=VIL and OE#=VIH during power up, the
de vice do es no t accept co mmands o n the rising edge o f
WE#. The internal state machine is automatically reset
to the read mo de on power-up.
POWER SUPPLY DE COUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND .
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MX29LV320MT/B
TABLE 3. MX29LV320MT/B COMMAND DEFINITIONS
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 R A R D
Reset (Note 6) 1 XXX F0
Automatic Select (Note 7)
Manufacturer ID Word 4 555 AA 2AA 55 555 90 X00 C2H
Byte 4 AAA AA 555 55 AAA 90 X00 C2H
Device ID Word 4 555 AA 2AA 55 555 90 X01 227EH X0E 221A X0F 2200/
(Note 8) 2201
Byte 4 AAA AA 555 55 AAA 90 X02 7E X1C 1A X1E 00/01
Secured Sector Fact- Word 4 555 AA 2AA 55 555 90 X03 see
ory Protect (Note 9) Byte 4 AAA AA 555 55 AAA 90 X06 Note 9
Sector Group Protect Word 4 555 AA 2AA 55 555 90 (SA)X02 XX00/
Verify (Note 10) Byte 4 AAA AA 555 55 AAA 90 (SA)X04 XX01
Enter Secured Silicon Word 3 555 AA 2AA 55 555 88
Sector Byte 3 AAA AA 555 55 AAA 88
Exit Secured Silicon Word 4 555 AA 2AA 55 555 90 XXX 00
Sector Byte 4 AAA AA 555 55 AAA 90 XXX 00
Program Word 4 555 AA 2AA 55 555 A0 PA PD
Byte 4 AAA AA 555 55 AAA A0 PA PD
Write to Buffer (Note 11) Word 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD
Byte 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash Word 1 SA 29
Byte 1 SA 29
Write to Buffer Abort Word 3 555 AA 2AA 55 555 F0
Reset (Note 12) Byte 3 AAA AA 5 5 5 5 5 AAA F0
Chip Erase Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase Word 6 5 55 AA 2A A 55 5 55 8 0 5 5 5 AA 2A A 5 5 SA 3 0
Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (Note 13) 1 XXX B0
Program/Erase Resume (Note 14) 1 XXX 30
CFI Query (Note 15) Word 1 5 5 98
Byte 1 AA 98
SOFTWARE COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values o r writing them
in the improper sequence will reset the device to the
read mo de . Tab le 3 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) co mmands are valid o nly while the
Sector Erase operation is in pro gress . Either of the two
reset command sequences will reset the device (when
applicable).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data are latched on
rising edge of WE# or CE#, whichever happens first.
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Notes:
1. See Table 1 fo r descriptio ns o f bus o perations.
2. All values are in hexadecimal.
3. Except when reading arra y o r auto matic select data, all bus cycles are write o peratio n.
4. Address bits are don't care f or unlo ck and command cycles, e xcept when PA or SA is required.
5. No unlo c k o r co mmand cycles required when device is in read mo de .
6. The Reset command is required to return to the read mo de when the device is in the auto matic select mo de o r if
Q5 go es high.
7. The f ourth cycle o f the automatic select co mmand sequence is a read cycle .
8. The de vice ID must be read in three cycles . The data is 01h f or to p bo o t and 00h f or bo ttom bo ot.
9. If WP# protects the top two address sectors, the data is 98h f or factory locked and 18h fo r not factory locked. If
WP# protects the botto m tw o address secto rs , the data is 88h f or facto ry lo c k ed and 08h for no t f actor lo c k ed.
10 . The data is 00h fo r an unprotected secto r/secto r block and 01h f o r a pro tected secto r/secto r blo c k.
1 1 . The to tal number o f cycles in the co mmand sequence is determined by the number of wo rds written to the write
buff er . The maximum number o f cycles in the co mmand sequence is 21(Wo rd Mo de) / 37(Byte Mo de).
1 2. Co mmand sequence resets device fo r next command after abo rted write-to-buffer o peration.
13. The system may read and pro gram functio ns in no n-erasing sectors, or enter the auto matic select mode, when in
the erase Suspend mo de. The Erase Suspend co mmand is valid only during a secto r erase o peration.
14 . The Erase Resume co mmand is valid o nly during the Erase Suspend mo de.
15 . Co mmand is v alid when de vice is ready to read arra y data or when de vice is in auto matic select mode.
Legend:
X=Do n't care
RA=Address o f the memo ry locatio n to be read.
RD=Data read fro m locatio n RA during read operation.
PA=Address of the memory locatio n to be programmed.
Addresses are latched o n the falling edge o f the WE# o r CE# pulse, whichever happen later .
DDI=Data o f device identifier
C2H for manufacture code
PD=Data to be pro grammed at lo cation PA. Data is latched o n the rising edge o f WE# o r CE# pulse.
SA=Address o f the secto r to be erase o r verified (in auto select mo de).
Address bits A20-A12 uniquely select any sector .
WBL=Write Buffer Locatio n. Address m ust be within the same write buff er page as PA.
WC=Wo rd Count. Number of write buffer lo cations to lo ad minus 1.
BC=Byte Co unt. Number o f write buff er lo catio ns to lo ad min us 1.
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MX29LV320MT/B
READING ARRAY DATA
The de vice is auto matically set to reading array data af-
ter device power-up. No commands are required to re-
trieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algo rithm.
After the de vice accepts an Erase Suspend co mmand,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase Sus-
pend mo de, the system may once again read array data
with the same exception. See Erase Suspend/Erase
Resume Co mmands f or mo re inf o rmatio n on this mo de .
The system must issue the reset command to re-en-
able the device fo r reading array data if Q5 go es high, o r
while in the auto matic select mode. See the "Reset Com-
mand" section, ne xt.
RESET COMMAND
Writing the reset co mmand to the de vice resets the de-
vice to reading array data. Address bits are don't care f or
this co mmand.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however , the device igno res
reset co mmands until the o peratio n is co mplete.
The reset command may be written between the se-
quence cycles in a pro gram co mmand sequence befo re
programming begins. This resets the device to reading
array data (also applies to programming in Erase Sus-
pend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the se-
quence cycles in an SILICON ID READ command se-
quence. Once in the SILICON ID READ mo de, the reset
co mmand must be written to return to reading array data
(also applies to SILICON ID READ during Erase Sus-
pend).
If Q5 go es high during a program o r erase operatio n, writ-
ing the reset co mmand returns the device to reading
array data (also applies during Erase Suspend).
SILICON ID READ COMMAND SEQUENCE
The SILICON ID READ co mmand sequence allo ws the
host system to access the manufacturer and devices
codes, and determine whether or no t a sector is protected.
Table 2 shows the address and data requirements.
This method is an alter native to that shown in Table 1,
which is intended f o r PROM pro grammers and requires
VID on address bit A9.
The SILICON ID READ co mmand sequence is initiated
by wr iting two unlock cycles, followed by the SILICON
ID READ command. The device then enters the SILI-
CON ID READ mode, and the system may read at any
address any number of times, without initiating another
co mmand sequence. A read cycle at address XX00h re-
trieves the manuf acturer code. A read cycle at address
XX01h returns the device co de. A read cycle co ntaining
a sector address (SA) and the address 02h returns 01h if
that secto r is protected, o r 00h if it is unprotected. Ref er
to T able for valid sector addresses.
The system must write the reset command to exit the
auto matic select mode and return to reading array data.
BYTE/WORD PROGRAM COMMAND SE-
QUENCE
The command sequence requires fo ur bus cycles, and is
initiated by writing two unlock write cycles, followed by
the program set-up co mmand. The program address and
data are written next, which in turn initiate the Embed-
ded Program algorithm. The system is not required to
pro vide further co ntro ls o r timings. The device auto mati-
cally generates the pro gram pulses and verifies the pro-
grammed cell margin. Table 3 shows the address and
data requirements for the byte program command se-
quence.
When the Embedded Program algo rithm is complete, the
device then returns to reading array data and addresses
are no lo nger latched. The system can determine the sta-
tus of the program operatio n by using Q7, Q6, or RY/BY#.
See "Write Operation Status" for information on these
status bits.
Any co mmands written to the device during the Embed-
ded Program Algorithm are igno red. Note that a hardware
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MX29LV320MT/B
reset immediately terminates the programming o peration.
The Byte/Wo rd Program command sequence should be
reinitiated o nce the device has reset to reading array data,
to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the op-
eration and set Q5 to "1", or cause the Data# Polling
algo rithm to indicate the o peratio n was successful. How-
ever, a succeeding read will show that the data is still
"0". Only erase o perations can co nvert a "0" to a "1".
Write Buffer Programming
Write Buffer Programming allows the system write to a
maximum o f 16 wo rds/32 bytes in o ne pro gramming o p-
eratio n. This results in faster effective pro gramming time
than the standard programming algorithms. The Write
Buff er Programming command sequence is initiated by
first writing two unlo c k cycles. This is f o llow ed by a third
write cycle containing the Write Buffer Load command
written at the Secto r Address in which pro gramming will
o ccur. The fo urth cycle writes the sector address and the
number o f wo rd locations, minus o ne, to be pro grammed.
For example, if the system will program 6 unique ad-
dress lo cations, then 05h sho uld be written to the device.
This tells the device how many write buffer addresses
will be loaded with data and therefo re when to expect the
Pro gram Buffer to Flash co mmand. The number o f lo ca-
tio ns to program cannot exceed the size of the write buffer
o r the operatio n will abort.
The fifth cycle writes the first address lo cation and data
to be pro grammed. The write-buffer-page is selected by
address bits AMAX-4. All subsequent address/data pairs
must f all within the selected-write-buffer-page. The sys-
tem then writes the remaining address/data pairs into
the write buffer . Write b uffer lo cations may be loaded in
any order.
The write-buff er-page address must be the same f or all
address/data pairs loaded into the write buffer. (This
means Write Buff er Programming cannot be perf ormed
acro ss multiple write-buffer pages. This also means that
Write Buffer Programming cannot be performed across
multiple secto rs. If the system attempts to load pro gram-
ming data o utside of the selected write-buff er page, the
o peration will abo rt.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented fo r every data load operation. The ho st sys-
tem must theref o re acco unt f o r lo ading a write-buff er lo-
catio n more than once. The counter decrements for each
data lo ad o peratio n, not fo r each unique write-buff er-ad-
dress location. Note also that if an address location is
loaded more than once into the buffer, the final data loaded
fo r that address will be pro grammed.
Once the specified number o f write buff er locatio ns have
been loaded, the system must then write the Program
Buffer to Flash command at the sector address. Any o ther
address and data combination abor ts the Write Buffer
Programming o peration. The device then begins program-
ming. Data polling should be used while monitoring the
last address lo cation loaded into the write buff er. Q7, Q6,
Q5, and Q1 should be monitored to determine the device
status during Write Buffer Pro gramming.
The write-buffer programming operation can be suspended
using the standard pro gram suspend/resume commands.
Upon successful completion of the Write Buffer Program-
ming operation, the device is ready to execute the next
command.
The Write Buffer Programming Sequence can be aborted
in the f ollowing w a ys:
•Lo ad a value that is greater than the page buffer size
during the Number of Lo cations to Pro gram step.
•Write to an address in a secto r different than the o ne
specified during the Write-Buffer-Load command.
•Write an Address/Data pair to a different write-buffer-
page than the one selected by the Starting Address
during the write buffer data loading stage of the opera-
tion.
•Write data other than the Confirm Command after the
specified number of data load cycles .
The abo rt conditio n is indicated b y Q1 = 1, Q7 = D ATA#
(for the last address location loaded), Q6 = toggle, and
Q5=0. A Write-to-Buffer-Abort Reset command sequence
must be written to reset the device fo r the next operation.
Note that the full 3-cycle Write-to-Buffer-Abo rt Reset com-
mand sequence is required when using Write-Buffer-Pro-
gr amming features in Unlo c k Bypass mo de.
Program Suspend/Program Resume Command
Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer pro-
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MX29LV320MT/B
gramming operation so that data can be read from any
non-suspended sector. When the Pro gram Suspend co m-
mand is written during a pro g ramming process, the de-
vice halts the program operation within 15us maximum
(5 us typical) and updates the status bits. Addresses are
not required when writing the Program Suspend command.
After the programming operation has been suspended,
the system can read array data from any non-suspended
secto r. The Program Suspend co mmand may also be is-
sued during a pro gramming operatio n while an erase is
suspended. In this case, data ma y be read from any ad-
dresses no t in Erase Suspend o r Pro gram Suspend. If a
read is needed from the Secured Silicon Sector area (One-
time Pro gram area), then user must use the proper com-
mand sequences to enter and e xit this regio n.
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device e xits the auto select mode,
the device reverts to the Program Suspend mo de, and is
ready for another valid operation. See Autoselect Com-
mand Sequence for more information.
After the Pro gram Resume co mmand is written, the de-
vice reverts to programming. The system can determine
the status of the program operation using the Q7 o r Q6
status bits, just as in the standard program operation.
See Write Operation Status fo r more information.
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation . There are two
"unlock" write cycles. These are f ollowed b y writing the
"set-up" co mmand 80H. Two mo re "unlock" write cycles
are then followed by the chip erase co mmand 10H, or the
secto r erase co mmand 30H.
The MX29LV320MT/B contains a Silicon-ID-Read opera-
tio n to supplement traditional PROM pro gramming meth-
o dolo gy . The operatio n is initiated by writing the read sili-
co n ID co mmand sequence into the co mmand register .
Following the command write, a read cycle with
A1=VIL,A0=VIL retriev es the manufacturer co de of C2H.
AUTOMATIC CHIP/SECTOR ERASE COM-
MAND
The device does not require the system to preprogram
prio r to erase. The A uto matic Er ase algo rithm auto mati-
cally pre-program and v erifies the entire memo ry for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls o r timings during
these operations. Table 3 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Auto matic
Erase algo rithm are ignored. Note that a hardware reset
during the chip erase o peratio n immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
arra y data, to ensure data integrity.
The system can determine the status o f the erase opera-
tion by using Q7, Q6, Q2, o r RY/BY#. See "Write Opera-
tion Status" for information on these status bits. When
the Automatic Erase algor ithm is complete, the device
returns to reading array data and addresses are no lo nger
latched.
Figure 10 illustrates the algo rithm fo r the erase o peration.
See the Erase/Pro g ram Operatio ns tab les in "A C Char-
acteristics" for parameters, and to Figure 9 for timing
diagrams.
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MX29LV320MT/B
SECTOR ERASE COMMANDS
The Automatic Secto r Erase do es not require the device
to be entirely pre-pro grammed prior to executing the Au-
tomatic Set-up Sector Erase command and Automatic
Secto r Er ase co mmand. Upo n e x ecuting the A uto matic
Sector Erase co mmand, the device will automatically pro-
gram and verify the secto r(s) memory fo r an all-zero data
pattern. The system is no t required to provide an y co n-
tro l or timing during these operatio ns.
When the secto r(s) is automatically verified to co ntain an
all-zero pattern, a self-timed secto r erase and verify be-
gin. The erase and verify operations are co mplete when
the data on Q7 is "1" and the data on Q6 sto ps toggling
for two consecutive read cycles, at which time the de-
vice returns to the Read mode. The system is not re-
quired to pro vide any control or timing during these opera-
tions.
When using the Auto matic Secto r Erase algo rithm, no te
that the erase auto matically terminates when adequate
erase margin has been achieved for the memory array
(no erase verificatio n command is required). Sector erase
is a six-bus cycle operation. There are two "unlo ck" write
cycles. These are followed by writing the set-up com-
mand 80H. Two more "unlo ck" write cycles are then f o l-
lowed by the sector erase command 30H. The sector
address is latched on the falling edge of WE# or CE#,
whiche ver happens later , while the co mmand (data) is
latched on the rising edge of WE# or CE#, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE# or
CE#, whichever happens later . Each successiv e sector
load cycle started by the falling edge of WE# or CE#,
whichever happens later must begin within 50us from
the rising edge of the preceding WE# o r CE#, whichever
happens first. Otherwise, the loading per iod ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the secto r erase timer windo w is still open,
see section Q3, Sector Erase Timer.) Any command other
than Secto r Erase(30H) o r Erase Suspend(B0H) during
the time-o ut perio d resets the device to read mo de.
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Auto matic Sector Erase operation, and
therefore will only be responded during Auto matic Secto r
Erase o peratio n. When the Erase Suspend co mmand is
issued during the secto r erase operatio n, the de vice re-
quires a maximum 20us to suspend the sector erase
operation. However , When the Erase Suspend co mmand
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex-
ecuted, the co mmand register will initiate erase suspend
mo de. The state machine will return to read mo de auto-
matically after suspend is ready. At this time , state ma-
chine only allows the co mmand register to respond to the
Erase Resume , program data to, or read data from any
secto r no t selected f o r erasure.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard pro gram operation. After an erase-suspend pro-
gram operatio n is co mplete , the system can o nce again
read array data within non-suspended blo cks.
ERASE RESUME
This co mmand will cause the command register to clear
the suspend state and return back to Secto r Erase mode
b ut only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
o ther conditions. Another Erase Suspend co mmand can
be written after the chip has resumed erasing.
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MX29LV320MT/B
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description Address h Address h Data h
(x16) (x8)
Query-unique ASCII string "QRY" 1 0 20 0051
11 22 0052
12 24 0059
Primary vendor command set and control interface ID code 1 3 2 6 0002
14 28 0000
Address for primary algorithm extended query table 1 5 2A 0040
16 2C 0000
Alternate vendor command set and control interface ID code (none) 17 2E 0000
18 30 0000
Address for secondary algorithm extended query table (none) 19 3 2 0000
1A 34 0000
Table 4-2. CFI Mode: System Interface Data Values
Description Address h Address h Data h
(x16) (x8)
VCC supply, minimum (2.7V) 1B 3 6 0027
VCC supply, maximum (3.6V) 1 C 3 8 0036
VPP supply, minimum (none) 1 D 3A 0000
VPP supply, maximum (none) 1E 3 C 0000
Typical timeout for single word/byte write (2N us) 1F 3E 0007
Typical timeout for maximum size buffer write (2N us) 2 0 4 0 0007
Typical timeout for individual block erase (2N ms) 2 1 42 000A
Typical timeout for full chip erase (2N ms) 2 2 4 4 0000
Maximum timeout for single word/byte write times (2N X Typ) 23 4 6 0001
Maximum timeout for maximum size buffer write times (2N X Typ) 24 4 8 0005
Maximum timeout for individual block erase times (2N X Typ) 25 4A 0004
Maximum timeout for full chip erase times (not supported) 2 6 4C 0000
QUERY COMMAND AND COMMON FLASH IN-
TERFACE (CFI) MODE
MX29L V320MT/B is capable of operating in the CFI mo de.
This mode all the host system to determine the manu-
facturer of the device such as operating parameters and
co nfiguration. Two co mmands are required in CFI mo de.
Quer y command of CFI mode is placed first, then the
Reset co mmand exits CFI mo de. These are described in
Table 4.
The single cycle Query co mmand is valid o nly when the
device is in the Read mode, including Erase Suspend,
Standby mo de, and Read ID mo de; however, it is ignored
otherwise.
The Reset command exits fro m the CFI mode to the Read
mode, or Erase Suspend mode, or read ID mode. The
command is valid only when the device is in the CFI
mode.
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MX29LV320MT/B
Description Address h Address h Data h
(x16) (x8)
Device size (2n bytes) 27 4E 0016
Flash device interface code (02=asynchronous x8/x16) 2 8 5 0 0002
29 52 0000
Maximum number of bytes in multi-byte write = 2n2A 54 0005
2B 56 0000
Number of erase block regions 2 C 5 8 0002
Erase block region 1 information 2 D 5A 0007
[2E,2D] = # of blocks in region -1 2E 5C 0000
[30, 2F] = size in multiples of 256-bytes 2F 5E 0020
30 60 0000
31 62 003E
Erase Block Region 2 Information (refer to CFI publication 100) 3 2 6 4 0000
33 66 0000
34 68 0001
35 6A 0000
Erase Block Region 3 Information (refer to CFI publication 100) 3 6 6 C 0000
37 6E 0000
38 70 0000
39 72 0000
Erase Block Region 4 Information (refer to CFI publication 100) 3A 7 4 0000
3B 76 0000
3C 78 0000
Table 4-3. CFI Mode: Device Geometry Data Values
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MX29LV320MT/B
Description Address h Address h Data h
(x16) (x8)
Query-unique ASCII string "PRI" 4 0 80 0050
41 82 0052
42 84 0049
Major version number, ASCII 4 3 86 0031
Minor version number, ASCII 4 4 88 0033
Address sensitive unlock (0=required, 1= not required) 4 5 8A 0000
Erase suspend (2= to read and write) 4 6 8 C 0002
Sector protect (N= # of sectors/group) 4 7 8E 0001
Temporary sector unprotect (1=supported) 48 90 0001
Sector protect/unprotect scheme 49 92 0004
Simultaneous R/W operation (0=not supported) 4A 94 0000
Burst mode type (0=not supported) 4B 9 6 0000
Page mode type (1=4 word page) 4 C 98 0001
ACC (Acceleration) Supply Minimum 4D 9A 00B5
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
ACC (Acceleration) Supply Maximum 4E 9C 00C5
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
Top/Bottom Boot Sector Flag 4F 9E 0002/
02h=Bottom Boot Device, 03h=Top Boot Device 0003
Program Suspend 50 A0 0001
00h=Not Supported, 01h=Supported
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
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Table 5. Write Operation Status
WRITE OPERATION STATUS
The device provides several bits to determine the status
of a write operation: Q2, Q3, Q5, Q6, Q7, and R Y/BY#.
Table 5 and the fo llowing subsectio ns describe the func-
tions of these bits. Q7, RY/BY#, and Q6 each offer a
Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#
Byte/Wo rd Pro gram in Auto Program Algo rithm Q7# To ggle 0 N/A No 0 0
Toggle
Auto Erase Algo rithm 0 To ggle 0 1 Toggle N/A 0
Erase Suspend Read 1 N o 0 N/A To ggle N/A 1
Erase (Erase Suspended Secto r) To ggle
Suspended Erase Suspend Read Data Data Data Data Data Data 1
Mo de (No n-Erase Suspended Sector)
Erase Suspend Pro gram Q7# To ggle 0 N/A N/A N/A 0
Program-Suspended Read Invalid (not allowed) 1
Program (Program-Suspended Sector)
Suspend Program-Suspended Read Data 1
(Non-Program-Suspended Sector)
Write-to-Buffer Busy Q7# Toggle 0 N/A N/A 0 0
Abort Q7# Toggle 0 N/A N/A 1 0
Notes:
1. Q5 s witches to "1" when an W ord/Byte Pro gram, Erase , or Write-to-Buffer operatio n has e xceeded the maximum
timing limits. Refer to the section o n Q5 f o r mo re inf ormatio n.
2. Q7 and Q2 require a valid address when reading status info rmation. Refer to the appro priate subsection for further
details.
3. The Data# Po lling algorithm should be used to mo nito r the last loaded write-buffer address lo cation.
4. Q1 s witches to "1" when the device has abo rted the write-to-buff er o peratio n.
metho d f o r determining whether a pro gram o r er ase o p-
eration is complete or in progress. These three bits are
discussed first.
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MX29LV320MT/B
Q7: Data# Polling
The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend. Data#
P olling is valid after the rising edge o f the final WE# pulse
in the pro gram o r erase co mmand sequence.
During the Auto matic Pro gram algo rithm, the device o ut-
puts o n Q7 the complement of the datum programmed to
Q7. This Q7 status also applies to progr amming during
Erase Suspend. When the Auto matic Pro gram algo rithm
is co mplete , the de vice o utputs the datum pro g rammed
to Q7. The system must pro vide the program address to
read valid status info rmation on Q7. If a program address
falls within a protected sector, Data# Polling on Q7 is
active f o r appro ximately 1 us, then the device returns to
reading array data.
During the Auto matic Erase algorithm, Data# Polling pro-
duces a "0" o n Q7. When the Auto matic Erase algorithm
is complete, or if the device enters the Erase Suspend
mo de, Data# Polling produces a "1" o n Q7. This is analo-
go us to the complement/true datum output described for
the Automatic Program algorithm: the erase function
changes all the bits in a sector to "1" prior to this, the
device outputs the "complement," or "0". The system
must provide an address within any of the sectors se-
lected fo r erasure to read valid status info rmation on Q7.
After an erase command sequence is written, if all sec-
to rs selected f o r erasing are pro tected, Data# P olling o n
Q7 is active for approximately 100 us, then the device
returns to reading arra y data. If not all selected secto rs
are pro tected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are pro tected.
When the system detects Q7 has changed from the
co mplement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output Enable
(OE#) is asserted low.
Q6:Toggle BIT I
Toggle Bit I o n Q6 indicates whether an Automatic Pro-
gram or Erase algor ithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge o f the final WE# o r CE#, whiche ver
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.
During an Auto matic Pro gram o r Erase algo rithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
co ntro l the read cycles. When the operatio n is co mplete,
Q6 sto ps to ggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles for
100us and returns to reading array data. If not all se-
lected sectors are pro tected, the A utomatic Erase algo-
rithm erases the unprotected sectors, and ignores the
selected secto rs that are pro tected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing o r is erase suspended.
When the device is actively erasing (that is, the Auto-
matic Erase algo rithm is in progress), Q6 to ggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to de-
termine which secto rs are erasing o r erase-suspended.
Alternatively, the system can use Q7.
If a program address falls within a pro tected sector , Q6
toggles fo r approximately 2us after the pro gram command
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program mo de,
and sto ps toggling once the Automatic Program algo rithm
is complete.
Table 5 shows the outputs for To ggle Bit I on Q6.
Q2:Toggle Bit II
The "To ggle Bit II" o n Q2, when used with Q6, indicates
whether a par ticular sector is actively erasing (that is,
the Auto matic Erase algo rithm is in process), o r whether
that sector is erase-suspended. To ggle Bit II is v alid af-
ter the rising edge of the final WE# or CE#, whichever
happens first pulse in the co mmand sequence.
Q2 toggles when the system reads at addresses within
tho se secto rs that have been selected fo r erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 canno t distinguish whether the secto r is
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MX29LV320MT/B
actively erasing o r is erase-suspended. Q6, by co mpari-
so n, indicates whether the device is actively er asing, o r
is in Erase Suspend, but cannot distinguish which sec-
to rs are selected fo r er asure. Thus , both status bits are
required for sectors and mo de info rmation. Refer to T able
5 to co mpare o utputs f o r Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenev er the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is to ggling. Typically , the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the to ggle bit is no t to ggling, the device has co m-
pleted the pro gr am o r erase o per atio n. The system can
read arra y data o n Q7-Q0 on the fo llowing read cycle.
However, if after the initial two read cycles, the system
determines that the to ggle bit is still to ggling, the system
also should note whether the value o f Q5 is high (see the
section on Q5). If it is, the system should then deter-
mine again whether the toggle bit is toggling, since the
toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully co mpleted the program o r erase opera-
tio n. If it is still to ggling, the de vice did not co mplete the
operation successfully, and the system must write the
reset co mmand to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is to ggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 thro ugh successive read cycles, determining the sta-
tus as described in the previo us paragraph. Alternatively ,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the op-
eration.
Q5:Program/Erase Timing
Q5 will indicate if the program o r erase time has exceeded
the specified limits (internal pulse count). Under these
co nditio ns Q5 will pro duce a "1". This time-o ut conditio n
indicates that the program or erase cycle was not suc-
cessfully completed. Data# Polling and Toggle Bit are
the o nly operating functio ns o f the device under this co n-
dition.
If this time-out conditio n occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. Howe ver , other sectors are still func-
tional and may be used f or the program o r er ase opera-
tio n. The device must be reset to use o ther sectors. Write
the Reset command sequence to the device, and then
execute pro gram o r erase co mmand sequence . This al-
lows the system to co ntin ue to use the o ther active sec-
tors in the device.
If this time-out condition occurs during the chip erase
o peration, it specifies that the entire chip is bad or combi-
natio n of secto rs are bad.
If this time-o ut condition occurs during the byte/wo rd pro-
gramming operation, it specifies that the entire sector
containing that byte is bad and this sector may not be
reused, (o ther sectors are still functio nal and can be re-
used).
The time-o ut co nditio n ma y also appear if a user tries to
pro gram a non blank location without erasing. In this case
the de vice locks o ut and ne ver co mpletes the Auto matic
Algorithm operation. Hence, the system never reads a
v alid data o n Q7 bit and Q6 ne v er sto ps toggling. Once
the Device has exceeded timing limits, the Q5 bit will
indicate a "1". Please note that this is not a de vice fail-
ure co nditio n since the de vice w as inco rrectly used.
The Q5 f ailure condition may appear if the system tries
to program a to a "1" location that is previously pro-
grammed to "0". Only an erase o per atio n can change a
"0" back to a "1". Under this condition, the device halts
the o peratio n, and when the operatio n has exceeded the
timing limits, Q5 produces a "1".
Q3:Sector Erase Timer
After the co mpletio n o f the initial secto r erase co mmand
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is co mplete. Data# P o lling
and T o ggle Bit are valid after the initial secto r erase com-
mand sequence.
If Data# Polling o r the To ggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the inter nally controlled erase
cycle has begun; attempts to write subsequent commands
29
P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
to the de vice will be ignored until the erase operation is
co mpleted as indicated by Data# P o lling o r To ggle Bit. If
Q3 is low ("0"), the device will accept additional sector
erase co mmands. To insure the co mmand has been ac-
cepted, the system software should check the status of
Q3 prio r to and f o llowing each subsequent sector erase
co mmand. If Q3 w ere high o n the seco nd status check,
the co mmand ma y no t hav e been accepted.
If the time between additio nal erase co mmands from the
system can be less than 50us, the system need not to
mo nitor Q3.
Q1: Write-to-Buffer Abort
Q1 indicates whether a Write-to-Buffer operation was
abo rted. Under these co nditions Q1 pro duces a "1". The
system must issue the Write-to-Buffer-Abo rt-Reset com-
mand sequence to return the device to reading array data.
See Write Buffer section fo r more details.
RY/BY#:READY/BUSY OUTPUT
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge o f the final WE# pulse in the co mmand sequence.
Since RY/BY# is an o pen-dr ain o utput, se v eral RY/BY#
pins can be tied to gether in parallel with a pull-up resistor
to VCC .
If the o utput is lo w (Busy), the device is activ ely erasing
or programming. (This includes programming in the Erase
Suspend mo de.) If the o utput is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mo de), o r is in the standby mode.
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ABSOLUTE MAXIMUM RATINGS
Storage T emperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient T emperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
V o ltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Sho rt Circuit Current (No te 3) . . . . . . 200 mA
Notes:
1. Minim um DC v oltage o n input or I/O pins is -0.5 V.
During vo ltage transitio ns, input o r I/O pins may o ver-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During vo ltage transitio ns, input o r I/O pins may o ver-
sho o t to VCC +2.0 V fo r periods up to 20ns.
2. Minimum DC input voltage on pins A9, OE#, and
RESET# is -0.5 V. During vo ltage transitio ns, A9, OE#,
and RESET# may o versho o t VSS to -2.0 V fo r periods
o f up to 20 ns. Maximum DC input vo ltage o n pin A9 is
+12.5 V which may oversho o t to 14.0 V fo r perio ds up
to 20 ns.
3. No more than o ne output may be sho rted to gro und at
a time. Duration of the short circuit should not be greater
than o ne second.
Stresses abo v e tho se listed under "Abso lute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these o r any other conditio ns abo ve tho se indi-
cated in the o perational sections of this data sheet is not
implied. Exposure of the device to absolute maximum
rating co nditio ns fo r extended periods may affect de vice
reliability.
OPERATING RATINGS
Commercial (C) Devices
Ambient Temperature (TA ) . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA ) . . . . . . . . . . . -40°C to +85°C
VCC Supply Voltages
VCC for full voltage range. . . . . .. . . . . . +2.7 V to 3.6 V
VCC for regulated voltage range. . . . . . . +3.0 V to 3.6 V
Operating ranges define tho se limits between which the
functio nality o f the de vice is guaranteed.
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MX29LV320MT/B
Notes:
1. On the WP#/A CC pin only, the maximum input load current when WP# = VIL is ± 5.0uA.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC =
3.0V.
4 . ICC active while Embedded Erase o r Embedded Pro gram is in pro gress.
5. A uto matic sleep mo de enables the lo w power mo de when addresses remain stab le fo r tA CC + 30 ns .
6. No t 100% tested.
7 . A9=12.5V when TA=0°C to 85°C , A9=12V when when TA=-40°C to 0°C.
DC CHARACTERISTICS
TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R)
Para-
meter Description T est Conditions Min. Typ. Max. Unit
I LI Input Lo ad Current (Note 1) VIN = VSS to VCC , ±1.0 uA
VCC = VCC max
I LIT A9 Input Leakage Current VCC=VCC max; A9 = 12.5V 3 5 uA
I LO Output Leakage Current VOUT = VSS to VCC , ±1.0 uA
VCC= VCC max
ICC1 VCC Initial Read Current CE#= VIL, 10 MHz 3 5 5 0 mA
(No tes 2,3) OE# = VIH 5 MHz 1 8 2 5 mA
1 MHz 5 2 0 mA
ICC2 VCC Intra-Page Read CE#= VIL , 10 MHz 5 2 0 mA
Current (Notes 2,3) OE# = VIH 40 MHz 10 40 mA
ICC3 VCC Active Write Current CE#= VIL , OE# = VIH 50 60 mA
(Notes 2,4,6) WE#=VIL
ICC4 VCC Standby Current CE#,RESET#=VCC±0.3V 20 50 uA
(Note 2) WP#=VIH
ICC5 VCC Reset Current RESET#=VSS±0.3V 20 50 uA
(Note 2) WP#=VIH
ICC6 Automatic Sleep Mo de VIL = V SS ± 0.3 V, 20 50 u A
(Note 2,5) VIH = VCC ± 0.3 V,
WP#=VIH
VIL Input Low V o ltage -0.5 0.8 V
VIH Input High Voltage 0.7xVCC VCC+0.5 V
VHH Voltage for ACC Program VCC = 2.7V ~ 3.6V 11.5 12.0 12.5 V
Acceleration
VID Vo ltage f or A uto select and VCC = 3.0 V ± 10% 11.5 12.0 12.5 V
Temporary Sector Unprotect
V OL Output Low V o ltage IOL= 4.0mA,VCC=VCC min 0.45 V
V OH1 Output High Voltage IOH=-2.0mA,VCC=VCC min 0.85xVCC V
V OH2 IOH=-100uA,VCC=VCC min VCC-0.4 V
VLKO Low VCC Lock-Out Voltage 2.3 2.5 V
(Note 4)
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SWITCHING TEST CIRCUITS
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change P ermitted Changing, State Unknown
Do es Not Apply Center Line is High Impedance State(High Z)
KEY TO SWITCHING WAVEFORMS
SWITCHING TEST WAVEFORMS
TEST SPECIFICATIONS
Test Condition All Speeds Unit
Output Lo ad 1 TTL gate
Output Lo ad Capacitance, CL 3 0 pF
(including jig capacitance)
Input Rise and F all Times 5 ns
Input Pulse Levels 0.0-3.0 V
Input timing measurement 1.5 V
reference levels
Output timing measurement 1.5 V
reference levels
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm 3.3V
1.5 1.5
Measurement Level
3.0V
0.0V OUTPUT
INPUT
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Read-Only Operations
AC CHARACTERISTICS
TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R)
Parameter Speed Options
Std. Description Test Setup 70R 9 0 Unit
tRC Read Cycle Time (Note 1) Min 7 0 9 0 ns
tACC Address to Output Delay CE#, OE#=VIL Max 70 9 0 ns
tCE Chip Enable to Output Delay OE#=VIL Max 7 0 9 0 ns
tPA C C P age Access Time Max 25 25 ns
tOE Output Enable to Output Delay Max 3 5 3 5 ns
tDF Chip Enable to Output High Z (No te 1) Max 1 6 ns
tD F Output Enable to Output High Z (No te 1) Max 1 6 ns
tO H Output Hold Time F rom Address, CE# Min 0 ns
o r OE#, whiche v er Occurs First
Read Min 35 ns
tOEH Output Enable Ho ld Time To ggle and Min 10 ns
(No te 1) Data# Polling
Notes:
1. Not 100% tested.
2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE f o r test specifications.
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MX29LV320MT/B
Figure 1. READ TIMING WAVEFORMS
Addresses
CE#
OE#
tACC
WE#
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
0V
VIH
VIL
VOH
VOL
HIGH Z HIGH Z
D ATA V alid
tOE
tOEH tDF
tCE
tRH
tRH
tRC
Outputs
RESET#
RY/BY#
tOH
ADD V alid
Figure 2. PAGE READ TIMING WAVEFORMS
Same Page
A2-A20
(A-1), A0~A2
CE#
OE#
Output
tACC
tPACC tPACC tPACC
Qa Qb Qc Qd
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MX29LV320MT/B
Figure 3. RESET# TIMING WAVEFORM
AC CHARACTERISTICS
Parameter Description Test Setup All Speed Options Unit
tREAD Y1 RESET# PIN Low (During Auto matic Algorithms) MAX 2 0 us
to Read o r Write (See No te)
tREAD Y2 RESET# PIN Low (NOT During Automatic Algorithms) MAX 500 ns
to Read o r Write (See No te)
tRP RESET# Pulse Width (NO T During Automatic Algo rithms) MIN 500 ns
tRH RESET# High Time Befo re Read (See Note) MIN 5 0 ns
tRB RY/BY# Reco very Time(to CE#, OE# go low) MIN 0 ns
tRPD RESET# Low to Standby Mo de MI N 2 0 us
No te:Not 100% tested
tRH
tRB
tReady1
tRP
tRP
tReady2
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
RESET#
RESET# Operations
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MX29LV320MT/B
Erase and Program Operations
AC CHARACTERISTICS
TA=-40°°
°°
°C to 85°°
°°
°C, VCC=2.7V~3.6V (T A= 0°°
°°
°C to 70°°
°°
°C, VCC=3.0V~3.6V for 70R)
Parameter Speed Options
Std. Description 70R 90 Unit
tWC Write Cycle Time (Note 1) Min 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during to ggle bit po lling Min 1 5 ns
tAH Address Hold Time Min 4 5 ns
tAHT Address Ho ld Time F ro m CE# or OE# high during toggle Min 0 ns
bit po lling
tDS Data Setup Time Min 3 5 ns
tDH Data Hold Time Min 0 ns
tCEPH CE# High During To ggle Bit Po lling Min 2 0 ns
tOEPH Output Enable High during to ggle bit polling Min 2 0 ns
tGHWL Read Reco very Time Befo re Write Min 0 ns
(OE# High to WE# Low)
tGHEL Read Reco very Time Befo re Write Min 0 ns
tCS CE# Setup Time Min 0 ns
tCH CE# Ho ld Time Min 0 ns
tWP Write Pulse Width Min 3 5 ns
tWPH Write Pulse Width High Min 3 0 ns
Write Buffer Pro gram Operatio n (No tes 2,3) Typ 240 us
Single Word/Byte Program Byte Typ 60 us
tWHWH1 Operatio n (Notes 2,5) W ord Typ 6 0 us
Accelerated Single Word/Byte Byte Typ 54 us
Programming Operatio n (Notes 2,5) W ord Typ 5 4 us
tWHWH2 Sector Erase Operatio n (Note 2) Typ 0.5 sec
tVCS VCC Setup Time (Note 1) Min 5 0 us
tRB Write Reco very Time from R Y/BY# Min 0 ns
tBUSY Pro gram/Erase V alid to RY/BY# Delay Min 7 0 9 0 ns
tVHH VHH Rise and F all Time (Note 1) Min 250 ns
tPOLL Program Valid Befo re Status Polling (No te 6) Max 4 us
Notes:
1. No t 100% tested.
2. See the "Erase And Pro gramming P erfo rmance" section fo r mo re info rmatio n.
3. Fo r 1-16 wo rds/1-32 bytes pro grammed.
4. Effectiv e write buffer specification is based upo n a 16-wo rd/32-byte write buff er o peratio n.
5. Wo rd/Byte programming specification is based upon a single word/byte pro gramming operation not utilizing the write
buffer.
6. When using the pro gram suspend/resume feature, if the suspend co mmand is issued within tPOLL, tPOLL must be
fully re-applied upo n resuming the programming o peratio n. If the suspend command is issued after tPOLL, tPOLL is
no t required again prio r to reading the status bits upon resuming.
37
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MX29LV320MT/B
Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS
Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM
ACC
tVHH
VHH
VIL or VIH VIL or VIH
tVHH
tWC
Address
OE#
CE#
A0h
XXXh PA
PD Status DOUT
PA PA
Note :
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
tAS
tAH
tPOLL
tCH
tWP
tDS tDH
tWHWH1
Read Status Data (last two cycle)Program Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE#
Data
RY/BY#
VCC
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MX29LV320MT/B
Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Verify Word Ok ?
YES
Auto Program Completed
Data Poll
from system
Increment
Address
Last Address ?
No
No
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MX29LV320MT/B
Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
2. Q7 may change simultaneously with Q5.
Therefore, Q7 should be verified.
3. If this flowchart location was reached because Q5=
"1" then the device FAILED. If this flowchart location
was reached because Q1="1", then the Write to
Buffer operation was ABORTED. In either case, the
proper reset command must be written before the
device can begin another operation. If Q1=1, write
the Write-Buffer-Programming-Abort-Reset com-
mand. If Q5=1, write the Reset command.
4. See Table 3 for command sequences required for
write buffer programming.
Write "Write to Buffer"
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Part of "Write to Buffer"
Command Sequence
Write program buffer
to flash sector address
Read Q7~Q0 at Last
Loaded Address
Read Q7~Q0 with address
= Last Loaded Address
FAIL or ABORT PASS
Write first address/data
Write next address/data pair
Write to a different
sector address
Write to buffer ABORTED.
Must write "Write-to-buffer
Abort Reset" command sequence
to return to read mode.
WC = WC - 1
WC = 0 ?
Abort Write to
Buffer Operation ?
Q7 = Data ?
Q5 = 1 ?
Q1 = 1 ?
Q7 and Q15 = Data ?
Yes
Yes
Yes
Yes
Yes
Yes
(Note 2)
(Note 1)
(Note 3)
No
No
No
No
No
No
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MX29LV320MT/B
Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and Secured Sector
read operations are also allowed
Data cannot be read from erase-or
program-suspended sectors
Write Program Resume
Command Sequence
Read data as
required
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Wait 15us
Done reading ?
No
Yes
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Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM
tWC
Address
OE#
CE#
55h
2AAh SA
30h In
Progress Complete
VA VA
Note :
1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
tAS
tAH
555h for chip erase
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
10 for Chip Erase
tVCS
WE#
Data
RY/BY#
VCC
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Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
Write Data 10H Address 555H
Write Data 55H Address 2AAH
DATA = FFh ?
YES
Auto Erase Completed
Data Poll
from system
No
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Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Auto Sector Erase Completed
Data Poll from System
YES
NO
Data=FFh?
Last Sector
to Erase ?
NO
YES
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AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter Speed Options
Std. Description 70R 90 Unit
tWC Write Cycle Time (Note 1) Min 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tAH Address Hold Time Min 4 5 ns
tDS Data Setup Time Min 3 5 ns
tDH Data Hold Time Min 0 ns
tGHEL Read Reco very Time Befo re Write Min 0 ns
(OE# High to WE# Low)
tWS WE# Setup Time Min 0 ns
tWH WE# Hold Time Min 0 ns
tCP CE# Pulse Width Min 3 5 ns
tCPH CE# Pulse Width High Min 2 5 ns
Write Buffer Pro gram Operation (Notes 2,3) Typ 24 0 us
Single Word/Byte Program Byte Typ 60 us
tWHWH1 Operatio n (Notes 2,5) W o rd Typ 60 us
Accelerated Single Wo rd/Byte Byte Typ 54 us
Pro gramming Operatio n (Notes 2,5) W o r d Typ 5 4 us
tWHWH2 Sector Erase Operatio n (Note 2) Typ 0.5 sec
tRH RESET HIGH Time Before Write (Note 1) Min 50 ns
Notes:
1. Not 100% tested.
2. See the "Erase And Pro gramming P erfo rmance" section fo r mo re info rmatio n.
3. Fo r 1-16 wo rds/1-32 bytes pro grammed.
4. Effectiv e write buffer specificatio n is based upon a 16-wo rd/32-byte write buff er o peratio n.
5. Wo rd/Byte programming specificatio n is based upon a single word/byte pro gramming operation not utilizing the write
buffer.
6. When using the pro gram suspend/resume f eature, if the suspend command is issued within tPOLL, tPOLL must be
fully re-applied upon resuming the programming o peration. If the suspend command is issued after tPOLL, tPOLL is
no t required again prior to reading the status bits upon resuming.
TA=-40° C to 85° C, VCC=2.7V~3.6V (TA= 0° C to 70° C, VCC=3.0V~3.6V for 70R)
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Figure 13. CE# CONTROLLED PROGRAM TIMING WAVEFORM
tWC
tWH
tGHEL
tWHWH1 or 2
tCP
Address
WE#
OE#
CE#
Data Q7
PA
Data# Polling
DOUT
RESET#
RY/BY#
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
tAH
tAS
PA for program
SA for sector erase
555 for chip erase
tRH
tDH
tDS
tWS
A0 for program
55 for erase
tCPH
tBUSY
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
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SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)
No te: Fo r sector gro up pro tect A6=0, A1=1, A0=0. Fo r chip unprotect A6=1, A1=1, A0=0
Sector Group Protect:150us
Chip Unprotect:15ms
1us
VID
VIH
Data
SA, A6
A1, A0
CE#
WE#
OE#
Valid* Valid*
Status
Valid*
Sector Group Protect or Chip Unprotect
40h60h60h
Verify
RESET#
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MX29LV320MT/B
Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH
RESET#=VID
START
PLSCNT=1
RESET#=VID
Wait 1us
Set up sector address
Sector Protect:
Write 60h to sector
address with
A6=0, A1=1, A0=0
Wait 150us
Verify Sector Protect:
Write 40h to sector
address with
A6=0, A1=1, A0=0
Read from
sector address
with
A6=0, A1=1, A0=0
Reset
PLSCNT=1
Remove VID from RESET#
Write reset command
Sector Protect
Algorithm
Chip Unprotect
Algorithm
Sector Protect complete Remove VID from RESET#
Write reset command
Sector Unprotect complete
Device failed
Temporary Sector
Unprotect Mode
Increment PLSCNT
Increment PLSCNT
First Write
Cycle=60h?
Set up first sector address
Protect all sectors:
The indicated portion of
the sector protect algorithm
must be performed
for all unprotected sectors
prior to issuing the first
sector unprotect address
Sector Unprotect:
Write 60h to sector
address with
A6=1, A1=1, A0=0
Wait 15 ms
Verify Sector Unprotect:
Write 40h to sector
address with
A6=1, A1=1, A0=0
Read from
sector address
with
A6=1, A1=1, A0=0
Data=01h?
PLSCNT=25?
Device failed
START
PLSCNT=1
RESET#=VID
Wait 1us
First Write
Cycle=60h?
All sectors
protected?
Data=00h?
PLSCNT=1000?
Last sector
verified?
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
YesYes
Yes
No
No
No
No
No
No
Protect another
sector?
Reset
PLSCNT=1
Temporary Sector
Unprotect Mode
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P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)
Parameter Description Test Setup All Speed Options Unit
tVLHT Voltage transitio n time Min. 4 us
tWPP1 Write pulse width fo r secto r group pro tect Min. 100 ns
tWPP2 Write pulse width fo r chip unpro tect Min. 100 ns
tOESP OE# setup time to WE# activ e Min. 4 us
AC CHARACTERISTICS
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
A6
tOESP
tWPP 1
tVLHT
tVLHT
tVLHT
Verify
01H F0H
A20-A16 Sector Address
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P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
Sector Protection
Complete
Data=01H?
Yes
.
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=32?
Yes
No
No
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MX29LV320MT/B
Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Chip Unprotect
Complete
Data=00H?
Yes
Set OE#=A9=VID
CE#=VIL, A6=1
Activate WE# Pulse
Time Out 15ms
Set OE#=CE#=VIL
A9=VID, A1=1
Set Up First Sector Addr
All sectors have
been verified?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=1000?
No
Increment
PLSCNT
No
Read Data from Device
Yes
Yes
No
Increment
Sector Addr
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
53
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Figure 20. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS
AC CHARACTERISTICS
Parameter Description Test All Speed Options Unit
Setup
tVIDR VID Rise and Fall Time (see No te) Min 5 00 ns
tRSP RESET# Setup Time for T emporary Sector Unprotect Min 4 us
tRRB RESET# Ho ld Time from RY/BY# High fo r Tempo rary Min 4 us
Secto r Group Unprotect
RESET#
CE#
WE#
RY/BY#
tVIDR
12V
0 or 3V VIL or VIH
tRSP
tVIDR
Program or Erase Command Sequence
tRRB
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MX29LV320MT/B
Figure 21. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
RESET# = VID (Note 1)
Perform Erase or Program Operation
RESET# = VIH
Temporary Sector Unprotect Completed(Note 2)
Operation Completed
2. All previously protected sectors are protected again.
Notes : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
55
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MX29LV320MT/B
Figure 22. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART
START
Enter Secured Silicon Sector
Data = 01h ?
No
Yes
Wait 1us
First Wait Cycle Data=60h
Second Wait Cycle Data=60h
A6=0, A1=1, A0=0
Wait 300us
Write Reset CommandDevice Failed
Secured Sector Protect Complete
56
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MX29LV320MT/B
Figure 23. SILICON ID READ TIMING WAVEFORM
tACC
tCE
tACC
tOE
tOH tOH
tDF
DATA OUT
Manufacturer ID Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
VID
VIH
VIL
ADD
A9
ADD
CE#
A1
OE#
WE#
ADD
A0
DATA OUT DATA OUT DATA OUT
DATA
Q0-Q15
VCC 3V
VIH
VIL
VIH
VIL
VIH
VIL
A2
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tACC tACC
tOH tOH
57
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MX29LV320MT/B
WRITE OPERATION STATUS
Figure 24. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Note :
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.
tDF
tCE
tCH
tOE
tOEH
tACC
tRC
tOH
Address
CE#
OE#
WE#
Q7
Q0-Q6
RY/BY#
tBUSY
Status Data Status Data
Status Data Complement True Valid Data
VAVAVA
High Z
High Z
Valid DataTrue
58
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MX29LV320MT/B
Figure 25. DATA# POLLING ALGORITHM
Notes:
1.V A=valid address fo r pro gramming.
2.Q7 sho uld be rechec ked e ven Q5="1" because Q7 ma y change simultaneo usly with Q5.
Read Q7~Q0
Add.=VA(1)
Read Q7~Q0
Add.=VA
Start
Q7 = Data ?
Q5 = 1 ?
Q7 = Data ?
FAIL Pass
No
No
(2)
No
Yes
Yes
Yes
59
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MX29LV320MT/B
Figure 26. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Note :
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
tDF
tCE
tCH tOE
tASO
tOEH
tACC tAHT
tCEPH
tOEPH
tRC tAS
tOH
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
tDH
Valid Status
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA
Valid Data
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P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
START
Read Q7~Q0
Read Q7~Q0
YES
NO
Toggle Bit Q6
=Toggle?
Q5=1?
YES
NO
(Note 1)
Read Q7~Q0 Twice (Note 1,2)
Toggle Bit Q6=
Toggle?
Program/Erase Operation Not
Complete, Write Reset Command
YES
Program/Erase Operation Complete
Figure 27. TOGGLE BIT ALGORITHM
No tes :
1. Read to ggle bit twice to determine whether or no t it is to ggling.
2. Recheck toggle bit because it may stop to ggling as Q5 changes to "1".
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P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
Figure 28. Q6 versus Q2
Note :
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
WE#
Enter Embedded
Erasing Erase
Suspend Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase Suspend
Read Erase
Erase
Resume
Erase
Complete
Erase
Q6
Q2
62
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MX29LV320MT/B
MIN. MAX.
Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V
Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical pro gram and erase times assume the fo llo wing co nditio ns: 25°C, 3.0 V VCC. Programming specifications
assume checkerboard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 pro gram/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the
write buffer.
4 . Fo r 1-16 wo rds or 1-32 bytes pro grammed in a single write buffer programming o peration.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer
operation.
6 . In the pre-pro gramming step of the Embedded Erase algorithm, all bits are programmed to 00h befo re erasure.
7 . System-level o verhead is the time required to execute the command sequence(s) for the program co mmand. See
Tables 3 fo r further info rmatio n on co mmand definitions.
8. The de vice has a minimum erase and pro gram cycle endur ance o f 100,000 cycles.
Parameter Min Unit
Minimum Pattern Data Retention Time 2 0 Years
DATA RETENTION
PARAMETER Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0. 5 3 .5 sec Excludes 00h
programming
Chip Erase Time 3 2 sec prior to erasure
Note 6
Total Write Buffer Program Time (Note 4) 2 40 us Excludes
Total Accelerated Effective Write Buffer 2 00 us system level
Program Time (Note 4) overhead
Chip Program Time 31.5 sec Note 7
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MX29LV320MT/B
Parameter Symbol Parameter Description Test S et TYP MAX UNIT
CIN Input Capacitance VIN=0 TSOP/SOP 6 7.5 pF
CSP 4.2 5.0 pF
COUT Output Capacitance VOUT=0 TSOP/SOP 8.5 12 pF
CSP 5.4 6.5 pF
CIN2 Control Pin Capacitance VIN=0 TSOP/SOP 7.5 9 pF
CSP 3.9 4.7 pF
PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. T est conditions T A=25°C, f=1.0MHz
64
P/N:PM1129 REV. 1.1 , JUL. 14, 2005
MX29LV320MT/B
ORDERING INFORMATION
PART NO. ACCESS TIME Ball Pitch/ PACKAGE Remark
(ns) Ball size
MX29LV320MTMC-70R 70 44 Pin SOP
MX29LV320MTMC-90 90 44 Pin SOP
MX29LV320MBMC-70R 70 44 Pin SOP
MX29LV320MBMC-90 90 44 Pin SOP
MX29LV320MTMI-90 90 44 Pin SOP
MX29LV320MBMI-90 90 44 Pin SOP
MX29LV320MTTC-70R 70 48 Pin TSOP
(Normal Type)
MX29LV320MTTC-90 90 48 Pin TSOP
(Normal Type)
MX29LV320MBTC-70R 70 48 Pin TSOP
(Normal Type)
MX29LV320MBTC-90 90 48 Pin TSOP
(Normal Type)
MX29LV320MTTI-90 90 48 Pin TSOP
(Normal Type)
MX29LV320MBTI-90 90 48 Pin TSOP
(Normal Type)
MX29LV320MTXBC-70R 70 0.8mm/0.3mm 48 Ball CSP
MX29LV320MTXBC-90 90 0.8mm/0.3mm 48 Ball CSP
MX29LV320MBXBC-70R 70 0.8mm/0.3mm 48 Ball CSP
MX 2 9LV320MBXBC-9 0 90 0.8mm/0.3mm 48 Ball CSP
MX29LV320MTXBI-90 90 0.8mm/0.3mm 48 Ball CSP
MX29LV320MBXBI-90 90 0.8mm/0.3mm 48 Ball CSP
MX29LV320MTXEC-70R 70 0.8mm/0.4mm 48 Ball CSP
MX29LV320MTXEC-90 90 0.8mm/0.4mm 48 Ball CSP
MX29LV320MBXEC-70R 70 0.8mm/0.4mm 48 Ball CSP
MX 2 9LV320MBXEC-9 0 90 0.8mm/0.4mm 48 Ball CSP
MX29LV320MTXEI-90 90 0.8mm/0.4mm 48 Ball CSP
MX29LV320MBXEI-90 90 0.8mm/0.4mm 48 Ball CSP
65
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PART NO. ACCESS TIME Ball Pitch/ PACKAGE Remark
(ns) Ball size
MX29LV320MTMC-90G 90 44 Pin SOP PB-free
MX29LV320MBMC-90G 90 44 Pin SOP PB-free
MX29LV320MTMI-90G 90 44 Pin SOP PB-free
MX29LV320MBMI-90G 90 44 Pin SOP PB-free
MX29LV320MTTC-90G 90 48 Pin TSOP PB-free
(Normal Type)
MX29LV320MBTC-90G 90 48 Pin TSOP PB-free
(Normal Type)
MX29LV320MTTI-90G 90 48 Pin TSOP PB-free
(Normal Type)
MX29LV320MBTI-90G 90 4 8 Pin TSOP PB-free
(Normal Type)
MX29LV320MTXBC-90G 90 0.8mm/0.3mm 48 Ball CSP PB-free
MX29LV320MBXBC-90G 90 0.8mm/0.3mm 48 Ball CSP PB-free
MX29LV320MTXBI-90G 90 0.8mm/0.3mm 4 8 Ball CSP PB-free
MX29LV320MBXBI-90G 90 0.8mm/0.3mm 4 8 Ball CSP PB-free
MX29LV320MTXEC-90G 90 0.8mm/0.4mm 48 Ball CSP PB-free
MX29LV320MBXEC-90G 90 0.8mm/0.4mm 48 Ball CSP PB-free
MX29LV320MTXEI-90G 90 0.8mm/0.4mm 4 8 Ball CSP PB-free
MX29LV320MBXEI-90G 90 0.8mm/0.4mm 4 8 Ball CSP PB-free
MX29LV320MTMC-70Q 70 44 Pin SOP PB-free
MX29LV320MBMC-70Q 70 44 Pin SOP PB-free
MX29LV320MTTC-70Q 70 48 Pin TSOP PB-free
(Normal Type)
MX29LV320MBTC-70Q 70 48 Pin TSOP PB-free
(Normal Type)
MX29LV320MTXBC-70Q 70 0.8mm/0.3mm 48 Ball CSP PB-free
MX29LV320MBXBC-70Q 70 0.8mm/0.3mm 48 Ball CSP PB-free
MX29LV320MTXEC-70Q 70 0.8mm/0.4mm 48 Ball CSP PB-free
MX29LV320MBXEC-70Q 70 0.8mm/0.4mm 48 Ball CSP PB-free
No te : VCC operatio n range fo r -70R and -70Q is 3.0V~3.6V.
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REVISION HISTORY
Revision No. Description Page Date
1.0 1. Added TA=0°C to 70°C , VCC=3.0V~3.6V for 70Q operation P65 MAR/11/2005
2. Removed "Advanced Information" P1
1. 1 1. To correct content error P6,8,45 JUL/14/2005
2. To add note 7 for ILIT parameter in DC Characteristics table P3 1
3. To add comments into performance table P62
4. To add tWPP2 parameter P4 9
5. To add "tPOLL" parameter into Automatic Program Waveform P3 7
6. To add "tASO", "tAS", "tAHT", "tCEPH" and "tOEPH" parameters P59
into Toggle Bit Timing Waveform
MX29LV320MT/B
MACRONIX INTERNATIONAL CO., LTD .
Headquarters:
TEL:+886-3-578-6688
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