4-11
STK10C68-M
DESCRIPTION
The Simtek STK10C68-M is a fast static RAM (35, 45
and 55ns), with a nonvolatile electrically-erasable PROM
(EEPROM) element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data may easily be transferred
from the SRAM to the EEPROM (
STORE
), or from the
EEPROM to the SRAM (
RECALL
) using the NE pin. It
combines the high performance and ease of use of a
fast SRAM with nonvolatile data integrity.
The STK10C68 features industry standard pinout for
nonvolatile RAMs in a 28-pin 300 mil ceramic DIP, and
28-pad LCC packages. Commercial and industrial
temperature devices are also available.
FEATURES
• 35, 45 and 55ns Access Times
• 20 and 25ns Output Enable Access
• Unlimited Read and Write to SRAM
• Hardware
STORE
Initiation
• Automatic
STORE
Timing
• 100,000
STORE
cycles to EEPROM
• 10 year data retention in EEPROM
• Automatic
RECALL
on Power Up
• Hardware
RECALL
Initiation
• Unlimited
RECALL
cycles from EEPROM
• Single 5V±10% Operation
• Available in multiple standard packages
LOGIC BLOCK DIAGRAM PIN CONFIGURATIONS
A
A
A
A
A
A
A
A
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
G
A
E
DQ
Vss NE
Vcc
W
NC
7
12
6
5
4
3
2
1
0
0
1
8
9
11
10
7
6
2
3
4
5
TOP VIEW
4
5
6
7
8
9
10
11
12
32128 2726
25
24
23
22
21
20
19
18
1716151413
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NE
A
A
A
A
A
A
A
A
DQ
DQ
DQ DQ
DQ
DQ
DQ
DQ
V
V
W
NC
A
A
A
G
A
E
SS
7
6
5
4
3
2
1
0
0
1
2
8
9
10
7
6
5
4
3
CC
A
12
11
PIN NAMES
28-LCC 28-300 CDIP
A
A
A
A
A
A
4
5
6
7
8
EEPROM ARRAY
256 x 256
STORE
RECALL
STATIC RAM
ARRAY
256 x 256
ROW DECODER
STORE/
RECALL
CONTROL
AAAAA
0 1 2 10 11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
G
NE
E
W
COLUMN I/O
COLUMN DECODER
INPUT BUFFERS
A3
A
9
12
STK10C68-M
CMOS nvSRAM
High Performance
8K x 8 Nonvolatile Static RAM
MIL-STD-833/SMD 5962 - 93056
A0 - A12 Address Inputs
W Write Enable
DQ0 - DQ7Data In/Out
E Chip Enable
G Output Enable
NE Nonvolatile Enable
VCC Power (+5V)
VSS Ground
4-12
STK10C68-M
ICC bAverage VCC Current 90 mA tAVAV = 35ns
85 mA tAVAV = 45ns
80 mA tAVAV = 55ns
ICC dAverage VCC Current 50 mA E ≥ (VCC – 0.2V)
during
STORE
cycle all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
ISB cAverage VCC Current 27 mA tAVAV = 35ns
(Standby, Cycling TTL Input Levels) 23 mA tAVAV = 45ns
20 mA tAVAV = 55ns
E ≥ VIH; all others cycling
ISB cAverage VCC Current 2 mA E ≥ (VCC – 0.2V)
(Standby, Stable CMOS Input Levels) all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
IILK Input Leakage Current (Any Input) ±1µAV
CC = max
VIN = VSS to VCC
IOLK Off State Output Leakage Current ±5µAV
CC = max
VIN = VSS to VCC
VIH Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
VIL Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
VOH Output Logic "1" Voltage 2.4 V IOUT = –4mA
VOL Output Logic "0" Voltage 0.4 V IOUT = 8mA
TAOperating Temperature –55 125 °C
ABSOLUTE MAXIMUM RATINGSa
Figure 1: AC Output Loading
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(One output at a time, one second duration)
5.0V
Output
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
255 Ohms
Note e: These parameters are guaranteed but not tested.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
AC TEST CONDITIONS
CAPACITANCEe (TA=25°C, f=1.0MHz)
CIN Input Capacitance 5 pF ∆V = 0 to 3V
COUT Output Capacitance 7 pF ∆V = 0 to 3V
SYMBOL PARAMETER MAX UNITS CONDITIONS
SYMBOL PARAMETER MIN MAX UNITS NOTES
1
2
1
2
Note b: ICC is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: ICC is the average current required for the duration of the store cycle (t
STORE
) after the sequence (tWC) that initiates the cycle.
1
2
4-13
STK10C68-M
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
READ CYCLE #2 f,g
READ CYCLE #1 f,g,h
W
DQ (Data Out)
ADDRESS
DATA VALID
5
t
AXQX
11A
t
WHQV
2
t
AVAV
3
t
AVQV
READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO. PARAMETER UNITS
1t
ELQV tACS Chip Enable Access Time 35 45 55 ns
2t
AVAVgtRC Read Cycle Time 35 45 55 ns
3t
AVQVhtAA Address Access Time 35 45 55 ns
4t
GLQV tOE Output Enable to Data Valid 20 25 25 ns
5t
AXQX tOH Output Hold After Address Change 5 5 5 ns
6t
ELQX tLZ Chip Enable to Output Active 5 5 5 ns
7t
EHQZitHZ Chip Disable to Output Inactive 17 20 25 ns
8t
GLQX tOLZ Output Enable to Output Active 0 0 0 ns
9t
GHQZitOHZ Output Disable to Output Inactive 17 20 25 ns
10 tELICCHetPA Chip Enable to Power Active 0 0 0 ns
11 tEHICCLc,e tPS Chip Disable to Power Standby 35 45 55 ns
11A tWHQV tWR Write Recovery Time 45 55 65 ns
SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M
Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: NE must be high during entire cycle.
Note g: For READ CYCLE #1 and #2, W and NE must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured ± 200mV from steady state output voltage.
ADDRESS
E
G
DQ (Data Out)
DATA VALID
I
CC
W
2
t
AVAV
1
t
ELQV
6
t
ELQX
4
t
GLQV
8
t
GLQX
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
10
t
ELICCH
11A
t
WHQV
ACTIVE
STANDBY
4-14
STK10C68-M
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
NO. PARAMETER UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
12 tAVAV tAVAV tWC Write Cycle Time 35 45 55 ns
13 tWLWH tWLEH tWP Write Pulse Width 30 35 45 ns
14 tELWH tELEH tCW Chip Enable to End of Write 30 35 45 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 18 20 30 ns
16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 30 35 45 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns
19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns
SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M
NO. PARAMETER UNITS
WRITE CYCLES #1 & #2; G low
12 tAVAV tAVAV tWC Write Cycle Time 45 45 55 ns
13 tWLWH tWLEH tWP Write Pulse Width 35 35 45 ns
14 tELWH tELEH tCW Chip Enable to End of Write 35 35 45 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 30 30 30 ns
16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 35 35 45 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns
19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns
20 tWLQZi,m tWZ Write Enable to Output Disable 35 35 35 ns
21 tWHQX tOW Output Active After End of Write 5 5 5 ns
SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M
WRITE CYCLES #1 & #2; G high (VCC = 5.0V ± 10%)
Note f: NE must be ≥ VIH during entire cycle.
Note i: Measured + 200mV from steady state output voltage.
Note k: E or W must be ≥ VIH during address transitions.
Note m: If W is low when E goes low, the outputs remain in the high impedance state.
(VCC = 5.0V ± 10%)
4-15
STK10C68-M
PREVIOUS DATA
ADDRESS
E
W
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
12
t
AVAV
14
t
ELWH
19
t
WHAX
17
t
AVWH
18
t
AVWL
13
t
WLWH
15
t
DVWH
16
t
WHDX
20
t
WLQZ
21
t
WHQX
WRITE CYCLE #1: W CONTROLLED f,k
ADDRESS
E
W
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
12
t
AVAV
18
t
AVEL
14
t
ELEH
19
t
EHAX
17
t
AVEH
13
t
WLEH
15
t
DVEH
16
t
EHDX
WRITE CYCLE #2: E CONTROLLED f,k
4-16
STK10C68-M
NE
G
W
E
DQ (Data Out)
HIGH IMPEDANCE
26
t
NLEL
25
t
GHEL
28
t
WLEL
23
t
ELNHS
22
t
ELQXS
STORE CYCLES #1 & #2 (VCC = 5.0V ± 10%)
STORE CYCLE #2: E CONTROLLEDo
HIGH IMPEDANCE
NE
G
W
E
DQ (Data Out)
24
t
GHNL
26
t
NLWL
23
t
WLNH
27
t
ELWL
22
t
WLQX
STORE CYCLE #1: W CONTROLLEDo
Note n: An automatic
RECALL
also takes place at power up, starting when VCC exceeds 4.0V, and taking t
RECALL
from the time at which VCC exceeds 4.5V.
VCC must not drop below 4.0V once it has been exceeded for the
RECALL
to function properly.
Note o: If E is low for any period of time in which W is high and G and NE are low, then a
RECALL
cycle may be initiated.
Note p: Measured with W and NE both returned high, and G returned low. Note that
STORE
cycles are inhibited/aborted by VCC < 4.0V (
STORE
inhibit).
Note q: Once tWC has been satisfied by NE, G, W and E, the
STORE
cycle is completed automatically. Any of NE, G, W or E may be used to terminate the
STORE
initiation cycle.
#1 #2 Alt.
22 tWLQXptELQXS t
STORE
STORE
Cycle Time 12 ms
23 tWLNHqtELNHS tWC
STORE
Initiation Cycle Time 35 ns
24 tGHNL Output Disable Set-up to NE Fall 0 ns
25 tGHEL Output Disable Set-up to E Fall 0 ns
26 tNLWL tNLEL NE Set-up 0ns
27 tELWL Chip Enable Set-up 0 ns
28 tWLEL Write Enable Set-up 0 ns
SYMBOLS
NO. PARAMETER MIN MAX UNITS
MODE SELECTION
H X X X Not Selected Standby
L H L H Read RAM Active
L L X H Write RAM Active
L H L L Nonvolatile
RECALL
nActive
L L H L Nonvolatile
STORE
ICC
LLLL No operation Active
LHHX
E W G NE MODE POWER
2
NONVOLATILE MEMORY OPERATION
4-17
STK10C68-M
NO. PARAMETER MIN MAX UNITS
RECALL CYCLES #1, #2 & #3 (VCC = 5.0V ± 10%)
HIGH IMPEDANCE
E
DQ (Data Out)
G
W
NE
31
tNLGL
30
tGLNH
33
tWHGL
34
tELGL
29
tGLQXR
RECALL CYCLE #3: G CONTROLLEDo,t
HIGH IMPEDANCE
E
DQ (Data Out)
G
W
NE
31
t
NLEL
32
t
GLEL
33
t
WHEL
30
t
ELNHR
29
t
ELQXR
RECALL CYCLE #2: E CONTROLLEDo
HIGH IMPEDANCE
DQ (Data Out)
NE
G
W
E
30
t
NLNH
32
t
GLNL
33
t
WHNL
34
t
ELNL
35
t
NLQZ
29
t
NLQX
RECALL CYCLE #1: NE CONTROLLEDo
#1 #2 #3
29 tNLQXrtELQXR tGLQXR
RECALL
Cycle Time 25 µs
30 tNLNHstELNHR tGLNH
RECALL
Initiation Cycle Time 35 ns
31 tNLEL tNLGL NE Set-up 0ns
32 tGLNL tGLEL Output Enable Set-up 0 ns
33 tWHNL tWHEL tWHGL Write Enable Set-up 0 ns
34 tELNL tELGL Chip Enable Set-up 0 ns
35 tNLQZ NE Fall to Outputs Inactive 35 ns
SYMBOLS
Note r: Measured with W and NE both high, and G and E low.
Note s: Once tNLNH has been satisfied by NE, G, W and E, the
RECALL
cycle is completed automatically. Any of NE, G or E may be used to terminate the
RECALL
initiation cycle.
Note t: If W is low at any point in which both E and NE are low and G is high, then a
STORE
cycle will be initiated instead of a
RECALL
.
4-18
STK10C68-M
LOW and G is HIGH. While any sequence to achieve
this state will initiate a
STORE
, only W initiation (
STORE
CYCLE #1) and E initiation (
STORE
CYCLE #2) are
practical without risking an unintentional SRAM WRITE
that would disturb SRAM data. During a
STORE
cycle,
previous nonvolatile data is erased and the SRAM
contents are then programmed into nonvolatile ele-
ments. Once a
STORE
cycle is initiated, further input
and output is disabled and the DQ0-7 pins are tri-stated
until the cycle is completed.
If E and G are LOW and W and NE are HIGH at the end
of the cycle, a READ will be performed and the outputs
will go active, signaling the end of the
STORE
.
HARDWARE PROTECT
The STK10C68-M offers two levels of protection to
suppress inadvertent
STORE
cycles. If the control
signals (E, G, W, and NE) remain in the
STORE
condition at the end of a
STORE
cycle, a second
STORE
cycle will
not
be started. The
STORE
(or
RECALL
) will
be initiated only after a transition on any one of these
signals to the required state. In addition to multi-trigger
protection, the STK10C68-M offers hardware protec-
tion through VCC Sense. A
STORE
cycle will not be
initiated, and one in progress will discontinue, if VCC
goes below 4.0V. 4.0V is a typical, characterized
value.
NONVOLATILE RECALL
A
RECALL
cycle is performed when E, G, and NE are
LOW and W is HIGH. Like the
STORE
cycle,
RECALL
is
initiated when the last of the four clock signals goes to
the
RECALL
state. Once initiated, the
RECALL
cycle will
take tNLQX to complete, during which all inputs are
ignored. When the
RECALL
completes, any READ or
WRITE state on the input pins will take effect.
Internally,
RECALL
is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL
operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be recalled
an unlimited number of times.
The STK10C68-M has two modes of operation: SRAM
mode and nonvolatile mode, determined by the state of
the NE pin. When in SRAM mode, the memory
operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to EEPROM or from EEPROM to SRAM.
SRAM READ
The STK10C68-M performs a READ cycle whenever E
and G are LOW and NE and W are HIGH. The address
specified on pins A0-12 determines which of the 8192
data bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid after
a delay of tAVQV (READ CYCLE #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ CYCLE #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for
transitions on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W or NE is brought LOW.
The STK10C68-M is a high speed memory and there-
fore must have a high frequency bypass capacitor of
approximately 0.1µF connected between DUT VCC
and VSS using leads and traces that are as short as
possible. As with all high speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM WRITE
A write cycle is performed whenever E and W are LOW
and NE is HIGH. The address inputs must be stable
prior to entering the WRITE cycle and must remain
stable until either E or W go HIGH at the end of the
cycle. The data on pins DQ0-7 will be written into the
memory if it is valid tDVWH before the end of a W
controlled WRITE or tDVEH before the end of an E
controlled
WRITE.
It is recommended that G be kept HIGH during the entire
WRITE cycle to avoid data bus contention on common
I/O lines. If G is left LOW, internal circuitry will turn off
the output buffers tWLQZ after W goes LOW.
NONVOLATILE STORE
A
STORE
cycle is performed when NE, E and W are
DEVICE OPERATION
4-19
STK10C68-M
Like the
STORE
cycle, a transition must occur on some
control pin to cause a recall, preventing inadvertent
multi-triggering. On power-up, once VCC exceeds the
VCC sense voltage of 4.0V, a
RECALL
cycle is automati-
cally initiated. The voltage on the VCC pin must not drop
below 4.0V once it has risen above it in order for the
RECALL
to operate properly. Due to this automatic
RECALL
, SRAM operation cannot commence until tNLQX
after VCC exceeds 4.0V. 4.0V is a typical, character-
ized value.
If the STK10C68-M is in a WRITE state at the end of
power-up
RECALL
, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor should
be connected between W and system VCC.
4-20
STK10C68-M
Temperature Range
M = Military (-55 to 125 degrees C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Package
C = Ceramic 28 pin 300-mil DIP with gold lead finish
K = Ceramic 28 pin 300-mil DIP with solder DIP finish
L = Ceramic 28 pin LCC
Retention / Endurance
10 years / 100,000 cycles
STK10C68 - 5 C 35 M
Lead Finish
A =Solder DIP lead finish
C =Gold lead DIP finish
X =Lead finish "A" or "C" is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
5962-93056 04 MX X
ORDERING INFORMATION
