S-1740/1741 Series
5.5 V INPUT, 100 mA
V
OLTAGE REGULATO
R
WITH SUPPLY VOLTAGE DIVIDED OUTPUT
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© ABLIC Inc., 2016-2018 Rev.1.3_00
1
The S-1740/1741 Series, developed using CMOS technology, is a positive voltage regulator with the supply voltage divided
output, which features super low current consumption and low dropout voltage.
The regulator block has low current consumption of 0.35 μA typ. and high-accuracy output voltage of ±1.0%.
The function of the supply voltage divided output is prepared in the S-1740/1741 Series. The supply voltage divided output is
a function that divides the input voltage (VIN) of the regulator into VIN/2 or VIN/3 and outputs the voltage. For example, this
function makes it possible that the IC connects to a low voltage microcontroller A/D converter directly and the microcontroller
monitors a battery voltage.
Features
Regulator block
• Output voltage: VOUT = 1.0 V to 3.5 V, selectable in 0.05 V step
• Input voltage: VIN = 1.5 V to 5.5 V
• Output voltage accuracy: ±1.0% (1.0 V to 1.45 V output product: ±15 mV) (Ta = +25°C)
• Dropout voltage: 20 mV typ. (2.5 V output product, at IOUT = 10 mA) (Ta = +25°C)
• Current consumption during operation: ISS1 = 0.35 μA typ. (Ta = +25°C)
• Output current: Possible to output 100 mA ( at VIN ≥ VOUT
(
S
)
+ 1.0 V)*1
• Input capacitor: A ceramic capacitor can be used. (1.0 μF or more)
• Output capacitor: A ceramic capacitor can be used. (1.0 μF to 100 μF)
• Built-in overcurrent protection circuit: Limits overcurrent of output transistor.
Supply voltage divider block
• Output voltage: VPMOUT = VIN/2 (S-1740 Series)
V
PMOUT = VIN/3 (S-1741 Series)
•
Current consumption during operation
:
ISS1P = 0.15 μA typ. (Ta = +25°C)
• Output capacitor: A ceramic capacitor can be used. (100 nF to 220 nF)
• Built-in enable circuit: Ensures long battery life.
Overall
• Operation temperature range: Ta = −40°C to +85°C
• Lead-free (Sn 100%), halogen-free
*1. Please make sure that the loss of the IC will not exceed the power dissipation when the output current is large.
Applications
• Constant-voltage power supply and battery voltage monitoring support for battery-powered device
• Constant-voltage power supply for portable communication device, digital camera, and digital audio player
• Constant-voltage power supply for home electric appliance
Packages
• SOT-23-5
• HSNT-6(1212)
• HSNT-4(1010)
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5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
2
Block Diagram
1. S-1740/1741 Series A / C type (SOT-23-5, HSNT-6(1212))
*1
VSS
PMEN
VIN
PMOUT
VOUT
Enable circuit
Reference
voltage circuit
Overcurrent
protection circuit
SW
+
−
+
−
Product Type Output Voltage (VPMOUT) PMEN Pin Logic
S-1740 Series A type VIN/2 Active "H"
S-1740 Series C type Active "L"
S-1741 Series A type VIN/3 Active "H"
S-1741 Series C type Active "L"
*1. Parasitic diode
Figure 1
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
3
2. S-1740/1741 Series G type (HSNT-4(1010))
*1
VSS
VIN
PMOUT
VOUT
Reference
voltage circuit
Overcurrent
protection circuit
+
−
+
−
Product Type Output Voltage (VPMOUT) PMEN Pin Logic
S-1740 Series G type VIN/2 Without PMEN pin
S-1741 Series G type VIN/3
*1. Parasitic diode
Figure 2
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
4
Product Name Structure
Users can select supply voltage divider block output voltage, product type, regulator block output voltage, and
package type for the S-1740/1741 Series. Refer to "1. Product name" regarding the contents of product name, "2.
Function list of product type" regarding the product type, "3. Packages" regarding the package drawings and "4.
Product name list" for details of product names.
1. Product name
S-174x x xx - xxxx U 4
Product type*4
A, C, G
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
A6T2: HSNT-6(1212), Tape
A4T2: HSNT-4(1010), Tape*2
Regulator block output voltage*3
10 to 35
(e.g., when the output voltage is 1.0 V, it is expressed as 10.)
Environmental code
U: Lead-free (Sn 100%), halogen-free
Supply voltage divider block output voltage*4
0: VIN/2
1: VIN/3
*1. Refer to the tape drawing.
*2. Only S-1740/1741 Series G type
*2. Contact our sales office when the product which has 0.05 V step is necessary.
*3. Refer to "2. Function list of product type" and "2. 2 PMEN pin" in "2. Supply voltage divider
block" in " Operation".
2. Function list of product type
Table 1
Product Type Output Voltage (VPMOUT) PMEN Pin Logic Package
S-1740 Series A type
VIN/2
Active "H" HSNT-6(1212),
SOT-23-5
S-1740 Series C type Active "L"
S-1740 Series G type Without PMEN pin HSNT-4(1010)
S-1741 Series A type
VIN/3
Active "H" HSNT-6(1212),
SOT-23-5
S-1741 Series C type Active "L"
S-1741 Series G type Without PMEN pin HSNT-4(1010)
3. Packages
Table 2 Package Drawing Codes
Package Name Dimension Tape Reel Land
SOT-23-5 MP005-A-P-SD MP005-A-C-SD MP005-A-R-SD −
HSNT-6(1212) PM006-A-P-SD PM006-A-C-SD PM006-A-R-SD PM006-A-L-SD
HSNT-4(1010) PL004-A-P-SD PL004-A-C-SD PL004-A-R-SD PL004-A-L-SD
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
5
4. Product name list
4. 1 S-1740 Series
4. 1. 1 A type
PMEN pin logic: Active "H" Output Voltage (VPMOUT): VIN/2
Table 3
Output Voltage (VOUT) SOT-23-5 HSNT-6(1212)
1.0 V ± 15 mV S-1740A10-M5T1U4 S-1740A10-A6T2U4
1.7 V ± 1.0% S-1740A17-M5T1U4 S-1740A17-A6T2U4
1.8 V ± 1.0% S-1740A18-M5T1U4 S-1740A18-A6T2U4
2.0 V ± 1.0% S-1740A20-M5T1U4 S-1740A20-A6T2U4
2.1 V ± 1.0% S-1740A21-M5T1U4 S-1740A21-A6T2U4
3.0 V ± 1.0% S-1740A30-M5T1U4 S-1740A30-A6T2U4
Remark Please contact our sales office for products with specifications other than the above.
4. 1. 2 C type
PMEN pin logic: Active "L" Output Voltage (VPMOUT): VIN/2
Table 4
Output Voltage (VOUT) SOT-23-5 HSNT-6(1212)
1.0 V ± 15 mV S-1740C10-M5T1U4 S-1740C10-A6T2U4
1.7 V ± 1.0% S-1740C17-M5T1U4 S-1740C17-A6T2U4
1.8 V ± 1.0% S-1740C18-M5T1U4 S-1740C18-A6T2U4
2.0 V ± 1.0% S-1740C20-M5T1U4 S-1740C20-A6T2U4
2.1 V ± 1.0% S-1740C21-M5T1U4 S-1740C21-A6T2U4
3.0 V ± 1.0% S-1740C30-M5T1U4 S-1740C30-A6T2U4
Remark Please contact our sales office for products with specifications other than the above.
4. 1. 3 G type
PMEN pin logic: Without PMEN pin Output Voltage (VPMOUT): VIN/2
Table 5
Output Voltage (VOUT) HSNT-4(1010)
1.0 V ± 15 mV S-1740G10-A4T2U4
1.7 V ± 1.0% S-1740G17-A4T2U4
1.8 V ± 1.0% S-1740G18-A4T2U4
2.0 V ± 1.0% S-1740G20-A4T2U4
2.1 V ± 1.0% S-1740G21-A4T2U4
3.0 V ± 1.0% S-1740G30-A4T2U4
Remark Please contact our sales office for products with specifications other than the above.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
6
4. 2 S-1741 Series
4. 2. 1 A type
PMEN pin logic: Active "H" Output Voltage (VPMOUT): VIN/3
Table 6
Output Voltage (VOUT) SOT-23-5 HSNT-6(1212)
1.0 V ± 15 mV S-1741A10-M5T1U4 S-1741A10-A6T2U4
1.7 V ± 1.0% S-1741A17-M5T1U4 S-1741A17-A6T2U4
1.8 V ± 1.0% S-1741A18-M5T1U4 S-1741A18-A6T2U4
2.0 V ± 1.0% S-1741A20-M5T1U4 S-1741A20-A6T2U4
2.1 V ± 1.0% S-1741A21-M5T1U4 S-1741A21-A6T2U4
3.0 V ± 1.0% S-1741A30-M5T1U4 S-1741A30-A6T2U4
Remark Please contact our sales office for products with specifications other than the above.
4. 2. 2 C type
PMEN pin logic: Active "L" Output Voltage (VPMOUT): VIN/3
Table 7
Output Voltage (VOUT) SOT-23-5 HSNT-6(1212)
1.0 V ± 15 mV S-1741C10-M5T1U4 S-1741C10-A6T2U4
1.7 V ± 1.0% S-1741C17-M5T1U4 S-1741C17-A6T2U4
1.8 V ± 1.0% S-1741C18-M5T1U4 S-1741C18-A6T2U4
2.0 V ± 1.0% S-1741C20-M5T1U4 S-1741C20-A6T2U4
2.1 V ± 1.0% S-1741C21-M5T1U4 S-1741C21-A6T2U4
3.0 V ± 1.0% S-1741C30-M5T1U4 S-1741C30-A6T2U4
Remark Please contact our sales office for products with specifications other than the above.
4. 2. 3 G type
PMEN pin logic: Without PMEN pin Output Voltage (VPMOUT): VIN/3
Table 8
Output Voltage (VOUT) HSNT-4(1010)
1.0 V ± 15 mV S-1741G10-A4T2U4
1.7 V ± 1.0% S-1741G17-A4T2U4
1.8 V ± 1.0% S-1741G18-A4T2U4
2.0 V ± 1.0% S-1741G20-A4T2U4
2.1 V ± 1.0% S-1741G21-A4T2U4
3.0 V ± 1.0% S-1741G30-A4T2U4
Remark Please contact our sales office for products with specifications other than the above.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
7
Pin Configurations
1. SOT-23-5
132
45
Top view
Figure 3
Table 9 S-1740/1741 Series A / C type
Pin No. Symbol Description
1 VIN Input voltage pin
2 VSS GND pin
3 PMEN Supply voltage divided output enable pin
4 PMOUT Supply voltage divided output pin
5 VOUT Output voltage pin
2. HSNT-6(1212)
Top view
1
3
2
6
4
5
6
4
5
1
3
2
Bottom view
*1
Figure 4
Table 10 S-1740/1741 Series A / C type
Pin No. Symbol Description
1 VOUT Output voltage pin
2 VSS GND pin
3 PMOUT Supply voltage divided output pin
4 PMEN Supply voltage divided output enable pin
5 NC*2 No connection
6 VIN Input voltage pin
*1. Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
*2. The NC pin is electrically open.
The NC pin can be connected to the VIN pin or the VSS pin.
3. HSNT-4(1010)
Top view
14
23
Bottom view
41
32
*1
Figure 5
Table 11 S-1740/1741 Series G type
Pin No. Symbol Description
1 VOUT Output voltage pin
2 VSS GND pin
3 PMOUT Supply voltage divided output pin
4 VIN Input voltage pin
*1. Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
8
Absolute Maximum Ratings
Table 12
(Ta = +25°C unless otherwise specified)
Item Symbol Absolute Maximum Rating Unit
Input voltage Regulator block VIN V
SS − 0.3 to VSS + 6.0 V
Supply voltage divider block VPMEN V
SS − 0.3 to VSS + 6.0 V
Output voltage Regulator block VOUT V
SS − 0.3 to VIN + 0.3 V
Supply voltage divider block VPMOUT V
SS − 0.3 to VIN + 0.3 V
Output current IOUT 120 mA
Operation ambient temperature To
pr
−40 to +85 °C
Storage temperature Tst
g
−40 to +125 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 13
Item Symbol Condition Min. Typ. Max. Unit
Junction-to-ambient thermal resistance*1 θJA
SOT-23-5
Board A − 192 − °C/W
Board B − 160 − °C/W
Board C − − − °C/W
Board D − − − °C/W
Board E − − − °C/W
HSNT-6(1212)
Board A − 234 − °C/W
Board B − 193 − °C/W
Board C − − − °C/W
Board D − − − °C/W
Board E − − − °C/W
HSNT-4(1010)
Board A − 378 − °C/W
Board B − 317 − °C/W
Board C − − − °C/W
Board D − − − °C/W
Board E − − − °C/W
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark Refer to " Power Dissipation" and "Test Board" for details.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
9
Electrical Characteristics
1. Regulator block
Table 14
(Ta = +25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Output voltage
*1
V
OUT(E)
V
IN
= V
OUT(S)
+
1.0 V,
I
OUT
= 10 mA
1.0 V
≤
V
OUT(S)
< 1.5 V V
OUT(S)
−
0.015 V
OUT(S)
V
OUT(S)
+
0.015 V 1
1.5 V
≤
V
OUT(S)
≤
3.5 V V
OUT(S)
×
0.99 V
OUT(S)
V
OUT(S)
×
1.01 V 1
Output current
*2
I
OUT
V
IN
≥
V
OUT
(
S
)
+
1.0 V 100
*5
− −
mA 3
Dropout voltage
*3
V
drop
I
OUT
= 10 mA
1.0 V
≤
V
OUT
(
S
)
< 1.1 V 0.50
−
−
V 1
1.1 V
≤
V
OUT
(
S
)
< 1.2 V 0.40
−
−
V 1
1.2 V
≤
V
OUT
(
S
)
< 1.3 V 0.30
−
−
V 1
1.3 V
≤
V
OUT
(
S
)
< 1.4 V 0.20
−
−
V 1
1.4 V
≤
V
OUT
(
S
)
< 1.5 V 0.10
−
−
V 1
1.5 V
≤
V
OUT
(
S
)
< 1.7 V
−
0.050 0.080 V 1
1.7 V
≤
V
OUT
(
S
)
< 1.8 V
−
0.040 0.060 V 1
1.8 V
≤
V
OUT
(
S
)
< 2.0 V
−
0.040 0.050 V 1
2.0 V
≤
V
OUT
(
S
)
< 2.5 V
−
0.030 0.040 V 1
2.5 V
≤
V
OUT
(
S
)
< 2.8 V
−
0.020 0.030 V 1
2.8 V
≤
V
OUT
(
S
)
< 3.0 V
−
0.019 0.021 V 1
3.0 V
≤
V
OUT
(
S
)
≤
3.5 V
−
0.018 0.020 V 1
Line regulation
Δ
V
OUT1
Δ
V
IN
•
V
OUT
V
OUT(S)
+
0.5 V
≤
V
IN
≤
5.5 V, I
OUT
= 10 mA
−
0.05 0.2 %/V 1
Load regulation
Δ
V
OUT2
V
IN
= V
OUT(S)
+
1.0 V, 1
μ
A
≤
I
OUT
≤
50 mA
−
20 40 mV 1
Output voltage
temperature coefficient
*4
Δ
V
OUT
Δ
Ta
•
V
OUT
V
IN
= V
OUT(S)
+
1.0 V, I
OUT
= 10 mA,
−
40
°
C
≤
Ta
≤
+
85
°
C
−
±
130
−
ppm/
°
C1
Current consumption
during operation I
SS1
V
IN
= V
OUT(S)
+
1.0 V, no load
−
0.35 0.53
μ
A 2
Input voltage V
IN
−
1.5
−
5.5 V
−
Short-circuit current I
short
V
IN
= V
OUT(S)
+
1.0 V, V
OUT
= 0 V
−
60
−
mA 3
*1. VOUT(S): Set output voltage
VOUT(E): Actual output voltage
Output voltage when fixing IOUT (= 10 mA) and inputting VOUT
(
S
)
+ 1.0 V
*2. The output current at which the output voltage becomes 95% of VOUT
(
E
)
after gradually increasing the output current.
*3. Vdrop = VIN1 − (VOUT3 × 0.98)
V
IN1 is the input voltage at which the output voltage becomes 98% of VOUT3 after gradually decreasing the input
voltage.
VOUT3 is the output voltage when VIN = VOUT
(
S
)
+ 1.0 V and IOUT = 10 mA.
*4. A change in the temperature of the output voltage [mV/°C] is calculated using the following equation.
ΔVOUT
ΔTa []
mV/°C *1 = VOUT(S) []
V*2 × ΔVOUT
ΔTa•VOUT
[]
ppm/°C *3 ÷ 1000
*1. Change in temperature of output voltage
*2. Set output voltage
*3. Output voltage temperature coefficient
*5. Due to limitation of the power dissipation, this value may not be satisfied. Attention should be paid to the power
dissipation when the output current is large.
This specification is guaranteed by design.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
10
2. Supply voltage divider block
Table 15
(Ta = +25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test
Circuit
Output voltage
*1
VPMOUT
(S)
V
IN
= 3.6 V,
−
10
μ
A
≤
I
PMOUT
≤
10
μ
A
S-1740 Series
−
V
IN
/2
−
V 4
S-1741 Series
−
V
IN
/3
−
V 4
Load current I
PMOUT
V
IN
= 3.6 V
−
10
−
10
μ
A
−
Output offset voltage V
POF
V
IN
= 3.6 V,
−
10
μ
A
≤
I
PMOUT
≤
10
μ
A
−
30
−
30 mV 4
Output impedance R
PS
V
IN
= 3.6 V,
−
10
μ
A
≤
I
PMOUT
≤
10
μ
A
−
−
1000
Ω
4
Set-up time t
PU
S-1740/1741 Series A / C type,
V
IN
= 3.6 V, C
PM
= 220 nF, no load
−
5 10 ms 4
Current consumption
during operation
*2
I
SS1P
V
IN
= 3.6 V, when supply voltage divided output is
enabled, no load
−
0.15 0.23
μ
A 5
Input voltage V
IN
−
1.5
−
5.5 V
−
PMEN pin input voltage "H" V
PSH
S-1740/1741
Series A / C type
V
IN
= 3.6 V, determined by
VPMOUT
output level 1.0
−
−
V 6
PMEN pin input voltage "L" V
PSL
V
IN
= 3.6 V, determined by
VPMOUT
output level
−
−
0.25 V 6
PMEN pin input current "H" I
PSH
V
IN
= 3.6 V, V
PMEN
= V
IN
−
0.1
−
0.1
μ
A 6
PMEN pin input current "L" I
PSL
V
IN
= 3.6 V, V
PMEN
= 0 V
−
0.1
−
0.1
μ
A 6
Discharge shunt resistance
during power-off R
PLOW
S-1740/1741 Series A / C type,
V
IN
= 3.6 V, when supply voltage divided output is
disabled, V
PMOUT
= 0.1 V
−
2.8
−
k
Ω
7
*1. V
PMOUT(S): Set output voltage
VPMOUT(S) + VPOF: Actual output voltage
*2. Increased current value from the current consumption during operation (ISS1) of the regulator block when the supply
voltage divided output is enabled.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
11
Test Circuits
+
VOUT
VIN
VSS
+
V
A
PMEN
*1
Set to Disable
PMOUT
Figure 6 Test Circuit 1
VOUT
VIN
Set to Disable
+
A
PMEN
*1
VSS
PMOUT
Figure 7 Test Circuit 2
Set to Disable
VOUT
VIN
+
V
+
A
PMEN
*1
VSS
PMOUT
Figure 8 Test Circuit 3
+
PMOUT
VIN
VSS +
V
PMEN
*1
Set to Enable
VOUT
A
Figure 9 Test Circuit 4
PMOUT
VIN
VSS
PMEN
*1
Set to Enable
VOUT
+A
Figure 10 Test Circuit 5
*1. Only S-1740/1741 Series A / C type
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
12
VOUT
VIN
PMEN*1
VSS
+
A PMOUT
+
V
Figure 11 Test Circuit 6
Set to Enable
VOUT
VIN
+
V
PMEN*1
VSS
PMOUT +
A
Figure 12 Test Circuit 7
*1. Only S-1740/1741 Series A / C type
Standard Circuit
C
IN
*1 C
L
*2
Input Output for regulator block
GND
Single GND
VOUT
VIN
VSS
PMEN*4 PMOUT
C
L
*2
C
PM
*3
Output for supply voltage
divider block
*1. C
IN is a capacitor for stabilizing the input.
*2. C
L is a capacitor for stabilizing the output.
*3. C
PM is a capacitor for stabilizing the output.
*4. Only S-1740/1741 Series A / C type
Figure 13
Caution The above connection diagram and constants will not guarantee successful operation. Perform
thorough evaluation including the temperature characteristics with an actual application to set the
constants.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
13
Condition of Application
Input capacitor (CIN): A ceramic capacitor with capacitance of 1.0 μF or more is recommended.
Output capacitor (CL): A ceramic capacitor with capacitance of 1.0 μF to 100 μF is recommended.
Output capacitor (CPM): A ceramic capacitor with capacitance of 100 nF to 220 nF is recommended.
Caution Generally, in a voltage regulator, an oscillation may occur depending on the selection of the external
parts. Perform thorough evaluation including the temperature characteristics with an actual
application using the above capacitors to confirm no oscillation occurs.
Selection of Regulator Block Input Capacitor (CIN) and Output Capacitor (CL)
The S-1740/1741 Series requires CL between the VOUT pin and the VSS pin for regulator phase compensation.
The operation is stabilized by a ceramic capacitor with capacitance of 1.0 μF to 100 μF. When using an OS capacitor, a
tantalum capacitor or an aluminum electrolytic capacitor, the capacitance must also be 1.0 μF to 100 μF. However, an
oscillation may occur depending on the equivalent series resistance (ESR).
Moreover, the S-1740/1741 Series requires CIN between the VIN pin and the VSS pin for a stable operation.
Generally, an oscillaiton may occur when a voltage regulator is used under the conditon that the impedance of the power
supply is high. Note that the output voltage transient characteristics vary depending on the capacitance of CIN and CL and
the value of ESR.
Caution Perform thorough evaluation including the temperature characteristics with an actual application to
select CIN, CL.
Selection of Supply Voltage Divider Block Output Capacitor (CPM)
The S-1740/1741 Series requires CPM between the PMOUT pin and the VSS pin for supply voltage divider phase
compensation.
The operation is stabilized by a ceramic capacitor with capacitance of 100 nF to 220 nF. When using an OS capacitor, a
tantalum capacitor or an aluminum electrolytic capacitor, the capacitance must also be 100 nF to 220 nF. However, an
oscillation may occur depending on ESR.
Note that the output voltage transient characteristics vary depending on the capacitance of CPM and the value of ESR.
Caution Perform thorough evaluation including the temperature characteristics with an actual application to
select CPM.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
14
Explanation of Terms
1. Regulator block
1. 1 Output voltage (VOUT)
This voltage is output at an accuracy of ±1.0% or ±15 mV*2 when the input voltage, the output current and the
temperature are in a certain condition*1.
*1. Differs depending on the product.
*2. When VOUT < 1.5 V: ±15 mV, when VOUT ≥ 1.5 V: ±1.0%
Caution If the certain condition is not satisfied, the output voltage may exceed the accuracy range of
±1.0% or ±15 mV. Refer to Table 14 in " Electrical Characteristics" for details.
1. 2 Line regulation
ΔVOUT1
ΔVIN•VOUT
Indicates the dependency of the output voltage against the input voltage. The value shows how much the
output voltage changes due to a change in the input voltage after fixing output current constant.
1. 3 Load regulation (ΔVOUT2)
Indicates the dependency of the output voltage against the output current. The value shows how much the
output voltage changes due to a change in the output current after fixing input voltage constant.
1. 4 Dropout voltage (Vdrop)
Indicates the difference between input voltage (VIN1) and the output voltage when the output voltage becomes
98% of the output voltage value (VOUT3) at VIN = VOUT(S) + 1.0 V after the input voltage (VIN) is decreased
gradually.
Vdrop = VIN1 − (VOUT3 × 0.98)
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
15
1. 5 Output voltage temperature coefficient
ΔVOUT
ΔTa•VOUT
The shaded area in Figure 14 is the range where VOUT varies in the operation temperature range when the
output voltage temperature coefficient is ±130 ppm/°C.
V
OUT(E)*1
Example of S-1740/1741A10 typ. product
−40 +25
+0.13 mV/°C
V
OUT
[V]
*1. V
OUT(E)
is the value of the output voltage measured at Ta = +25°C.
+85 Ta [°C]
−0.13 mV/°C
Figure 14
A change in the temperature of the output voltage [mV/°C] is calculated using the following equation.
ΔVOUT
ΔTa []
mV/°C *1 = VOUT(S) []
V*2 × ΔVOUT
ΔTa•VOUT
[]
ppm/°C *3 ÷ 1000
*1. Change in temperature of output voltage
*2. Set output voltage
*3. Output voltage temperature coefficient
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
16
2. Supply voltage divider block
2. 1 Supply voltage divided output
This is a function that divides the input voltage (VIN) of the regulator into VIN/2 or VIN/3 and outputs the voltage.
For example, a microcontroller can monitor a battery voltage by inputting output voltage (VPMOUT) to the microcontroller
A/D converter.
2. 2 Output voltage (VPMOUT)
This is the voltage of the divided VIN, which is VIN/2 in the S-1740 Series and VIN/3 in the S-1741 Series.
2. 3 Output offset voltage (VPOF)
This is the supply voltage divider block offset voltage when VIN, the load current and the temperature are in a certain
condition.
Caution If the certain condition is not satisfied, the output voltage may exceed the accuracy range of
±30 mV. Refer to " Electrical Characteristics" for details.
2. 4 Output impedance (RPS)
This is the supply voltage divider block impedance. It shows how much VPMOUT changes when the load current
changes.
For example, the output impedance can be used in sampling rate calculation as signal source impedance when
VPMOUT from the PMOUT pin is input to the A/D converter as a microcontroller input signal.
2. 5 Set-up time (tPU) (S-1740/1741 Series A / C type)
This is the time from when the supply voltage divided output is enabled until VPMOUT stabilizes.
VPMOUT, VPOF and RPS are not guaranteed until the set-up time elapses.
2. 6 Discharge shunt resistance during power-off (RPLOW) (S-1740/1741 Series A / C type)
The ON resistance of the N-channel transistor built into the supply voltage divider block.
When the supply voltage divided output is disabled, VPMOUT is set to the VSS level by the built-in N-channel
transistor.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
17
Operation
1. Regulator block
1. 1 Basic operation
Figure 15 shows the block diagram of the regulator block to describe the basic operation.
The error amplifier compares the feedback voltage (Vfb) whose output voltage (VOUT) is divided by the feedback
resistors (Rs and Rf) with the reference voltage (Vref). The error amplifier controls the output transistor,
consequently, the regulator starts the operation that holds VOUT constant without the influence of the input
voltage (VIN).
*1
*1. Parasitic diode
VS
S
Current
Supply
−
+
Vfb
Vref
VIN
VOUT
Rf
Rs
Error amplifier
Reference voltage
circuit
Figure 15
1. 2 Output transistor
In the S-1740/1741 Series, a low on-resistance P-channel MOS FET is used between the VIN pin and the
VOUT pin as the output transistor. In order to keep VOUT constant, the ON resistance of the output transistor
varies appropriately according to the output current (IOUT).
Caution Since a parasitic diode exists between the VIN pin and the VOUT pin due to the structure of
the transistor, the IC may be damaged by a reverse current if VOUT becomes higher than VIN.
Therefore, be sure that VOUT does not exceed VIN + 0.3 V.
1. 3 Overcurrent protection circuit
The S-1740/1741 Series has a built-in overcurrent protection circuit to limit the overcurrent of the output
transistor. When the VOUT pin is shorted to the VSS pin, that is, at the time of the output short-circuit, the
output current is limited to 60 mA typ. due to the overcurrent protection circuit operation. The S-1740/1741
Series restarts regulating when the output transistor is released from the overcurrent status.
Caution This overcurrent protection circuit does not work as for thermal protection. For example,
when the output transistor keeps the overcurrent status long at the time of output short-
circuit or due to other reasons, pay attention to the conditions of the input voltage and the
load current so as not to exceed the power dissipation.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
18
2. Supply voltage divider block
2. 1 Basic operation
2. 1. 1 S-1740/1741 Series A / C type
Figure 16 shows the block diagram of the S-1740/1741 Series A / C type to describe basic operation.
Reference voltage (Vrefpm) is generated by dividing the input voltage (VIN) to VIN/2 or VIN/3 using the dividing
resistance (Rpm1 and Rpm2). Since the buffer amplifier constitutes a voltage follower, it can perform the
feedback control so that the output voltage (VPMOUT) and Vrefpm are the same. Low output impedance is
realized by the buffer amplifier, while outputting VPMOUT according to VIN.
When "L" is input to the PMEN pin in the S-1740/1741 Series A type, or "H" is input to the PMEN pin in the C
type, the current which flows to Rpm1 and Rpm2 and the current which flows to the buffer amplifier can be
stopped. The buffer amplifier output is pulled down to VSS by the built-in N-channel transistor, and VPMOUT is
set to the VSS level.
PMEN
VSS
VIN
PMOUT
Enable circuit
SW
Rpm1
Rpm2
Vrefpm
Buffer amplifie
r
+
−
Figure 16
2. 1. 2 S-1740/1741 Series G type
Figure 17 shows the block diagram of the S-1740/1741 Series G type to describe basic operation.
Vrefpm is made by dividing VIN to VIN/2 or VIN/3 using Rpm1 and Rpm2. Since the buffer amplifier constitutes a
voltage follower, it can perform the feedback control so that VPMOUT and Vrefpm are the same. Low output
impedance is realized by the buffer amplifier, while outputting VPMOUT according to VIN.
VSS
VIN
PMOUT
Rpm1
Rpm2
Vrefpm
Buffer amplifier
+
−
Figure 17
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
19
2. 2 PMEN pin
2. 2. 1 S-1740/1741 Series A / C type
The PMEN pin controls the enable circuit.
When "H" is input to the PMEN pin in the S-1740/1741 Series A type, or "L" is input to the PMEN pin in the C
type, the enable circuit operates. This enables the supply voltage divided output and allows for monitoring of the
power supply voltage. When "L" is input to the PMEN pin in the S-1740/1741 Series A type, or "H" is input to the
PMEN pin in the C type, the enable circuit stops. This disables the supply voltage divided output, reducing the
IC current consumption.
In addition, the PMEN pin has absolutely no effect on the operation of the regulator block.
Table 16
Product Type PMEN Pin Supply Voltage Divided Output Output Voltage
(VPMOUT)
Current
Consumption
VOUT Pin
Voltage
A "H" Enable VPMOUT
*1 ISS1 + ISS1P V
OUT
A "L" Disable VSS level ISS1 V
OUT
C "L" Enable VPMOUT
*1 ISS1 + ISS1P V
OUT
C "H" Disable VSS level ISS1 V
OUT
*1. Refer to *1 in Table 15 in " Electrical Characteristics".
Figure 18 shows the internal equivalent circuit structure in relation to the PMEN pin. The PMEN pin is neither
pulled up nor pulled down, so do not use it in the floating status. When not using the PMEN pin, connect it to the
VIN pin. Note that the current consumption increases when a voltage of 0.25 V to VIN − 0.3 V is applied to the
PMEN pin.
VSS
VIN
PMEN
Figure 18
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
20
2. 3 PMEN pin voltage and output voltage (VPMOUT)
2. 3. 1 S-1740/1741 Series A / C type
Figure 19 shows the relation between the PMEN pin voltage and the supply voltage divided output.
When "H" is input to the PMEN pin in the S-1740/1741 Series A type, or "L" is input to the PMEN pin in the C
type, the supply voltage divided output is enabled. Once set-up time (tPU) = 10 ms max.*1 elapses, the output
voltage (VPMOUT) will settle and the power supply voltage can be monitored.
When "L" is input to the PMEN pin in the S-1740/1741 Series A type, or "H" is input to the PMEN pin in the C
type, the supply voltage divided output is disabled. VPMOUT is set to the VSS level by the built-in N-channel
transistor.
By inputting "H" and "L" alternately to the PMEN pin, allowing for minimization of current consumption during
the period when the power supply voltage is not monitored.
*1. When Ta = +25°C, VIN = 3.6 V, CPM = 220 nF, no load
V
PMEN
V
PMOUT
t
PU
V
PMOUT(S)
+
V
POF
t
PU
V
PMOUT(S)
+
V
POF
Example of active "H"
Figure 19
Remark VPMEN = VIN ↔ VSS
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
21
Typical Application in S-1740/1741 Series A / C Type
Figure 20 shows the circuit diagram of the typical application in the S-1740/1741 Series A / C type, and Figure 21 shows
the timing chart.
As shown in Figure 20, connect the PMOUT pin to an analog input pin (AIN pin) of the A/D converter in the
microcontroller. The microcontroller can monitor the battery voltage by inputting the output voltage (VPMOUT) to the A/D
converter.
The input voltage from the battery is converted to output voltage by the regulator operation, and the microcontroller starts
driving with the voltage. The supply voltage divided output can be controlled by inputting "H" and "L" signals output from
the microcontroller I/O pin to the PMEN pin. Control the supply voltage divided output according to the A/D converter
operation timing.
When inputting "H" to the PMEN pin in the S-1740/1741 Series A type, or "L" to the PMEN pin in the C type, the
microcontroller monitors the battery voltage. The IC current consumption can be minimized by inputting "L" to the PMEN
pin in the S-1740/1741 Series A type, or "H" to the PMEN pin in the C type when battery voltage is not monitored.
Battery
S-1740/1741 Series
A / C type
VOUT
VIN
PMEN
VSS
PMOUT
Microcontroller
VDD
IN
A/D
converter
VSS
CPM
CL
CIN
I/O
Figure 20
V
PMOUT
V
PMOUT(S)
+
V
POF
Voltage monitoring timing
t
PU
t
PU
t
PU
V
PMEN
Example of active "H"
Figure 21
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
22
Precautions
• Generally, when a voltage regulator is used under the condition that the load current value is small (1.0 μA or less), the
output voltage may increase due to the leakage current of an output transistor.
• Generally, when a voltage regulator is used under the condition that the temperature is high, the output voltage may
increase due to the leakage current of an output transistor.
• Generally, when a voltage regulator is used under the condition that the impedance of the power supply is high, an
oscillation may occur. Perform thorough evaluation including the temperature characteristics with an actual application
to select CIN.
• Generally, in a voltage regulator, an oscillation may occur depending on the selection of the external parts. The
following use conditions are recommended in the S-1740/1741 Series, however, perform thorough evaluation including
the temperature characteristics with an actual application to select CIN, CL and CPM.
Input capacitor (CIN): A ceramic capacitor with capacitance of 1.0 μF or more is recommended.
Output capacitor (CL): A ceramic capacitor with capacitance of 1.0 μF to 100 μF is recommended.
Output capacitor (CPM): A ceramic capacitor with capacitance of 100 nF to 220 nF is recommended.
• Generally, in a voltage regulator, the values of an overshoot and an undershoot in the output voltage vary depending
on the variation factors of input voltage start-up, input voltage fluctuation and load fluctuation etc., or the capacitance of
CIN, CL or CPM and the value of the equivalent series resistance (ESR), which may cause a problem to the stable
operation. Perform thorough evaluation including the temperature characteristics with an actual application to select
CIN, CL and CPM.
• Generally, in a voltage regulator, if the VOUT pin is steeply shorted with GND, a negative voltage exceeding the
absolute maximum ratings may occur in the VOUT pin due to resonance phenomenon of the inductance and the
capacitance including CL on the application. The resonance phenomenon is expected to be weakened by inserting a
series resistor into the resonance path, and the negative voltage is expected to be limited by inserting a protection
diode between the VOUT pin and the VSS pin.
• Make sure of the conditions for the input voltage, output voltage and the load current so that the internal loss does not
exceed the power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• When considering the output current value that the IC is able to output, make sure of the output current value specified
in Table 14 in " Electrical Characteristics" and footnote *5 of the table.
• Wiring patterns on the application related to the VIN pin, the VOUT pin and the VSS pin should be designed so that the
impedance is low. When mounting CIN between the VIN pin and the VSS pin and CL between the VOUT pin and the
VSS pin, connect the capacitors as close as possible to the respective destination pins of the IC.
• In the package equipped with heat sink of backside, mount the heat sink firmly. Since the heat radiation differs
according to the condition of the application, perform thorough evaluation with an actual application to confirm no
problems happen.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
23
Characteristics (Typical Data)
1. Regulator block
1. 1 Output voltage vs. Output current (When load current increases) (Ta = +25°C)
1. 1. 1 VOUT = 1.0 V 1. 1. 2 VOUT = 2.5 V
0.6
0.2
0.8
0.4
0.0
1.0
1.2
VOUT [V]
IOUT [mA]
100 200 300 400 500
0
VIN = 1.3 V
VIN = 1.5 V
VIN = 2.0 V
VIN = 3.0 V
VIN = 5.5 V
1.5
0.5
2.0
1.0
0.0
2.5
3.0
V
OUT
[V]
I
OUT
[mA]
100 200 300 400 500
0
V
IN
= 2.8 V
V
IN
= 3.0 V
V
IN
= 3.5 V
V
IN
= 4.5 V
V
IN
= 5.5 V
1. 1. 3 VOUT = 3.5 V
0.0
4.0
VOUT [V]
IOUT [mA]
100 200 300 400 500
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VIN = 3.8 V
VIN = 4.0 V
VIN = 4.5 V
VIN = 5.5 V
Remark In determining the output current, attention should
be paid to the following.
1. The minimum output current value and
footnote *5 of Table 14 in " Electrical
Characteristics"
2. Power dissipation
1. 2 Output voltage vs. Input voltage (Ta = +25°C)
1. 2. 1 VOUT = 1.0 V 1. 2. 2 VOUT = 2.5 V
0.9
0.7
1.0
0.8
0.6
1.1
1.2
VOUT [V]
VIN [V]
1.0 1.4 1.8 2.2 2.6
0.6
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
2.0
2.7
2.6
2.5
2.4
2.3
2.2
2.1
V
OUT
[V]
V
IN
[V]
2.5 3.0 3.5 4.0 4.5
2.0
I
OUT
= 1 mA
I
OUT
= 10 mA
I
OUT
= 50 mA
I
OUT
= 100 mA
1. 2. 3 VOUT = 3.5 V
3.0
3.7
3.6
3.5
3.4
3.3
3.2
3.1
VOUT [V]
VIN [V]
3.5 4.0 4.5 5.0 5.5
3.0
IOUT = 1 mA
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
24
1. 3 Dropout voltage vs. Output current
1. 3. 1 VOUT = 1.0 V 1. 3. 2 VOUT = 2.5 V
1000
Vdrop [V]
IOUT [mA]
80604020
0.0
1.2
1.0
0.8
0.6
0.4
0.2
Ta = +85C
Ta = +25C
Ta = 40C
1000
Vdrop [V]
IOUT [mA]
80604020
0.00
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
Ta = +85C
Ta = +25C
Ta = 40C
1. 3. 3 VOUT = 3.5 V
1000
Vdrop [V]
IOUT [mA]
80604020
0.00
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
Ta = +85C
Ta = +25C
Ta = 40C
1. 4 Dropout voltage vs. Set output voltage
3.51.0
Vdrop [V]
VOUT(S) [V]
3.02.52.01.5
0.0
1.2
1.0
0.8
0.6
0.4
0.2
IOUT = 0.1 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 10 mA
IOUT = 1 mA
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
25
1. 5 Output voltage vs. Ambient temperature
1. 5. 1 VOUT = 1.0 V 1. 5. 2 VOUT = 2.5 V
1.10
V
OUT
[V]
−
40 8
5
7550250
−
25
Ta [ °C]
0.90
1.05
1.00
0.95
2.70
V
OUT
[V]
−
40 8
5
7550250
−
25
Ta [ °C]
2.30
2.60
2.50
2.40
1. 5. 3 VOUT = 3.5 V
3.80
V
OUT
[V]
−
40 8
5
7550250
−
25
Ta [ °C]
3.20
3.50
3.30
3.60
3.40
3.70
1. 6 Current consumption vs. Input voltage
1. 6. 1 VOUT = 1.0 V 1. 6. 2 VOUT = 2.5 V
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
SS1
[A]
V
IN
[V]
6.0
0.0 5.04.03.02.01.0
Ta = +85C
Ta = +25C
Ta = 40C
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
SS1
[A]
V
IN
[V]
6.0
0.0 5.04.03.02.01.0
Ta = +85C
Ta = +25C
Ta = 40C
1. 6. 3 VOUT = 3.5 V
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
SS1
[A]
V
IN
[V]
6.0
0.0 5.04.03.02.01.0
Ta = +85C
Ta = +25C
Ta = 40C
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
26
1. 7 Current consumption vs. Ambient temperature
1. 7. 1 VOUT = 1.0 V 1. 7. 2 VOUT = 2.5 V
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
SS1
[A]
−
40 8
5
7550250
−
25
Ta [ C]
V
IN
= 2.0 V
V
IN
= 5.5 V
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
SS1
[A]
−
40 8
5
7550250
−
25
Ta [ C]
V
IN
= 3.5 V
V
IN
= 5.5 V
1. 7. 3 VOUT = 3.5 V
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
SS1
[A]
−
40 8
5
7550250
−
25
Ta [ C]
V
IN
= 4.5 V
V
IN
= 5.5 V
1. 8 Current consumption vs. Output current
1. 8. 1 VOUT = 1.0 V 1. 8. 2 VOUT = 2.5 V
1000
IOUT [mA]
80604020
0
40
35
30
25
20
15
10
5
ISS1
[A]
VIN = 2.0 V
VIN = 5.5 V
1000
IOUT [mA]
80604020
0
40
35
30
25
20
15
10
5
ISS1
[A]
VIN = 3.5 V
VIN = 5.5 V
1. 8. 3 VOUT = 3.5 V
1000
IOUT [mA]
80604020
0
40
35
30
25
20
15
10
5
ISS1
[A]
VIN = 4.5 V
VIN = 5.5 V
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
27
2. Supply voltage divider block
2. 1 Output voltage vs. Load current
VPMOUT = VIN/2, VIN = 3.6 V VPMOUT = VIN/3, VIN = 3.6 V
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
PMOUT
[V]
I
PMOUT
[A]
105
05
10
Ta = 85C
Ta = 25C
Ta = 40C
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
PMOUT
[V]
I
PMOUT
[A]
1050
5
10
Ta = 85C
Ta = 25C
Ta = 40C
2. 2 Output voltage vs. Input voltage (Ta = +25°C)
VPMOUT = VIN/2 VPMOUT = VIN/3
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
PMOUT
[V]
V
IN
[V]
5.54.53.52.52.0 3.0 4.0 5.0
1.5
I
PMOUT
= 10 A
I
PMOUT
= 10 A
I
PMOUT
= 0 A
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
PMOUT
[V]
V
IN
[V]
5.54.53.52.52.0 3.0 4.0 5.0
1.5
I
PMOUT
= 10 A
I
PMOUT
= 10 A
I
PMOUT
= 0 A
2. 3 Output voltage vs. Ambient temperature
VPMOUT = VIN/2 VPMOUT = VIN/3
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
PMOUT
[V]
40 857550250
25
Ta [ C]
I
PMOUT
= 10 A
I
PMOUT
= 10 A I
PMOUT
= 0 A
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
PMOUT
[V]
40 857550250
25
Ta [ C]
I
PMOUT
= 10 A
I
PMOUT
= 10 A I
PMOUT
= 0 A
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
28
Reference Data
1. Characteristics of input transient response (Ta = +25°C)
1. 1 VOUT = 1.0 V
I
OUT
= 1 mA, C
IN
= C
L
= 1
μ
F, V
IN
= 2.0 V
↔
3.0 V, t
r
= t
f
= 5.0
μ
s
I
OUT
= 50 mA, C
IN
= C
L
= 1
μ
F, V
IN
= 2.0 V
↔
3.0 V, t
r
= t
f
= 5.0
μ
s
t [s]
V
IN
[V]
1.5 4.0
0.0
1200−200 0 200 600
400 800 1000
0.7
1.4 3.5
1.3 3.0
1.2 2.5
1.1 2.0
1.0 1.5
0.9 1.0
0.8 0.5
V
OUT
[V]
V
IN
V
OUT
t [s]
V
IN
[V]
1.5 4.0
0.0
1200−200 0 200 600
400 800 1000
0.7
1.4 3.5
1.3 3.0
1.2 2.5
1.1 2.0
1.0 1.5
0.9 1.0
0.8 0.5
V
OUT
[V]
V
OUT
V
IN
1. 2 VOUT = 2.5 V
I
OUT
= 1 mA, C
IN
= C
L
= 1
μ
F, V
IN
= 3.5 V
↔
4.5 V, t
r
= t
f
= 5.0
μ
s
I
OUT
= 50 mA, C
IN
= C
L
= 1
μ
F, V
IN
= 3.5 V
↔
4.5 V, t
r
= t
f
= 5.0
μ
s
t [s]
V
IN
[V]
3.0 5.5
1.5
1200−200 0 200 600
400 800 1000
2.2
2.9 5.0
2.8 4.5
2.7 4.0
2.6 3.5
2.5 3.0
2.4 2.5
2.3 2.0
V
OUT
[V]
V
OUT
V
IN
t [s]
V
IN
[V]
3.0 5.5
1.5
1200−200 0 200 600
400 800 1000
2.2
2.9 5.0
2.8 4.5
2.7 4.0
2.6 3.5
2.5 3.0
2.4 2.5
2.3 2.0
V
OUT
[V]
V
OUT
V
IN
1. 3 VOUT = 3.5 V
I
OUT
= 1 mA, C
IN
= C
L
= 1
μ
F, V
IN
= 4.5 V
↔
5.5 V, t
r
= t
f
= 5.0
μ
s
I
OUT
= 50 mA, C
IN
= C
L
= 1
μ
F, V
IN
= 4.5 V
↔
5.5 V, t
r
= t
f
= 5.0
μ
s
t [s]
V
IN
[V]
4.0 6.5
2.5
1200−200 0 200 600
400 800 1000
3.2
3.9 6.0
3.8 5.5
3.7 5.0
3.6 4.5
3.5 4.0
3.4 3.5
3.3 3.0
V
OUT
[V]
V
OUT
V
IN
t [s]
V
IN
[V]
4.0 6.5
2.5
1200−200 0 200 600
400 800 1000
3.2
3.9 6.0
3.8 5.5
3.7 5.0
3.6 4.5
3.5 4.0
3.4 3.5
3.3 3.0
V
OUT
[V]
V
OUT
V
IN
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
29
2. Characteristics of load transient response (Ta = +25°C)
2. 1 VOUT = 1.0 V
V
IN
= 2.0 V, C
IN
= C
L
= 1
μ
F, I
OUT
= 1 mA
↔
10 mA, t
r
= t
f
= 5.0
μ
s V
IN
= 2.0 V, C
IN
= C
L
= 1
μ
F, I
OUT
= 10 mA
↔
50 mA, t
r
= t
f
= 5.0
μ
s
t [s]
I
OUT
[mA]
1.5 75
125
1200200 0 200 600
400 800 1000
0.7
1.4 50
1.3 25
1.2 0
1.1
25
1.0
50
0.9
75
0.8
100
V
OUT
[V]
I
OUT
V
OUT
t [s]
I
OUT
[mA]
1.5 75
125
1200200 0 200 600
400 800 1000
0.7
1.4 50
1.3 25
1.2 0
1.1
25
1.0
50
0.9
75
0.8
100
V
OUT
[V]
I
OUT
V
OUT
2. 2 VOUT = 2.5 V
V
IN
= 3.5 V, C
IN
= C
L
= 1
μ
F, I
OUT
= 1 mA
↔
10 mA, t
r
= t
f
= 5.0
μ
s V
IN
= 3.5 V, C
IN
= C
L
= 1
μ
F, I
OUT
= 10 mA
↔
50 mA, t
r
= t
f
= 5.0
μ
s
t [s]
I
OUT
[mA]
3.0 75
125
600100 0 100 300
200 400 500
2.2
2.9 50
2.8 25
2.7 0
2.6
25
2.5
50
2.4
75
2.3
100
V
OUT
[V]
I
OUT
V
OUT
t [s]
I
OUT
[mA]
75
125
50
25
0
25
50
75
100
V
OUT
[V]
3.0
600100 0 100 300
200 400 500
2.2
2.9
2.8
2.7
2.6
2.5
2.4
2.3
I
OUT
V
OUT
2. 3 VOUT = 3.5 V
V
IN
= 4.5 V, C
IN
= C
L
= 1
μ
F, I
OUT
= 1 mA
↔
10 mA, t
r
= t
f
= 5.0
μ
s
V
IN
= 4.5 V, C
IN
= C
L
= 1
μ
F, I
OUT
= 10 mA
↔
50 mA, t
r
= t
f
= 5.0
μ
s
t [s]
I
OUT
[mA]
4.0 75
−
125
2400−400 0 400 1200
800 1600 2000
3.2
3.9 50
3.8 25
3.7 0
3.6
−
25
3.5
−
50
3.4
−
75
3.3
−
100
V
OUT
[V]
I
OUT
V
OUT
t [s]
I
OUT
[mA]
75
−
125
50
25
0
−
25
−
50
−
75
−
100
V
OUT
[V]
4800−800 0 800 2400
1600 3200 4000
4.0
3.2
3.9
3.8
3.7
3.6
3.5
3.4
3.3
I
OUT
V
OUT
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
30
3. Transient response characteristics of PMEN pin (Ta = +25°C)
3. 1 VPMOUT = VIN/2
V
IN
= 3.6 V, C
PM
= 220 nF, V
PMEN
= 0 V
↔
3.6 V, t
r
= t
f
= 1.0
μ
sV
IN
= 5.5 V, C
PM
= 220 nF, V
PMEN
= 0 V
↔
5.5 V, t
r
= t
f
= 1.0
μ
s
t [ms]
V
PMEN
[V]
10 6
6
12202 6
4810
2
V
PMOUT
[V]
4
0
6
2
84
2
0
2
4
V
PMEN
V
PMOUT
t [ms]
V
PMEN
[V]
10 6
6
12202 6
4810
2
V
PMOUT
[V]
4
0
6
2
84
2
0
2
4
V
PMEN
V
PMOUT
3. 2 VPMOUT = VIN/3
V
IN
= 3.6 V, C
PM
= 220 nF, V
PMEN
= 0 V
↔
3.6 V, t
r
= t
f
= 1.0
μ
sV
IN
= 5.5 V, C
PM
= 220 nF, V
PMEN
= 0 V
↔
5.5 V, t
r
= t
f
= 1.0
μ
s
t [ms]
V
PMEN
[V]
10 6
6
12202 6
4810
2
V
PMOUT
[V]
4
0
6
2
84
2
0
2
4
V
PMEN
V
PMOUT
t [ms]
V
PMEN
[V]
10 6
6
12202 6
4810
2
V
PMOUT
[V]
4
0
6
2
84
2
0
2
4
V
PMEN
V
PMOUT
4. Ripple rejection (Ta = +25°C)
4. 1 VOUT = 1.0 V
VIN = 2.0 V, CL = 1.0 μF
4. 2 VOUT = 2.5 V
VIN = 3.5 V, CL = 1.0 μF
Ripple Rejection [dB]
Frequency [Hz]
100 1k 10k10 1M
100k
0
100
90
80
70
60
50
40
30
20
10
IOUT = 50 mA
IOUT = 100 mA
IOUT = 10 mA
IOUT = 1 mA
Ripple Rejection [dB]
Frequency [Hz]
100 1k 10k10 1M
100k
0
100
90
80
70
60
50
40
30
20
10
IOUT = 50 mA
IOUT = 100 mA
IOUT = 10 mA
IOUT = 1 mA
4. 3 VOUT = 3.5 V
VIN = 4.5 V, CL = 1.0 μF
Ripple Rejection [dB]
Frequency [Hz]
100 1k 10k10 1M
100k
0
100
90
80
70
60
50
40
30
20
10
IOUT = 50 mA
IOUT = 100 mA
IOUT = 10 mA
IOUT = 1 mA
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
Rev.1.3_00 S-1740/1741 Series
31
5. Example of equivalent series resistance vs. Output current characteristics (Ta = +25°C)
100
0.01 100
I
OUT
[mA]
R
ESR
[Ω]
C
IN
= C
L
= 1.0
μ
F
0
Stable
100
−10 10
I
PMOUT
[
μ
A]
R
ESR
[Ω]
C
PM
= 0.1
μ
F
0
Stable
Figure 22 Figure 23
CIN
VIN
VSS
S-1740/1741
Series
A / C type
PMOUT
PMEN
CPM
*2
RESR
CL
*1
VOUT
RESR
CIN
VIN
VSS
S-1740/1741
Series
G type
PMOUT
CPM
*2
RESR
CL
*1
VOUT
RESR
*1. C
L: TDK Corporation C3216X7R1H105K160AB
*2. C
PM: TDK Corporation C2012X7R1H104K
*1. C
L: TDK Corporation C3216X7R1H105K160AB
*2. C
PM: TDK Corporation C2012X7R1H104K
Figure 24 Figure 25
5.5 V INPUT, 100 mA VOLTAGE REGULATOR WITH SUPPLY VOLTAGE DIVIDED OUTPUT
S-1740/1741 Series Rev.1.3_00
32
Power Dissipation
0 25 50 75 100 125 150 175
0.0
0.2
0.4
0.6
0.8
1.0
Ambient temperature (Ta) [C]
Power dissipation (P
D
) [W]
T
j
= 125C max.
SOT-23-5
B
A
0 25 50 75 100 125 150 175
0.0
0.2
0.4
0.6
0.8
1.0
Ambient temperature (Ta) [C]
Power dissipation (P
D
) [W]
T
j
= 125C max.
HSNT-6(1212)
B
A
Board Power Dissipation (PD) Board Power Dissipation (PD)
A 0.52 W A 0.43 W
B 0.63 W B 0.52 W
C − C −
D − D −
E − E −
0 25 50 75 100 125 150 175
0.0
0.2
0.4
0.6
0.8
1.0
Ambient temperature (Ta) [C]
Power dissipation (PD) [W]
Tj = 125C max.
HSNT-4(1010)
B
A
Board Power Dissipation (PD)
A 0.26 W
B 0.32 W
C −
D −
E −
(1)
1
2
3
4
(2)
1
2
3
4
Thermal via -
Material FR-4
Number of copper foil layer 4
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Thermal via -
Board B
Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Number of copper foil layer 2
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
-
-
74.2 x 74.2 x t0.070
Board A
Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Material FR-4
ICMountArea
SOT-23-3/3S/5/6 Test Board
No. SOT23x-A-Board-SD-2.0
ABLIC Inc.
(1)
1
2
3
4
(2)
1
2
3
4
Board A
Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Material FR-4
Number of copper foil layer 2
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
-
-
74.2 x 74.2 x t0.070
74.2 x 74.2 x t0.070
Thermal via -
Board B
Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Thermal via -
Material FR-4
Number of copper foil layer 4
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
ICMountArea
HSNT-6(1212) Test Board
No. HSNT6-A-Board-SD-1.0
ABLIC Inc.
(1)
1
2
3
4
(2)
1
2
3
4
Board B
Item Specification
Thermal via -
Material FR-4
Number of copper foil layer 4
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Size [mm] 114.3 x 76.2 x t1.6
2
Copper foil layer [mm]
Land pattern and wiring for testing: t0.070
-
-
74.2 x 74.2 x t0.070
Thermal via -
Material FR-4
Board A
Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Number of copper foil layer
ICMountArea
HSNT-4(1010) Test Board
No. HSNT4-B-Board-SD-1.0
ABLIC Inc.
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
2.9±0.2
1.9±0.2
0.95±0.1
0.4±0.1
0.16 +0.1
-0.06
123
4
5
No. MP005-A-P-SD-1.3
MP005-A-P-SD-1.3
SOT235-A-PKG Dimensions
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
ø1.5 +0.1
-0 2.0±0.05
ø1.0 +0.2
-0 4.0±0.1 1.4±0.2
0.25±0.1
3.2±0.2
123
45
No. MP005-A-C-SD-2.1
MP005-A-C-SD-2.1
SOT235-A-Carrier Tape
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY. 3,000
No. MP005-A-R-SD-1.1
MP005-A-R-SD-1.1
SOT235-A-Reel
Enlarged drawing in the central part
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
HSNT-6-B-PKG Dimensions
PM006-A-P-SD-1.1
No. PM006-A-P-SD-1.1
13
6
0.40
1.20±0.04
4
0.40 0.38±0.02
0.08 +0.05
-0.02
0.20±0.05
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.
1.00±0.05
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
PM006-A-C-SD-2.0
Feed direction
4.0±0.1
4.0±0.1
ø1.5
ø0.5
1.32±0.05
0.50±0.05
0.25±0.05
1
3
46
No. PM006-A-C-SD-2.0
2.0±0.05
+0.1
-0
+0.1
-0
HSNT-6-B-Carrier Tape
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
QTY. 5,000
No. PM006-A-R-SD-1.0
PM006-A-R-SD-1.0
mm
HSNT-6-B-Reel
11.4±1.0
9.0
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
+1.0
- 0.0
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
HSNT-6-B
-Land Recommendation
PM006-A-L-SD-2.0
No. PM006-A-L-SD-2.0
Land Pattern
Metal Mask Pattern
1.04min.
0.40±0.02
0.24min.
(1.22)
0.40±0.02
1.02
Caution It is recommended to solder the heat sink to a board
in order to ensure the heat radiation.
PKG
Aperture ratio
Aperture ratio
100%
40%
t0.10mm ~ 0.12 mm
Caution Mask aperture ratio of the lead mounting part is 100%.
Mask aperture ratio of the heat sink mounting part is 40%.
Mask thickness: t0.10mm to 0.12 mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
HSNT-4-B-PKG Dimensions
PL004-A-P-SD-1.1
No. PL004-A-P-SD-1.1
12
4
0.20±0.05
0.65
1.00±0.04
3
0.38±0.02
0.08+0.05
-0.02
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
PL004-A-C-SD-2.0
Feed direction
4.0±0.05
ø1.5
ø0.5
1.12±0.05 0.5±0.05
0.25±0.05
1
2
34
No. PL004-A-C-SD-2.0
2.0±0.05
+0.1
-0
+0.1
-0
HSNT-4-B-Carrier Tape
2.0±0.05
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
QTY. 10,000
No. PL004-A-R-SD-1.0
PL004-A-R-SD-1.0
mm
HSNT-4-B-Reel
11.4±1.0
9.0
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
+1.0
- 0.0
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
HSNT-4-B
-Land Recommendation
PL004-A-L-SD-2.0
No. PL004-A-L-SD-2.0
0.38~0.48
0.30min.
(1.02)
0.65±0.02
Land Pattern
Metal Mask Pattern
Caution It is recommended to solder the heat sink to a board
in order to ensure the heat radiation.
PKG
0.38~0.48
0.07
Aperture ratio
Aperture ratio
100%
40%
t0.10mm ~ 0.12 mm
Caution Mask aperture ratio of the lead mounting part is 100%.
Mask aperture ratio of the heat sink mounting part is 40%.
Mask thickness: t0.10mm to 0.12 mm
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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