SLVS367A - MARCH 2001 - REVISED JUNE 2001 FEATURES D Integrated Drive Regulator (4 V to 14 V) D Adjustable/Adaptive Dead-Time Control D 4-A Peak current at VDRV of 14 V D 10-V to 15-V Supply Voltage Range D TTL-Compatible Inputs D Internal Schottky Diode Reduces Part Count D Synchronous or Nonsynchronous Operation D Inverting and Noninverting Options D TSSOP PowerPad Package for Excellent Thermal Performance APPLICATIONS D Single or Multiphase Synchronous-Buck Power Supplies D High-Current DC/DC Power Modules The devices feature VDRV to PGND shootthrough protection with adaptive/adjustable deadtime control. The deadtime, for turning on the high-side FET from LOWDR transitioning low, is adjustable with an external capacitor on the DELAY pin. This allows compensation for the effect the gate resistor has on the synchronous FET turn off. The adaptive deadtime prevents the turning on of the low-side FET until the voltage on the BOOTLO pin falls below a threshold after the high-side FET stops conducting. The high-side drive can be configured as a ground referenced driver or a floating bootstrap driver. The internal Schottky diode minimizes the size and number of external components needed for the bootstrap driver circuit. Only one external ceramic capacitor is required to configure the bootstrap driver. DESCRIPTION The TPS2838/39/48/49 devices are MOSFET drivers designed for high-performance synchronous power supplies. The drivers can source and sink up to 4-A peak current at a 14-V drive voltage. These are ideal devices to use with power supply controllers that do not have on-chip drivers. The low-side driver is capable of driving loads of 3.3 nF in 10-ns rise/fall times and has 40-ns propagation delays at room temperature. The MOSFET drivers have an integrated 150-mA regulator, so the gate drive voltage can be optimized for specific MOSFETs. The TPS2848 and TPS2849 have a fixed 8-V drive regulator, while the TPS2838/39 allow the drive regulator to be adjusted from 4 V to 14 V by selection of two external resistors. TPS2838, TPS2839 PWP PACKAGE (TOP VIEW) ENABLE IN PWRRDY DELAY SYNC ADJ DT AGND 1 16 2 15 3 14 4 Thermal 13 Pad 5 12 6 11 7 10 8 9 TPS2848, TPS2849 PWP PACKAGE (TOP VIEW) BOOT HIGHDR BOOTLO VCC VDRV LOWDR NC PGND ENABLE IN PWRRDY DELAY NC DT ACTUAL SIZE AGND (5,1 mm x 6,6 mm) ACTUAL SIZE (5,1 mm x 6,6 mm) 1 14 2 13 3 12 Thermal 4 Pad 11 5 10 6 9 7 8 BOOT HIGHDR BOOTLO VCC VDRV LOWDR PGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. !"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0 $#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'( ('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+ '+('!5 #" &.. ,&$&%+'+$(0 Copyright 2001, Texas Instruments Incorporated www.ti.com 1 SLVS367A - MARCH 2001 - REVISED JUNE 2001 description (continued) The SYNC pin can be used regardless of load to disable the synchronous FET driver and operate the power supply nonsynchronously. A power ready/undervoltage lockout function outputs the status of the VCC-pin voltage and driver regulator output on the open-drain PWRRDY pin. This feature can be used to enable a controller's output once the VCC voltage reaches the threshold and the regulator output is stable. This function ensures both FET drivers are off when the VCC voltage is below the voltage threshold. The TPS2838/39/48/49 devices are offered in the thermally enhanced 14-pin and 16-pin PowerPAD TSSOP package. The PowerPAD package features an exposed leadframe on the bottom that can be soldered to the printed-circuit board to improve thermal efficiency. The TPS2838/48 are noninverting control logic while the TPS2839/49 drivers are inverting control logic. 2 www.ti.com SLVS367A - MARCH 2001 - REVISED JUNE 2001 functional block diagram (TPS2838, TPS2839) VCC ADJ VDRV Vr1 VCC 0.9 x Vref POR REFERENCES SYS_UVLO Vref PWRRDY Vr1 0.9 x Vref SHUTDOWN THERMAL SHUTDOWN DRIVE REGULATOR AGND BOOT SHUTDOWN HIGHDR IN BOOTLO INVERTING OPTION TPS2839 ONLY VDRV LOWDR SYNC SYS_UVLO DT ENABLE PGND DEADTIME CONTROL DELAY functional block diagram (TPS2848, TPS2849) VCC VDRV Vr1 VCC 0.9 x Vref POR REFERENCES SYS_UVLO Vref PWRRDY THERMAL SHUTDOWN DRIVE REGULATOR AGND Vr1 0.9 x Vref SHUTDOWN BOOT SHUTDOWN HIGHDR IN BOOTLO INVERTING OPTION TPS2849 ONLY VDRV LOWDR SYS_UVLO DT ENABLE DEADTIME CONTROL www.ti.com PGND DELAY 3 SLVS367A - MARCH 2001 - REVISED JUNE 2001 Terminal Functions NAME TERMINAL NO. DESCRIPTION TPS283x TPS284x ADJ 6 -- Adjust. The adjust pin is the feedback pin for the drive regulator (TPS283X only) AGND 8 7 Analog ground BOOT 16 14 Bootstrap. A capacitor is connected between the BOOT and BOOTLO pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 F and 1 F. BOOTLO 14 12 Boot low. This pin connects to the junction of the high-side and low-side MOSFETs. DELAY 4 4 Delay. Connecting a capacitor between this pin and ground adjusts the deadtime for high-side driver DT 7 6 Deadtime control. Connect DT to the junction of the high-side and low-side MOSFETs ENABLE 1 1 Enable. If ENABLE is low, both drivers are off. HIGHDR 15 13 High drive. This pin is the output drive for the high-side power MOSFET. IN 2 2 Input. This pin is the input signal to the MOSFET drivers. LOWDR 11 9 Low drive. This pin is the output drive for the low-side power MOSFET. NC 10 5 No internal connection PGND 9 8 Power ground. This pin is connected to the FET power ground. PWRRDY 3 3 Power ready. This open-drain pin indicates a power good for VDRV and VCC. SYNC 5 -- Synchronous rectifier enable. If SYNC is low, the low-side driver is always off; if SYNC is high, the low-side driver provides gate drive to the low-side MOSFET. VCC 13 11 Input power supply. It is recommended that a capacitor (minimum 1 F) be connected from VCC to PGND. Note that VCC must be 2 V higher than VDRV. VDRV 12 10 Drive regulator output voltage. It is recommended that a capacitor (minimum 1 F) be connected from VDRV to PGND. Note that VCC must be 2 V higher than VDRV. detailed description low-side driver The low-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 4 A, source and sink. high-side driver The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 4 A minimum, source and sink. The high-side driver can be configured as a GND-reference driver or as a floating-bootstrap driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum voltage that can be applied from BOOT to ground is 30 V. dead-time (DT) control Dead-time control prevents shoot-through current from flowing through the main power FETs during switching transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until the voltage at the junction of the power FETs (BOOTLO) is low. The TTL-compatible DT terminal connects to the junction of the power FETs. ENABLE The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a TTL-compatible digital terminal. 4 www.ti.com SLVS367A - MARCH 2001 - REVISED JUNE 2001 detailed description (continued) IN The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2838/48 have noninverting inputs; the TPS2839/49 have inverting inputs. On the TPS2838 and TPS2848, a high on IN results in a high on HIGHDR. On the TPS2839 and TPS2849, a high on IN results in a low on HIGHDR. SYNC (TPS283x only) The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the low-side FET is always off. SYNC is a TTL-compatible digital terminal. PWRRDY Depicts the status of the VCC pin voltage and the driver regulator output on the open-drain PWRRDY pin. DELAY Adjustable high-side turnon delay from from when the low-side FET is turned off. ADJ (TPS283x only) Input for adjusting the driver regulator output. See the application information section for the adjustment formula. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V Input voltage range: ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 30 V BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V ENABLE, IN, and SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V VDRV, PWRRDY, and DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Unless otherwise specified, all voltages are with respect to PGND. www.ti.com 5 SLVS367A - MARCH 2001 - REVISED JUNE 2001 DISSIPATION RATING TABLE TA 25C 2668 PACKAGE 14-pin PWP with solder DERATING FACTOR 26.68 mW/C TA = 70C 1467 TA = 85C 1067 14-pin PWP without solder 16-pin PWP with solder 1024 10.24 mW/C 563 409 2739 27.39 mW/C 1506 1095 16-pin PWP without solder 1108 11.08 mW/C 609 443 JUNCTION-CASE THERMAL RESISTANCE TABLE 14-pin PWP Junction-case thermal resistance 2.07 C/W 16-pin PWP Junction-case thermal resistance 2.07 C/W Test Board Conditions: 1. Thickness: 0.062I 2. 3I x 3I (for packages < 27 mm long) 3. 4I x 4I (for packages > 27 mm long) 4. 2-oz copper traces located on the top of the board (0,071 mm thick) 5. Copper areas located on the top and bottom of the PCB for soldering 6. Power and ground planes, 1-oz copper (0,036 mm thick) 7. Thermal vias, 0,33 mm diameter, 1,5 mm pitch 8. Thermal isolation of power plane For more information, refer to TI technical brief literature number SLMA002. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 10 15 V Input voltage, VI 10 29 V BOOT to PGND electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) supply current PARAMETER ICC Quiescent current TEST CONDITIONS V(ENABLE) = Low, V(ENABLE) = High, NOTE 2: Ensured by design, not production tested. 6 www.ti.com VCC = 13 V VCC = 13 V MIN TYP MAX UNIT 425 A 1 mA SLVS367A - MARCH 2001 - REVISED JUNE 2001 electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued) dead-time control PARAMETER TEST CONDITIONS MIN VIH(LOWDR) VIL(LOWDR) LOWDR high-level input voltage Over full VDRV range See Note 2 LOWDR low-level input voltage Over full VDRV range See Note 2 VIH(DT) VIL(DT) DT high-level input voltage Over full VCC range DT low-level input voltage Over full VCC range Deadtime delay V(VDRV) = 4 V to 14 V See Note 2 V(VDRV) = 4.5 V, TJ = 25C, See Note 2 0.5 V(VDRV) = 14.5 V, TJ = 25C, See Note 2 V(VDRV) = 4.5 V, CL(Delay) = 50 pF TJ = 25C, See Note 2 Driver nonoverlap time (DT to LOWDR) Driver nonoverlap time (LOWDR to HIGHDR) Driver nonoverlap time (LOWDR to HIGHDR) TYP MAX 50 UNIT %VDRV 1 V 2 V 1 1 V 1.5 ns/pF 30 150 ns 30 100 ns 75 180 V(VDRV) = 14.5 V, CL(Delay) = 50 pF TJ = 25C, See Note 2 58 125 V(VDRV) = 4.5 V, TJ = 25C, CL(Delay) = 0 pF See Note 2 50 125 V(VDRV) = 14.5 V, CL(Delay) = 0 pF TJ = 25C, See Note 2 30 100 ns ns NOTE 2: Ensured by design, not production tested. high-side driver PARAMETER Peak output current ro Output resistance TEST CONDITIONS MIN TYP V(BOOT) -V(BOOTLO) = 4 V, See Note 2 V(HIGHDR) = 0.5 V (src) V(HIGHDR) = 4 V (sink) 1 1.3 2 2.4 V(BOOT) -V(BOOTLO) = 8 V, See Note 2 V(HIGHDR) = 0.5 V (src) V(HIGHDR) = 8 V (sink) 2 2.4 2 3.3 V(BOOT) -V(BOOTLO) = 14 V, See Note 2 V(HIGHDR) = 0.5 V (src) V(HIGHDR) = 14 V (sink) 2 3.9 2 4.4 V(BOOT) -V(BOOTLO) = 4.5 V TJ = 25C V(HIGHDR) = 4 V (src) V(HIGHDR) = 0.5 V (sink) 45 V(BOOT) -V(BOOTLO) = 7.5 V, TJ = 25C V(HIGHDR) = 7 V (src) V(HIGHDR) = 0.5 V (sink) 26 V(BOOT) -V(BOOTLO) = 11.5 V, TJ = 25C V(HIGHDR) = 11 V (src) V(HIGHDR) = 0.5 V (sink) 20 HIGHDRV-to-BOOTLO resistor Rise and fall time (see Notes 2 and 3) CL = 10 nF, V(BOOTLO) = GND, TJ = 125C tPHL Propagation delay time, HIGHDR going low (excluding deadtime) V(BOOTLO) = GND, TJ = 125C, See Notes 2 and 3 V(BOOT)= 4 V V(BOOT)= 8 V V(BOOT)= 14 V V(BOOT)= 4 V UNIT A 6 5 4 250 CL = 3.3 nF, V(BOOTLO) = GND, TJ = 125C tr/tf MAX k 85 70 65 170 V(BOOT)= 8 V V(BOOT)= 14 V 140 V(BOOT) = 4 V V(BOOT)= 8 V 120 V(BOOT)= 14 V 80 ns 100 100 ns NOTES: 2: Ensured by design, not production tested. 3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. www.ti.com 7 SLVS367A - MARCH 2001 - REVISED JUNE 2001 electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued) low-side driver PARAMETER Peak output current ro Output resistance TEST CONDITIONS MIN TYP V(VDRV) = 4 V, TJ = 25C, See Note 2 V(LOWDR) = 0.5 V (src) V(LOWDR) = 4 V (sink) 1 1.6 2 2.4 V(VDRV) = 8 V, TJ = 25C, See Note 2 V(HIGHDR) = 0.5 V (src) V(HIGHDR) = 8 V (sink) 2 2.4 2 3.3 V(VDRV) = 14 V (src), TJ = 25C, See Note 2 V(HIGHDR) = 0.5 V (src) V(HIGHDR) = 14 V (sink) 2 3.9 2 4.4 V(VDRV) = 4.5 V, TJ = 25C V(LOWDR) = 4 V (src) V(LOWDR) = 0.5 V (sink) 30 V(VDRV) = 7.5 V, TJ = 25C V(LOWDR) = 7 V (src) V(LOWDR) = 0.5 V (sink) 25 V(VDRV)= 11.5 V, TJ = 25C V(LOWDR) = 11 V (src) V(LOWDR) = 0.5 V (sink) 22 TJ = 125C, Rise and fall time CL = 10 nF, See Note 2 tPLH Propagation delay time, LOWDR going high (excluding deadtime) A 7 TJ = 125C, TJ = 125C, See Notes 2 and 3 6 250 CL = 3.3 nF, See Note 2 UNIT 8 LOWDR-to-PGND resistor tr/tf MAX k V(VDRV) = 4 V V(VDRV) = 8 V 60 V(VDRV) = 14 V V(VDRV) = 4 V 40 50 110 ns V(VDRV) = 8 V V(VDRV) = 14 V 100 V(VDRV) = 4 V V(VDRV) = 8 V 110 ns 90 ns V(VDRV) = 14 V 80 80 ns NOTES: 2: Ensured by design, not production tested. 3: The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. VCC undervoltage lockout PARAMETER TEST CONDITIONS MIN TYP Start threshold voltage Stop threshold voltage Vhys tpd td Falling-edge delay time NOTE 2: Ensured by design, not production tested. 8 UNIT 10.3 V 7.5 Hysteresis voltage Propagation delay time MAX 1 50-mV overdrive, See Note 2 See Note 2 www.ti.com V 1.5 300 2 V 1000 ns 5 us SLVS367A - MARCH 2001 - REVISED JUNE 2001 electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued) digital control (IN, ENABLE, SYNC) PARAMETER VIH High-level input voltage VIL Low-level input voltage TEST CONDITIONS MIN TYP MAX UNIT IN Over full VCC range 2 V ENABLE, SYNC Over full VCC range 2.2 V IN Over full VCC range 1 ENABLE, SYNC Over full VCC range 1 V 7 s ENABLE propagation delay time NOTE 2: Ensured by design, not production tested. See Note 2 2 V thermal shutdown PARAMETER Thermal shutdown td Falling edge delay time NOTE 2: Ensured by design, not production tested. MIN TYP MAX UNIT See Note 2 TEST CONDITIONS 155 170 185 _C See Note 2 10 20 s drive regulator PARAMETER TEST CONDITIONS Recommended output voltage VO Vref Output voltage Reference voltage Dropout voltage Line regulation Load regulation Current limit Ilkg VCC = 10 V to 15 V, VCC = 10 V to 15 V IO = 5 mA to 150 mA VCC = 10 V, See Note 2 IO = 150 mA VCC = 10 V to 15 V, VCC = 10 V, IO = 5 mA IO = 5 mA to 150 mA PWRRDY saturation voltage VCC = 8 V IO = 5 mA Leakage current VI(PWRRDY) = 4.5 V MIN TYP MAX UNIT 4 14 V -2 2 %nom 1.235 1000 V 1100 0.2 %/V 2 0.5 mV % 0.6 A 0.8 V 1 A drive regulator undervoltage lockout PARAMETER Vhys tpd TEST CONDITIONS MIN Start threshold voltage See Note 2 Stop threshold voltage See Note 2 80 Hysteresis voltage See Note 2 2.5 Propagation delay time 50-mV overdrive, Falling-edge delay time See Note 2 Power on reset time NOTE 2: Ensured by design, not production tested. See Note 2 www.ti.com See Note 2 TYP MAX UNIT 85 %Vref %Vref 5 300 2 100 %Vref 1000 ns 5 s 1000 s 9 SLVS367A - MARCH 2001 - REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION Rising Edge VI (EN, SYNC, IN) Falling Edge 50% 50% toff ton VO (LOWDRV, HIGHDR) 50% 50% 50% VI (EN, SYNC, IN) toff ton 50% VO (LOWDRV, HIGHDR) 50% 50% High-Side and Low-Side Drive tf tr VO (LOWDRV, HIGHDR) 90% 90% 10% 10% Figure 1. Voltage Waveforms TYPICAL CHARACTERISTICS FALL TIME vs INPUT VOLTAGE (VDRV) RISE TIME vs INPUT VOLTAGE (VDRV) 70 35 CL = 3.3 nF TJ = 25C 50 30 t f - Fall Time - ns t r - Rise Time - ns 60 High Side 40 30 CL = 3.3 nF TJ = 25C Low Side 20 25 High Side 20 15 10 Low Side 10 5 0 0 4 5 6 7 9 10 11 12 13 8 VI - Input Voltage (VDRV) - V 14 15 5 6 7 8 9 10 11 12 13 VI - Input Voltage (VDRV) - V Figure 2 10 4 Figure 3 www.ti.com 14 15 SLVS367A - MARCH 2001 - REVISED JUNE 2001 TYPICAL CHARACTERISTICS RISE TIME vs JUNCTION TEMPERATURE FALL TIME vs JUNCTION TEMPERATURE 35 60 VDRV = 8 V CL = 3.3 nF VDRV = 8 V CL = 3.3 nF 30 50 High Side High Side t f - Fall Time - ns t r - Rise Time - ns 25 40 30 20 Low Side 10 20 15 Low Side 10 5 0 -50 -25 0 25 50 75 100 0 -50 125 CL = 3.3 nF TJ = 25C 160 140 High Side 100 80 60 Low Side 40 20 4 5 6 125 HIGH-TO-LOW PROPAGATION DELAY TIME vs INPUT VOLTAGE (VDRV) t PHL - High-to-Low Propagation Delay Time - ns t PLH - Low-to-High Propagation Delay Time - ns 200 0 100 Figure 5 LOW-TO-HIGH PROPAGATION DELAY TIME vs INPUT VOLTAGE (VDRV) 120 75 50 TJ - Junction Temperature - C Figure 4 180 25 0 -25 TJ - Junction Temperature - C 7 9 10 11 12 13 8 VI - Input Voltage (VDRV) - V 14 15 140 CL = 3.3 nF TJ = 25C 120 100 80 60 High Side 40 Low Side 20 0 4 5 6 7 8 9 10 11 12 13 14 15 VI - Input Voltage (VDRV) - V Figure 6 Figure 7 www.ti.com 11 SLVS367A - MARCH 2001 - REVISED JUNE 2001 TYPICAL CHARACTERISTICS 180 VDRV = 8 V CL = 3.3 nF 160 140 High Side 120 100 80 60 Low Side 40 20 0 -50 -25 25 75 0 50 100 TJ - Junction Temperature - C HIGH-TO-LOW PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE t PHL - High-to-Low Propagation Delay Time - ns t PLH - Low-to-High Propagation Delay Time - ns LOW-TO-HIGH PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE 125 80 VDRV = 8 V CL = 3.3 nF 70 High Side 60 50 Low Side 40 30 20 10 0 -50 -25 0 Figure 8 75 100 125 DRIVER-OUTPUT FALL TIME vs LOAD CAPACITANCE 1000 t f - Driver-Output Fall Time - ns 1000 VDRV = 8 V TJ = 25C t r - Driver-Output Rise Time - ns 50 Figure 9 DRIVER-OUTPUT RISE TIME vs LOAD CAPACITANCE 100 High Side 10 VDRV = 8 V TJ = 25C 100 High Side Low Side 10 Low Side 1 0.01 0.1 1 10 100 1 0.01 0.1 1 10 CL - Load Capacitance - nF CL - Load Capacitance - nF Figure 10 12 25 TJ - Junction Temperature - C Figure 11 www.ti.com 100 SLVS367A - MARCH 2001 - REVISED JUNE 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs INPUT VOLTAGE (VDRV) SUPPLY CURRENT vs INPUT VOLTAGE (VDRV) 10 25 CL = 50 pF TJ = 25C 9 20 7 ICC - Supply Current - mA 8 ICC - Supply Current - mA CL = 50 pF TJ = 25C 22.5 500 kHz 100 kHz 6 300 kHz 200 kHz 50 kHz 25 kHz 5 4 3 2 1 17.5 2 MHz 15 12.5 10 7.5 1 MHz 5 2.5 0 0 4 5 6 7 8 9 10 11 12 13 14 15 4 5 7 6 VI - Input Voltage (VDRV) - V Figure 12 10 11 12 13 14 15 PEAK SINK CURRENT vs INPUT VOLTAGE (VDRV) 5 4.5 TJ = 25C TJ = 25C 4.5 4 3.5 High Side Low Side Peak Sink Current - A Peak Source Current - A 9 Figure 13 PEAK SOURCE CURRENT vs INPUT VOLTAGE (VDRV) 4 8 VI - Input Voltage (VDRV) - V 3 2.5 High Side 2 1.5 1 3.5 3 Low Side 2.5 2 1.5 1 0.5 0.5 0 0 4 5 6 7 8 9 10 11 12 13 14 15 VI - Input Voltage (VDRV) - V 4 5 6 7 8 9 10 11 12 13 14 15 VI - Input Voltage (VDRV) - V Figure 14 Figure 15 www.ti.com 13 SLVS367A - MARCH 2001 - REVISED JUNE 2001 TYPICAL CHARACTERISTICS BOOTSTRAP SCHOTTKY DIODE INPUT CURRENT vs OUTPUT VOLTAGE START/STOP VCC UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE I I - Bootstrap Schottky Diode Input Current - mA Start/Stop VCC Undervoltage Lockout - V 10 9.8 Start 9.6 9.4 9.2 9 8.8 Stop 8.6 8.4 8.2 -50 -25 25 0 75 50 100 1200 TJ = 25C 1000 800 600 400 200 0 0 125 0.25 0.5 TJ - Junction Temperature - C Figure 16 1.5 1.75 2 200 VDRV = 8 V TJ = 25C 180 180 160 50 pF 160 10 pF 5 pF 140 20 pF 50 pF Delay Time - ns Dealy Time (Dead Time) - ns 1.25 DELAY TIME vs JUNCTION TEMPERATURE 200 120 100 80 60 10 pF 50 20 pF pF 5 pF 140 120 100 80 60 40 0 pF 40 1 pF 20 0 pF 1 pF 20 4 5 6 7 8 9 10 11 12 13 14 15 0 -50 -25 0 25 50 75 TJ - Junction Temperature - C VI - Input Voltage (VDRV) - V Figure 18 14 1 Figure 17 DELAY TIME (DEAD TIME) vs INPUT VOLTAGE (VDRV) 0 0.75 VO - Output Voltage - V Figure 19 www.ti.com 100 125 SLVS367A - MARCH 2001 - REVISED JUNE 2001 TYPICAL CHARACTERISTICS VDRV LOAD REGULATION VDRV LINE REGULATION 8.062 CL(VDRV) = 1 F TJ = 25C 8.061 CL(VDRV) = 1 F TJ = 25C 8.11 VO - Output Voltage - V VO - Output Voltage - V 8.115 8.06 8.059 8.058 8.057 8.105 8.1 8.095 8.09 8.056 8.055 10 11 12 13 14 8.085 -10 15 10 VCC - Supply Voltage - V 30 50 70 90 110 130 150 II - Input Current - mA Figure 20 Figure 21 APPLICATION INFORMATION Figure 22 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001ACD pulse-width-modulation (PWM) controller and a TPS2838 driver. The converter operates over an input range from 4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3-A continuous load. The converter achieves an efficiency of 94% for VIN = 5 V, IL=1 A, and 93% for VIN = 5 V, IL = 3 A. R1 (k) R2 (k) VDRV Voltage (V) 30 67 4 30 91 5 30 165 8 30 261 12 30 322 14.5 VDRV R2 ADJ R1 To set the regulator voltage (TPS2838/39) use the following equation: R2 + R1 1.235 VDRV * R1 www.ti.com 15 16 NOTES: SYNC PWRRDY ENABLE GND VIN J3 www.ti.com R1 1 k PGND NC LOWDR VDRV BOOTLO HIGHDR + OUT C5 1 F 5 SCP 1 DTC 7 R3 13.7 k RT 4 3 6 C7 0.1 F C28 1 F R2 4.7 R5 27.4 k Vfb See Note B C9 0.018 F L1 10 H R6 3.01 k C10 0.1 F C13 10 F + C12 220 F R7 1 k R8 100 C14 0.018 F C8 1000 pF R4 4.7 C11 390 pF Vphase See Note A Q1 IRF7201 VIN Figure 22. 3.3-V 3-A Synchronous-Buck Converter Circuit 8 GND FB COMP VCC 2 C1 1 F R21 30 k R22 165 k C3 1 F U2 TL5001ACD 9 10 11 12 13 14 15 16 C6 0.22 F A. Node Vphase generates RFI. Make this as contained as possible. B. Node Vphase is very sensitive. Make this as short as possible. fOSC = 400 kHz 7 DT 8 AGND 5 SYNC 6 ADJ 3 PWRRDY 4 DELAY 2 BOOT U1 TPS2838 R23 10 k 3 R20 10 k 4.5 V - 8 V 1 ENABLE 2 IN R24 10 R19 10 k + C4 100 F 1 2 C2 100 F + J1 1 R9 2.32 k R18 0 10 F + C15 L2 10 H 6 5 4 3 2 1 J3 3.3 V ANALOG ANALOG GND LOGIC GND 3.3 V LOGIC 5V BOOST 3.3 V SLVS367A - MARCH 2001 - REVISED JUNE 2001 SLVS367A - MARCH 2001 - REVISED JUNE 2001 APPLICATION INFORMATION Great care should be taken when laying out the PC board. The power-processing section is the most critical and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and C12 should also be connected to Q2 source. Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive traces. The bypass capacitor (C14) should be tied directly across VCC and PGND. The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible. The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply will be relatively free of noise. www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2838PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2838PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2839PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2839PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2848PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2848PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2849PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2849PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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