LTC3126 42V, 2.5A Synchronous Step-Down Regulator with No-Loss Input PowerPath Description Features n n n n n n n n n n n n n n n Seamless, Automatic Transition Between Two Input Power Sources Wide Input Voltage Range: 2.4V to 42V Wide Output Voltage Range: 0.818V to VIN Up to 2.5A Continuous Output Current Pin-Selectable Priority and Ideal Diode-OR Modes Burst Mode(R) Operation, IQ = 2A 95% Efficiency at 1A, VIN = 12V, VOUT = 5V 1A Current in Shutdown Programmable Input UVLO Thresholds Input Valid, Priority Channel and PGOOD Indicators 200kHz to 2.2MHz Fixed Frequency PWM Synchronizable to an External Clock Current Mode Control with 60ns Minimum On-Time Minimal External Components Thermally Enhanced 28-Lead 4mm x 5mm QFN and 28-Lead TSSOP Packages Applications n n n n Portable Industrial/Communications Test Equipment Battery and Supercapacitor Backup Power Automotive Power with Battery Backup Uninterruptible Power Supplies The LTC(R)3126 is a high efficiency synchronous buck converter with an internal no-loss PowerPathTM supporting seamless operation from two separate input power sources. Pin-selectable ideal diode-OR and priority input modes with user programmable undervoltage lockout thresholds provide full control over the transition between the input power sources. The fast, automatic switchover provided by the internal PowerPath eliminates the need for hold-up capacitors and minimizes disturbances on the output rail. An active input channel indicator and independent input and output power good signals provide complete feedback of the power system status. A wide 2.4V to 42V input voltage range, 2.5A output current capability and 2A Burst Mode operation quiescent current facilitate use of the LTC3126 with a wide variety of power sources including supercapacitors, automotive batteries, unregulated wall adapters and single to multicell stacks of most battery chemistries. Additional features include 1A current in shutdown, internal softstart and thermal protection. The LTC3126 is available in thermally enhanced 28-lead 4mm x 5mm QFN and 28-lead TSSOP packages. L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application 2MHz, 3.3V/2.5A Supply from Automotive and Battery Inputs 0.1F AUTOMOTIVE 10V TO 24V 42V TRANSIENT 15F + BATTERY 4.2V TO 24V + 4.7F 4.7F 499k 249k 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC ENA VREF PRIORITY VALID1 VSET1 VALID2 PGOOD 2.2H 10pF VOUT 3.3V 47F 2.5A 1.13M 374k Switchover to Battery Power, 2.5A Load VIN1 5V/DIV VIN2 5V/DIV AUTOMOTIVE INPUT UNPLUGGED VOUT 200mV/DIV INDUCTOR CURRENT 2A/DIV PRIORITY 5V/DIV VSET2 249k PWM/SYNC DIODE GND 50s/DIV PGND RT 3126 TA01b 16.5k 3126 TA01a 3126f For more information www.linear.com/LTC3126 1 LTC3126 Absolute Maximum Ratings (Note 1) PVIN1, PVIN2, VIN1, VIN2..............................................42V EXTVCC......................................................................42V VCC, PVCC.....................................................................6V VREF, VSET1, VSET2, FB, RT...........................................6V PWM/SYNC, DIODE, ENA............................................6V VALID1, VALID2, PGOOD, PRIORITY.............................6V BST1 Pin Above COM1................................................6V BST2 Pin Above COM2................................................6V Operating Junction Temperature Range (Notes 2, 4)............................................. -40C to 150C Storage Temperature.............................. -65C to 150C Lead Temperature (Soldering, 10 sec) TSSOP............................................................... 300C Pin Configuration TOP VIEW VIN2 1 28 VIN1 PWM/SYNC 2 27 PVIN1 VALID1 3 26 DIODE VALID2 4 25 BST1 VCC 5 24 COM1 PVCC 6 23 SW 19 PGND EXTVCC 7 18 PGND VSET1 8 17 SW VSET2 9 DIODE PVIN1 VIN1 VIN2 PWM/SYNC VALID1 TOP VIEW 28 27 26 25 24 23 VALID2 1 22 BST1 VCC 2 21 COM1 PVCC 3 20 SW EXTVCC 4 29 PGND VSET1 5 VSET2 6 29 PGND 22 PGND 21 PGND 20 SW VREF 7 16 COM2 VREF 10 19 COM2 GND 8 15 BST2 GND 11 18 BST2 ENA PVIN2 PRIORITY PGOOD FB RT 9 10 11 12 13 14 17 ENA 16 PVIN2 PGOOD 14 UFD PACKAGE 28-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 150C, JA = 34C/W EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB Order Information FB 12 RT 13 15 PRIORITY FE PACKAGE 28-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 30C/W EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB http://www.linear.com/product/LTC3126#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3126EUFD#PBF LTC3126EUFD#TRPBF 3126 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LTC3126IUFD#PBF LTC3126IUFD#TRPBF 3126 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LTC3126EFE#PBF LTC3126EFE#TRPBF LTC3126FE 28-Lead Plastic TSSOP (4.4mm) -40C to 125C LTC3126IFE#PBF LTC3126IFE#TRPBF LTC3126FE 28-Lead Plastic TSSOP (4.4mm) -40C to 125C LTC3126HFE#PBF LTC3126HFE#TRPBF LTC3126FE 28-Lead Plastic TSSOP (4.4mm) -40C to 150C LTC3126MPFE#PBF LTC3126MPFE#TRPBF LTC3126FE 28-Lead Plastic TSSOP (4.4mm) -55C to 150C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 3126f 2 For more information www.linear.com/LTC3126 LTC3126 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). PVIN1 = VIN1 = 24V, PVIN2 = VIN2 = 12V, VSET1 = VSET2 = GND, unless otherwise noted. PARAMETER CONDITIONS Input Operating Voltage After Start-Up l MIN VIN1, VIN2 UVLO Threshold VIN1/VIN2 Rising VIN1/VIN2 Falling l l VCC UVLO Threshold VCC Rising VCC Falling l VIN1 Current in Disable ENA Low, VIN1 = 24V, VIN2 = 12V ENA Low, VIN1 = 12V, VIN2 = 24V 1.35 0.55 A A VIN2 Current in Disable ENA Low, VIN2 = 24V, VIN1 = 12V ENA Low, VIN2 = 12V, VIN1 = 24V 1.35 0.55 A A VIN1 Current in Standby ENA High, Buck in UVLO, VIN1 = 24V, VIN2 = 12V ENA High, Buck in UVLO, VIN1 = 12V, VIN2 = 24V 1.65 0.55 A A VIN2 Current in Standby ENA High, Buck in UVLO, VIN2 = 24V, VIN1 = 12V ENA High, Buck in UVLO, VIN2 = 12V, VIN1 = 24V 1.65 0.55 A A VIN1 Current, Operating from VIN2 ENA High, Buck Operating, VIN1 = 24V, VIN2 = 27V 1.2 A VIN2 Current, Operating from VIN1 ENA High, Buck Operating, VIN2 = 24V, VIN1 = 27V 1.2 A Burst Mode Operation Quiescent Current from VIN Not Switching, VFB = 0.850V Oscillator Frequency Programmable Frequency RT Resistor = 33.2k PWM/SYNC Applied Clock Frequency 200 900 l 200 PWM/SYNC Low Pulse Width UNITS 42 V 2.50 2.34 2.6 2.4 V V 2.3 2.2 2.4 2.3 V V 1000 A 2200 1100 kHz kHz 2200 kHz 100 ns 150 Logic Input Threshold (ENA, DIODE, PWM/SYNC) ns l 0.3 0.8 1.1 V l 812 804 818 818 824 832 mV mV Feedback Voltage VIN1, VIN2 = 2.4V to 42V 0.2 Feedback Pin Current Feedback Pin Overvoltage Comparator Threshold MAX 5.5 l l PWM/SYNC High Pulse Width Feedback Voltage Line Regulation TYP 2.4 FB Rising, as a Percentage of the Feedback Voltage % -20 1 20 nA 7.4 9.8 12 % Feedback Pin Overvoltage Comparator Hysteresis 1.1 % Soft-Start Duration 7.5 ms PGOOD Threshold FB Falling, as a Percentage of the Feedback Voltage l -10.7 PGOOD Threshold Hysteresis PGOOD Delay FB Falling VREF Voltage l 0.995 0.982 -8.7 1 % s 1.000 1.000 1.005 1.018 1 VREF Current Limit 13 VIN1 Rising, VIN2 = 24V VIN1 Falling, VIN2 = 24V 280 VBEST Comparator Delay VIN1 Falling, VIN2 = 24V VIN2 Falling, VIN1 = 24V VIN1, VIN2 Input Valid Threshold, Rising VSET1 = VSET2 = 1000mV VSET1 = VSET2 = 500mV VSET1 = VSET2 = 250mV VSET1 = VSET2 = 150mV 365 19.8 9.9 4.9 2.91 20.0 10.0 5.0 3.0 mA V V 450 11 40 l l l l V V mA 24.18 23.83 VBEST Comparator Hysteresis % 200 VREF Output Current VBEST Comparator Threshold -6.6 mV s s 20.2 10.1 5.1 3.09 V V V V 3126f For more information www.linear.com/LTC3126 3 LTC3126 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). PVIN1, = VIN1 = 24V, PVIN2 = VIN2 = 12V, VSET1 = VSET2 = GND, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN1, VIN2 Input Valid Threshold, Falling VSET1 = VSET2 = 1000mV VSET1 = VSET2 = 500mV VSET1 = VSET2 = 250mV VSET1 = VSET2 = 150mV 17.57 8.77 4.34 2.57 17.75 8.86 4.43 2.65 17.93 8.95 4.52 2.73 V V V V VIN1, VIN2 Input Valid Threshold Hysteresis As a Percentage of the Rising Threshold 11 % VIN1, VIN2 Input Valid Comparator Delay VIN1/VIN2 Falling, 2V/s, VSET1/VSET2 = 1V VIN1/VIN2 Rising, 2V/s, VSET1/VSET2 = 1V 60 120 s s Open-Drain Output Voltage PGOOD, PRIORITY, VALID1, VALID2 Open-Drain Pull-Down Resistance PGOOD, PRIORITY, VALID1, VALID2 Open-Drain Leakage PGOOD, PRIORITY, VALID1, VALID2 5.5 70 High Side Switch Resistance Dropout Voltage 1 Low Side Switch Resistance 1A Load, VOUT = 3.3V V A 70 m 200 m 310 mV High Side Switch Current Limit (Note 3) 3.0 3.9 4.8 A Low Side Switch Current Limit (Note 3) 3.8 5.2 6.8 A Zero Cross Threshold PWM/SYNC = Low (Note 3) PWM/SYNC = High or Clocked (Note 3) 220 0 -3 mA mA SW Leakage Current VIN1 = VIN2 = PVIN1 = PVIN2 = 42V, VSW = 0V, 42V VCC Voltage IVCC = 1mA 4.12 VCC Current Limit VCC = 3.5V 35 67 mA VCC Drop-Out Voltage Powered from VIN1 or VIN2, VIN = 2.4V, ILOAD = 5mA Powered from EXTVCC, VEXTVCC = 3.3V, ILOAD = 5mA 70 100 mV mV VCC Load Regulation ILOAD = 1mA to 15mA 1.1 % EXTVCC Applied Voltage 4.22 3.15 EXTVCC Valid, Rising Threshold l EXTVCC Valid, Hysteresis 2.95 3 A 4.32 V 42 3.05 167 3.15 V V mV EXTVCC Current in Shutdown EXTVCC = 3.3V, ENA = Low 0.2 A EXTVCC Current Switching, fSW = 1MHz 8.8 mA 200 mV 46 ns 100 ns Frequency Foldback Threshold on FB SW Minimum On-Time VIN = 24V, 1A Load, EXTVCC = OPEN SW Minimum Low-Time SW Frequency Foldback Factor VFB < 0.2V 16 SW Frequency Divider in Drop-Out 8 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3126 is tested under pulsed load conditions such that TJ TA. The LTC3126E is guaranteed to meet specifications from 0C to 85C junction temperature. Specification over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3126I specifications are guaranteed over the -40C to 125C operating junction temperature range. The LTC3126H specifications are guaranteed over the -40C to 150C operating junction temperature range. The LTC3126MP specifications are guaranteed and tested over the -55C to 150C operating junction temperature range. High temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. Note 3: Current measurements are performed when the LTC3126 is not switching. The current limit values measured in operation will be somewhat higher due to the propagation delay of the comparators. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. 3126f 4 For more information www.linear.com/LTC3126 LTC3126 Typical Performance Characteristics Efficiency, VOUT = 3.3V, fSW = 700KHz Efficiency, VOUT = 5V, fSW = 700KHz 95 90 85 80 0.5 1.0 1.5 LOAD CURRENT (A) 2.0 85 80 70 0.0 0.5 1.0 1.5 LOAD CURRENT (A) 2.0 L = 4.7H PWM/SYNC = LOW 50 0.0 2.5 Efficiency, VOUT = 3.3V, fSW = 700KHz 100 90 90 80 80 80 70 70 40 30 L = 10H 20 0 0.0001 0.001 0.01 0.1 LOAD CURRENT (A) 1 60 PWM MODE 50 40 30 20 VIN = 12V VIN = 24V 10 10 0 0.0001 4 0.001 0.01 0.1 LOAD CURRENT (A) 10 80 80 70 50 PWM MODE 40 30 L = 2.2H 20 0.001 0.01 0.1 LOAD CURRENT (A) 1 3126 G07 0.001 0.01 0.1 LOAD CURRENT (A) 1 60 90 Efficiency, VOUT = 1.8V, fSW = 2MHz 70 Burst Mode OPERATION 50 PWM MODE 40 30 0 0.0001 4 L = 2.2H 80 VIN = 12V L = 2.2H 0.001 0.01 0.1 LOAD CURRENT (A) 1 60 50 Burst Mode OPERATION 40 30 PWM MODE 20 VIN = 12V VIN = 24V 10 4 VIN = 12V VIN = 24V 3126 G06 Efficiency, VOUT = 3.3V, fSW = 2MHz 20 VIN = 12V VIN = 24V 10 0 0.0001 EFFICIENCY (%) Burst Mode OPERATION L = 4.7H 0 0.0001 EFFICIENCY (%) 90 90 60 30 VIN = 12V VIN = 24V 4 PWM MODE 40 20 1 Burst Mode OPERATION 50 3126 G05 Efficiency, VOUT = 5V, fSW = 2MHz 70 60 L = 10H 3126 G04 100 2.5 70 Burst Mode OPERATION EFFICIENCY (%) EFFICIENCY (%) PWM MODE 50 2.0 Efficiency, VOUT = 1.8V, fSW = 700KHz 90 Burst Mode OPERATION 1.0 1.5 LOAD CURRENT (A) 3126 G03 100 60 0.5 3126 G02 Efficiency, VOUT = 5V, fSW = 700KHz EFFICIENCY (%) 70 L = 10H PWM/SYNC = LOW 3126 G01 EFFICIENCY (%) 80 60 75 2.5 VIN = 12V VIN = 24V 90 90 L = 10H PWM/SYNC = LOW 70 0.0 100 VIN = 12V VIN = 24V 95 EFFICIENCY (%) EFFICIENCY (%) 100 VIN = 12V VIN = 24V Efficiency, VOUT = 1.8V, fSW = 700KHz EFFICIENCY (%) 100 75 TA = 25C, unless otherwise noted. 10 4 3126 G08 0 0.0001 0.001 0.01 0.1 LOAD CURRENT (A) 1 4 3126 G09 3126f For more information www.linear.com/LTC3126 5 LTC3126 Typical Performance Characteristics Efficiency vs Switching Frequency VIN = 12V VIN = 24V 92 90 88 86 VOUT = 5V LOAD = 1A L = 10H 84 200 600 1000 1400 1800 SWITCHING FREQUENCY (kHz) 6 5 4 3 2 0 2200 20 VIN = 12V VIN = 24V 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 8 6 LOAD = 1A VOUT = 5V EXTVCC = VOUT L = 10H 0 200 600 1000 1400 1800 SWITCHING FREQUENCY (kHz) 1.2 0.8 0 45 fSW = 700kHz fSW = 2MHz 8 0 0.2 0.0 -0.2 -0.4 -0.6 LOAD = 1A VOUT = 5V 5 15 25 35 INPUT VOLTAGE (V) 45 -0.8 -1.0 0.0 80 0.2 70 -0.5 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 45 3126 G16 VIN - VCC (mV) 0.3 CHANGE IN VFB FROM 25C (%) 90 VOUT = 3.3V LOAD = 0.5A PWM/SYNC = HIGH 2.0 0.1 -0.0 -0.1 -0.2 VIN = 2.4V PWM/SYNC = HIGH 60 BUCK OPERATING IN REGULATION 50 40 30 -0.3 20 -0.4 10 -0.5 -50 -25 0 2.5 VCC LDO Voltage Drop vs Switching Frequency 100 -0.4 1.0 1.5 LOAD CURRENT (A) 3126 G15 0.4 -0.3 0.5 3126 G14 0.4 -0.2 45 0.4 0.5 -0.1 40 0.6 0.5 0.1 15 20 25 30 35 INPUT VOLTAGE (V) 0.8 FB Voltage vs Temperature -0.0 10 Load Regulation 12 Line Regulation 0.2 5 1.0 4 2200 0.3 0 3126 G12 EXTVCC Current vs Input Voltage 3126 G13 CHANGE IN VOUT FROM VIN = 24V (%) 40 CHANGE IN VOUT (%) 10 EXTVCC CURRENT (mA) EXTVCC CURRENT (mA) 12 2 1.6 0.4 16 14 4 ENA = LOW 3126 G11 EXTVCC Current vs Switching Frequency 16 Shutdown Current vs VIN 1 3126 G10 18 2.0 VOUT = 3.3V PWM/SYNC = LOW EXTVCC = VOUT 7 INPUT CURRENT (A) 94 EFFICIENCY (%) No-Load Input Current 8 INPUT CURRENT (A) 96 TA = 25C, unless otherwise noted. 25 50 75 100 125 150 TEMPERATURE (C) 3126 G17 0 200 BUCK OPERATING IN DROPOUT 600 1000 1400 1800 SWITCHING FREQUENCY (kHz) 2200 3126 G18 3126f 6 For more information www.linear.com/LTC3126 LTC3126 Typical Performance Characteristics 110 3 100 2 90 80 70 60 3000 SWITCHING FREQUENCY (kHz) 4 1 0 -1 -2 VIN = 2.5V ICC = 5mA 50 40 -50 -25 0 -4 25 50 75 100 125 150 TEMPERATURE (C) 0 4 8 12 ICC (mA) fSW = 700kHz fSW = 2MHz VOUT = 3.3V VIN = 24V ILOAD = 2A 0.4 0.8 1.2 VOLTAGE ON THE UNUSED INPUT (V) 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 -5.0 -50 -25 0 200 150 EXTVCC = OPEN VOUT = 3.3V LOAD = 1A 0 50 0 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 25 50 75 100 125 150 TEMPERATURE (C) 3126 G25 0 25 50 75 100 125 150 TEMPERATURE (C) 3126 G24 Temperature Rise vs Load Current 60 50 4.2 TEMPERATURE RISE (C) 44 BOTTOM SWITCH 100 4.5 HIGH SIDE CURRENT LIMIT (A) 60 SW MINIMUM ON-TIME (ns) 250 High Side Current Limit Threshold vs Temperature 48 TOP SWITCH 300 3126 G23 Minimum On-Time vs Temperature 52 3126 G21 350 3126 G22 56 200 300 100 Power Switch Resistance vs Temperature -4.0 1.6 20 RT (k) POWER SWITCH RESISTANCE (m) 0.5 10 3126 G20 4.0 1.0 40 -50 -25 100 20 5.0 1.5 CHANGE IN FSW FROM 25C (%) CURRENT OUT OF THE UNUSED INPUT (mA) 16 Switching Frequency vs Temperature Reverse Current Out of the Unused Input (VIN1 or VIN2) 0 1000 -3 3126 G19 0 Switching Frequency vs RT VCC Load Regulation 120 CHANGE IN VCC (%) VCC DROPOUT VOLTAGE (mV) VCC Dropout Voltage vs Temperature TA = 25C, unless otherwise noted. 3.9 3.6 3.3 3.0 -50 VIN = 12V VIN = 24V VIN = 36V 40 30 20 fSW = 1MHz VOUT = 3.3V ON DEMO PCB 10 0 50 100 TEMPERATURE (C) 150 3126 G26 0 0.5 1 1.5 2 LOAD CURRENT (A) 2.5 3126 G27 3126f For more information www.linear.com/LTC3126 7 LTC3126 Typical Performance Characteristics Temperature Rise vs Load Current 40 800 VIN = 12V VIN = 24V 30 20 fSW = 2MHz VOUT = 3.3V ON DEMO PCB 10 1 1.5 2 LOAD CURRENT (A) 600 500 400 300 200 fSW = 1MHz VIN = 3.3V VOUT = 3.3V 100 0 0.0 2.5 0.5 1.0 1.5 LOAD CURRENT (A) 2.0 3126 G28 25 250mA TO 2.5A LOAD VOUT = 5V VOUT = 1.8V VOUT = 3.3V, EXTVCC = VOUT VOUT = 3.3V, EXTVCC = OPEN fSW = 700kHz, L = 4.7H fSW = 1MHz, L = 3.3H fSW = 2MHz, L = 2.2H 600 400 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 45 0.0 -0.4 -1.2 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3126 G32 3126 G33 Load Step, 0.5A to 1.5A LOAD CURRENT 1A/DIV INDUCTOR CURRENT 200mA/DIV INDUCTOR CURRENT 1A/DIV VOUT 50mV/DIV 24V TO 5V AT 1A L = 2.2H fSW = 2MHz 45 0.4 Switching Waveforms, Burst Mode Operation 3126 G34 40 -0.8 Switching Waveforms, PWM Mode SW 10V/DIV 20 25 30 35 INPUT VOLTAGE (V) 0.8 VOUT = 3.3V 3126 G31 INDUCTOR CURRENT 500mA/DIV 15 VREF vs Temperature 200 5 600 800 1000 1200 1400 1600 1800 2000 2200 SWITCHING FREQUENCY (kHz) 10 3126 G30 CHANGE FROM 25C (%) LOAD CURRENT (mA) 30 5 1.2 800 35 200ns/DIV 10 0 2.5 1000 40 10 20 Burst Mode Operation Threshold vs Input Voltage 45 15 30 3126 G29 Maximum Input Voltage without Pulse Skipping 20 LOAD CURRENT (mA) 40 0 0.5 fSW = 700kHz L = 4.7H VOUT = 5V PWM/SYNC = HIGH 700 DROPOUT VOLTAGE (mV) 50 TEMPERATURE RISE (C) Minimum Load for Full Frequency Switching (No Pulse Skipping) Dropout Voltage vs Load Current 60 INPUT VOLTAGE (V) TA = 25C, unless otherwise noted. VOUT 100mV/DIV 10s/DIV 24V TO 5V AT 25mA L = 2.2H fSW = 2MHz COUT = 47F 3126 G35 100s/DIV FRONT PAGE APPLICATION 3126 G36 3126f 8 For more information www.linear.com/LTC3126 LTC3126 Typical Performance Characteristics Load Step, 0.5A to 2.5A Start-Up Waveforms ENA 5V/DIV LOAD CURRENT 2A/DIV VALID1 5V/DIV INDUCTOR CURRENT 2A/DIV VOUT 2V/DIV VOUT 200mV/DIV PGOOD 5V/DIV 3126 G37 100s/DIV FRONT PAGE APPLICATION 2ms/DIV FRONT PAGE APPLICATION VIN VIN, VOUT 2V/DIV 50ms/DIV VIN1 VIN1, VIN2 5V/DIV VOUT INDUCTOR CURRENT 500mA/DIV VIN2 PRIORITY 5V/DIV IIN2 500mA/DIV IIN1 500mA/DIV VOUT 100mV/DIV 3126 G39 50ms/DIV 10 LOAD VOUT = 5V 10 LOAD VOUT = 5V Priority Mode Transition Hot Plug of Automotive Input, VIN1 VIN2 VSET1 THRESHOLD VIN1 PRIORITY 5V/DIV IIN2 200mA/DIV IIN1 200mA/DIV VOUT 100mV/DIV 3126 G38 Ideal Diode Mode Transition Start-Up Dropout Performance VIN1, VIN2 10V/DIV TA = 25C, unless otherwise noted. 3126 G40 VIN1 VIN1, VIN2 10V/DIV VIN2 VOUT 100mV/DIV SW 10V/DIV 50ms/DIV 10 LOAD VIN2 = 10V VOUT = 3.3V 3126 G41 20s/DIV FRONT PAGE APPLICATION 1A LOAD VIN1 = 13.8V VIN2 = 6V 3126 G42 3126f For more information www.linear.com/LTC3126 9 LTC3126 Pin Functions (QFN/TSSOP) VCC, PVCC (Pins 2, 3/Pins 5, 6): Internal Linear Regulator Output and Power Supply for the Low Voltage Control Circuitry in the IC. Internal linear regulators generate a regulated voltage on these pins from either VIN1, VIN2 or EXTVCC. VCC and PVCC must be connected together in the application. A 4.7F or larger bypass capacitor must be connected between these pins and ground. The VCC rail remains powered in shutdown and can be used to supply up to 1mA to external loads. EXTVCC (Pin 4/Pin 7): VCC Regulator Bootstrapping Pin. If this pin is forced to 3.15V or greater then EXTVCC will be used to power the internal VCC rail. Typically, the EXTVCC input is connected to the buck converter output voltage. Bootstrapping the internal VCC rail in this fashion provides a significant efficiency advantage and reduced quiescent current especially in applications with high input voltage and low output voltage. If the EXTVCC pin is left open then the VCC rail will be powered from the VIN1 and VIN2 pins. VSET1, VSET2 (Pins 5, 6/Pins 8, 9): Programming Pins for the UVLO Thresholds on VIN1 and VIN2. The voltage on the VSET1 and VSET2 pins programs the UVLO threshold for the power source inputs VIN1 and VIN2, respectively. A voltage between zero and 1V programs a corresponding UVLO threshold between zero and 20V. However, there is also a fixed internal UVLO threshold (typically 2.34V) on each input which is always in effect. The voltage on VSET1,2 can be set using a resistor divider from the accurate reference output, VREF. Grounding VSET1,2 will allow the respective input VIN1,2 to be used down to the fixed, internal UVLO threshold. VREF (Pin 7/Pin 10): Voltage Reference Output for Powering Resistor Dividers to Set the VSET1 and VSET2 Inputs. The voltage at this pin is regulated by the IC to maintain a high precision, temperature stable 1.0V output. Resistive dividers from the VREF pin can be used to set the voltage at the VSET1 and VSET2 pins and thereby program the UVLO threshold for each input. The VREF output may also be used as a general purpose voltage reference in the application, providing a temperature stable reference for comparators, DACs or other functions. The total current drawn from this pin must be limited to 1mA and the total capacitive load should be limited to 470pF. If this pin is not used in the application (i.e., if there is no resistor from VREF to ground) then the VREF pin must be connected to VCC. GND (Pin 8/ Pin 11): Signal Ground. This pin is the ground connection for the control circuitry of the IC and must be tied to ground. FB (Pin 9/Pin 12): Feedback Voltage Input. A resistor divider connected to this pin establishes the output voltage of the buck converter. Care should be taken in the routing of connections to this pin in order to minimize stray coupling to the SW, BST1, BST2, COM1 and COM2 pins. RT (Pin 10/Pin 13): Switching Frequency Programming Pin. A resistor placed from this pin to ground sets the switching frequency of the buck converter. PGOOD (Pin 11/Pin 14): Open-Drain Power Good Indicator for the Buck Converter Output Voltage. This output is driven low if the buck converter output voltage is more than 8.7% below the regulation voltage or more than 9.8% above the regulation voltage. The PGOOD pin is also driven low whenever the buck converter is disabled. The maximum voltage that can be applied to the PGOOD pin is 5.5V. PRIORITY (Pin 12/Pin 15): Open-Drain Output Indicating That the Priority Input (VIN1) Is Being Utilized. The PRIORITY pin is driven low if the part is enabled and the buck converter is operating from the priority input, VIN1. In disable (ENA low) the PRIORITY pull-down is disabled, allowing the pin to float. The maximum voltage that can be applied to the PRIORITY pin is 5.5V. PVIN2 (Pin 13/Pin 16): Secondary Power Source Input for the Buck Converter. In priority mode (DIODE pin low) the buck converter will only operate from this input if the priority input power source is under voltage. This pin must be bypassed with a 4.7F or larger ceramic capacitor to ground. If the PVIN2 input will be subjected to inductive shorts to ground, then a power Schottky diode must be added from ground to PVIN2 to prevent this pin from being driven below ground. ENA (Pin 14/Pin 17): Enable Input. Forcing the ENA pin low disables the input voltage comparators, the VREF pin driver and the buck converter. The VCC rail remains powered in disable and therefore ENA can be connected to VCC to 3126f 10 For more information www.linear.com/LTC3126 LTC3126 Pin Functions (QFN/TSSOP) continuously enable the part. The maximum voltage that can be applied to the ENA pin is 5.5V. PGND (Pins 18, 19, Exposed Pad Pin 29/Pins 21, 22, Exposed Pad Pin 29): Power Ground Connections. These pins must be connected to ground in the application. For optimal thermal performance, the backpad should be soldered to the PC board and the PC board should be designed with the maximum possible number of vias connecting the backpad to the ground plane. SW (Pins 17, 20/Pins 20, 23): Power Switch Inductor Connections. This pin should be connected to one side of the buck converter inductor. COM1, COM2 (Pins 16, 21/Pins 19, 24): Negative Termination for Charge Pump Capacitors. External 0.1F capacitors (with 5V rating or greater) must be connected between BST1 and COM1 and between BST2 and COM2. BST1, BST2 (Pins 15, 22/Pins 18, 25): High Side Gate Driver Supply Rails. External 0.1F capacitors (with 5V rating or greater) must be connected between BST1 and COM1 and between BST2 and COM2. These pins are used to generate a gate drive rail for the high side power devices. DIODE (Pin 23/Pin 26): Logic Input Used to Select Between Ideal Diode-OR and Priority Modes. The integrated power path allows operation from either of two input power sources, VIN1 or VIN2. An input is considered valid for use only if its voltage is above the UVLO threshold for that input as programmed by the respective voltage at the VSET1 or VSET2 pin. If DIODE is high then the part operates in ideal-diode mode and the buck converter will operate from the highest voltage valid input (VIN1 or VIN2). If DIODE is low then the part operates in priority mode and the buck converter will operate from VIN1 whenever it is valid and will switch to VIN2 only if VIN1 becomes invalid. In either mode, if both inputs are under voltage then the buck converter will be disabled. PVIN1 (Pin 24/Pin 27): Priority Power Source Input for the Buck Converter. In priority mode (DIODE pin low) the buck converter will preferentially operate from this input if both input power sources are valid (above their respective UVLO thresholds). This pin must be bypassed with a 4.7F or larger ceramic capacitor to ground. If the PVIN1 input will be subjected to inductive shorts to ground, then a power Schottky diode must be added from ground to PVIN1 to prevent this pin from being driven below ground. VIN1 (Pin 25/Pin 28): Priority Power Source Kelvin Connection. This pin must be bypassed with a 0.1F ceramic capacitor to ground. The VIN1 pin must be connected to PVIN1 in the application. VIN2 (Pin 26/ Pin 1): Secondary Power Source Kelvin Connection. This pin must be bypassed with a 0.1F ceramic capacitor to ground. The VIN2 pin must be connected to PVIN2 in the application. PWM/SYNC (Pin 27/Pin 2): PWM/Burst Mode Operation Control and External Synchronization Clock Input. Forcing this pin high causes the buck converter to operate in PWM mode. In PWM mode, the converter maintains fixed frequency operation over the widest range of load currents possible, leaving fixed frequency operation only at extremely light loads where the converter skips pulses to maintain regulation. Forcing the PWM/SYNC pin low causes the IC to utilize Burst Mode operation at light loads and automatically transition to PWM mode at higher load current. Burst Mode operation improves light load efficiency and significantly reduces no-load input quiescent current at the expense of modestly increased output voltage ripple. In addition, an external clock can be applied to the PWM/ SYNC pin for synchronization purposes. When synchronized to an external clock the buck converter operates in PWM mode (Burst Mode operation is disabled). VALID1, VALID2 (Pins 1, 28/Pins 3, 4): Open-Drain Outputs Indicating Whether the VIN1 and VIN2 Inputs Are Valid. When the part is enabled (ENA is high) VALID1 and VALID2 are driven low if the voltage at the VIN1 or VIN2 input is above the UVLO threshold set by the respective VSET1 or VSET2 pin. When the part is disabled (ENA is low) the VALID1 and VALID2 pull-downs are disabled allowing the pins to float. The maximum voltage that can be applied to the VALID1 and VALID2 pins is 5.5V. 3126f For more information www.linear.com/LTC3126 11 LTC3126 Block Diagram VSET1 VIN1 2.34V + - VIN2 2.34V 6 23 26 25 4 2 3 15 13 COM1 - + VALID1 VIN1 HIGHER - + UVLO2 7 12 RUN ON VIN1 ENA VIN1 VALID POWER PATH VALID2 ENA VIN2 VALID DIODE 28 1 VIN2 VIN1 TRIPLE INPUT LDO EXTVCC CURRENT LIMIT VCC PVCC GATE DRIVERS PVCC ZERO CURRENT BST1 SW + - 3.9A 0A + - SW 898mV 5.2A CLK OSCILLATOR PWM/SYNC MODE SELECTION PWM/BURST MODE OPER. (PWM MODE IF PWM/SYNC IS HIGH OR SWITCHING + - VREF CONTROL LOGIC OV 20 + - PGOOD 11 SLOPE COMPENSATION + + - + - 17 BUCK ENABLE BST2 RT + - FB 747mV FB + - 27 PRIORITY COM2 UVLO1 PGND 10 16 PVIN2 ENA CURRENT LIMIT 22 21 PVIN1 - + 0.05VIN2 VSET2 24 - + 0.05VIN1 + - 5 Pin numbers shown for QFN package FB 9 818mV FB 898mV 1.000V ENA ENA 14 NOTE: PVIN1 AND VIN1 MUST BE CONNECTED TOGETHER IN THE APPLICATION PVIN2 AND VIN2 MUST BE CONNECTED TOGETHER IN THE APPLICATION VCC AND PVCC MUST BE CONNECTED TOGETHER IN THE APPLICATION GND PGND PGND PGND 8 18 19 29 3126 BD Quick Reference This section of the data sheet contains all of the equations necessary for external component selection as well as key part usage notes all compiled into one location for ease of use. Switching Frequency The buck converter switching frequency, fSW, is set by the value of RT resistor connected between the RT pin and ground according to the following equation: RT = Table 1. RT Value for Common Switching Frequencies fSW RT 300kHz 110k 500kHz 66.5k 750kHz 44.2k 1.0MHz 33.2k 1.2MHz 27.4k 1.5MHz 22.1k 2.0MHz 16.5k 33.2MHz k fSW 3126f 12 For more information www.linear.com/LTC3126 LTC3126 Quick Reference Output Voltage Table 2. Recommended Minimum Inductor Values fSW = 750kHz The buck converter output voltage is set via a resistor divider connected to the FB pin as shown in Figure 1. In most applications, choosing RTOP equal to 1M represents a good trade-off between quiescent current and robustness against PCB leakage. RBOT can be determined by the following equation where VOUT is the desired output voltage: VOUT LTC3126 3.3H 3.3V 2.2H 1.8V 1.2H VOUT MINIMUM INDUCTOR VALUE 12V 6.0H 5V 2.5H 3.3V 1.8H 1.8V 1.0H fSW = 2MHz RBOT Figure 1. FB Resistor Divider Inductor Value If the buck converter will be operated at duty cycles greater than 50% (i.e., VIN < 2VOUT) then the inductor value must be equal or greater than LMIN as defined by the following equation: MHz VOUT * H fSW 2V 5V RFF 3126 F01 LMIN = 8.0H CFF FB GND MINIMUM INDUCTOR VALUE 12V fSW = 1MHz R TOP RBOT = VOUT - 1 0.818V RTOP VOUT VOUT MINIMUM INDUCTOR VALUE 12V 3.3H 5V 1.5H 3.3V 1.0H 1.8V 1.0H The peak-to-peak inductor ripple, IL, is given by the following equation. IL = VOUT VOUT 1- fSW *L VIN Output Capacitor The recommended minimum output capacitor, CMIN, is given below as a function of output voltage: CMIN = 1V 150F VOUT Table 3. Minimum Output Capacitor vs VOUT VOUT MINIMUM COUT 24V 10F 12V 22F 5V 33F 3.3V 47F 1.8V 100F 1.2V 150F 3126f For more information www.linear.com/LTC3126 13 LTC3126 Quick Reference VIN1, VIN2 UVLO Thresholds The VIN1 and VIN2 UVLO thresholds are set by the voltage on the VSET1 and VSET2 pins respectively. Each UVLO threshold can be set from a maximum of 20V down to the internal fixed UVLO threshold of 2.34V using a resistor divider from the VREF output as shown in Figure 2. The rising UVLO threshold is given by the following equation: R2 VUVLO1,2 = 20VSET1,2 = 20V R1+R2 Grounding the VSET1,2 pin will define the respective input as valid down to the fixed internal UVLO threshold of 2.34V. LTC3126 VSET1,2 R2 GND The open-drain outputs (PGOOD, PRIORITY, VALID1 and VALID2) are low voltage pins and cannot be pulled up to a voltage higher than 5.5V. PGOOD is forced low in disable. Logic Inputs Important Usage Notes 3126 F02 Figure 2. Input UVLO Threshold Divider External Synchronization Clock Frequency The buck converter can be synchronized to an external clock applied to the PWM/SYNC pin. The frequency of the external clock must be higher than the internal oscillator frequency as set by the RT pin. In order to accommodate the 10% possible variation in the oscillator frequency, the RT resistor should be chosen to set the internal oscillator frequency at least 10% below the lowest synchronization frequency. For example, to synchronize to an external 1MHz clock, RT should be picked to set the internal oscillator at 900kHz or lower. Feedforward Capacitor The feedforward capacitor, CFF, as shown in Figure 1 improves the noise robustness of the FB pin and adds a zero to the loop at the frequency fZERO given below: fZERO = Open-Drain Outputs The logic input pins (DIODE, ENA, PWM/SYNC) are low voltage pins and cannot be forced above 5.5V. To force any of these pins continuously high, the pin can be connected to VCC. VREF R1 capacitor can be utilized to reduce the zero frequency and improve the transient response and phase margin. As shown in Figure 1, a 10k feedforward resistor, RFF, can be added to improve noise immunity in applications with high output voltage ripple or a long distance between the resistor divider and VOUT. 1 2 *R TOP *CFF In most applications performance will be optimized if the zero frequency is set at approximately 16kHz. In applications with large output capacitance, a larger feedforward 1. PVIN1 and VIN1 must be connected together in the application. PVIN2 and VIN2 must be connected together in the application. PVIN1 and PVIN2 must each have a 4.7F or larger bypass capacitor installed and placed as close to the pin as possible. In addition, VIN1 and VIN2 should have a separate 0.1F bypass capacitor installed as close to the pin as possible. 2. The two SW pins must be connected together in the application. 3. VCC and PVCC must be connected together in the application and should be bypassed with a 4.7F or larger capacitor. 4. If the VREF pin is not used in the application (i.e., there is no resistor from VREF to GND) then the VREF pin must be connected to VCC. 5. If PVIN1 or PVIN2 can be driven below ground in the application, for example due to large inductive ringing at the input, then Schottky diodes must be installed from ground to PVIN1/PVIN2 to protect the LTC3126. 3126f 14 For more information www.linear.com/LTC3126 LTC3126 Operation The LTC3126 is a dual-input synchronous monolithic buck converter featuring the ability to operate from two different input power sources with voltage ranges from 2.4V to 40V. An integrated lossless power path eliminates the need for an external diode-OR circuit or another type of external power path enabling a complete multi-input power supply solution with higher efficiency, fewer components, lower quiescent current and reduced drop-out voltage. The LTC3126 integrates all of the control circuitry required to automatically transition between two input power sources based on user programmable UVLO thresholds and selectable ideal-diode and priority modes. These features allow the LTC3126 to serve as a complete single chip power supply solution from a variety of different power sources including automotive, wall adapter, USB/Firewire and a wide range of battery chemistries. In addition, the LTC3126 is ideally suited for capacitor backup supplies with its ability to automatically transition to a capacitive backup rail when primary power is interrupted. A low 1A quiescent current in disable and 2A operating current make the LTC3126 ideally suited for battery powered and automotive applications. PowerPath Operation The power path controls whether the buck converter operates from the VIN1 or VIN2 input based on programmable undervoltage lockout thresholds for each input. The UVLO architecture used by the LTC3126 eliminates the need to connect external resistor dividers directly to the input voltages thereby providing a substantial reduction in quiescent current. The VSET1 and VSET2 pins are used to set the undervoltage lockout thresholds for the two power source inputs VIN1 and VIN2 respectively. The UVLO threshold for each input can be independently set to any voltage from 20V down to the internal fixed UVLO threshold of 2.34V using an external resistor divider as shown in Figure 3. The VREF pin is regulated to a fixed, temperature stable 1.0V. An external resistor divider from the VREF pin is used to establish the voltage at the VSET1 and VSET2 pins. The programmed voltage at the VSET1,2 pin is compared to the respective input voltage (VIN1 or VIN2) scaled down through an internal resistor divider with a ratio of 20:1 to determine if that input is undervoltage. As a result, a voltage + - VREF VIN1,2 R1 VIN1,2 VIN 20 VSET1,2 2.34V - + 1.00V LTC3126 - + UVLO1,2 R2 3126 F03 Figure 3. Programming the UVLO Thresholds on VIN1 and VIN2 range of zero to 1V on the VSET1,2 corresponds to a UVLO threshold of zero to 20V on VIN1,2. In addition, there is a fixed internal minimum UVLO threshold of 2.34V which is always enforced independent of the programmed voltage on the VSET1 and VSET2 pins. To enable a channel down to this minimum UVLO threshold, the respective VSET1,2 pin can be simply connected to ground. The LTC3126 power path has two operational modes as determined by the state of the DIODE logic input. With DIODE high, the part utilizes ideal diode-OR mode and operates from the input that has the higher voltage (assuming both inputs are above their respective UVLO thresholds). If one input is in UVLO then the other input will be utilized. If both inputs are in UVLO then the buck converter will be disabled. With the DIODE input low, the part operates in priority mode whereby VIN1 is always given priority and is utilized as long as it is above its UVLO threshold. If VIN1 is in UVLO then VIN2 is utilized as long as it is not in UVLO. If both VIN1 and VIN2 are in UVLO then the buck converter is disabled. All current drawn from the VREF pin is supplied by one of the inputs, VIN1 or VIN2. If neither input is above its respective UVLO threshold, then this current will be drawn from the input with the higher voltage. Otherwise, this current will be drawn by the active channel as determined by the power path. The VREF pin current will be supplied by the EXTVCC pin if that pin is utilized and has a valid voltage present. The PRIORITY, VALID1 and VALID2 open-drain outputs provide feedback on the state of the power path. The VALID1 and VALID2 outputs indicate that the respective input is present and above its UVLO threshold. Specifically, 3126f For more information www.linear.com/LTC3126 15 LTC3126 Operation the VALID1 pin is driven low if the part is enabled (ENA is high) and VIN1 is above its UVLO threshold. The VALID2 pin is driven low if the part is enabled and VIN2 is above its UVLO threshold. The PRIORITY pin is driven low if the part is enabled and the buck converter is operating from the priority channel, VIN1. The PRIORITY pin provides the ability to determine which input is being utilized in idealdiode mode when both inputs are valid. The VCC rail stays powered even when the LTC3126 is disabled (ENA is low) as long as either VIN1 or VIN2 is powered. In this disabled state, the VCC output is powered from whichever input (VIN1 or VIN2) is higher in voltage independent of the state of the DIODE pin. Given that the VCC output remains powered in shutdown, the ENA pin can be connected to VCC to continuously enable the part. Buck Converter Operation The LTC3126 buck converter utilizes constant frequency switching with peak current mode control to provide low noise operation. The switching frequency can be set from 200kHz to 2.2MHz by appropriate choice of the RT pin resistor. In addition, the buck converter can be synchronized to an external clock applied to the PWM/SYNC pin. The buck converter always operates from a single input power source (VIN1 or VIN2) at any time. The input that is used is determined by the state of the DIODE input, the programmed UVLO thresholds and the voltage of each input as described in the PowerPath Operation section. Each switching cycle begins with the high side switch of the active input turning on. The high side switch remains on until the inductor current reaches the current level set by the output of the internally compensated error amplifier. At that point, the low side synchronous rectifier turns on and remains on for the remainder of the cycle or until the inductor current falls to zero. The error amplifier continuously adjusts the commanded current level to maintain regulation of the FB pin voltage. If PWM/SYNC is forced high or has an external clock applied, then the buck converter will operate in PWM mode. In PWM mode operation, the buck converter will maintain fixed frequency switching at all possible load currents, switching to pulse skipping only at very light load currents when the minimum on-time of the SW is reached. PWM mode provides low noise, fixed frequency operation and low output voltage ripple over the widest possible range of load currents and should be used when it is necessary to maintain the lowest possible noise levels. With PWM/ SYNC forced low, the converter will automatically transition to Burst Mode operation at light loads to increase efficiency and reduce no-load quiescent current. The LTC3126 buck converter is current limit protected to prevent damage to the IC during output overload and short-circuit conditions. If the inductor current exceeds the high side switch current limit threshold then the high side switch is turned off for the remainder of the cycle. If the inductor current exceeds the low side current limit threshold, then the high side switch will remain off during the next cycle to prevent increasing the inductor current further during the high side switch minimum on-time. In addition, the switching frequency is reduced by a factor of 16 if the FB voltage is below 200mV to ensure control of the inductor current is maintained during output overcurrent conditions. The internal circuitry of the buck converter including the gate drivers is powered from VCC. Internal LDOs generate the VCC rail from the active input, VIN1 or VIN2. In applications where the buck converter output is 3.3V or greater, the VCC rail can be bootstrapped by connecting the EXTVCC pin to the buck converter output. This allows a third LDO to generate the VCC rail directly from EXTVCC. Given that the buck converter has much greater efficiency than the LDOs, bootstrapping via the EXTVCC pin increases the efficiency of the converter and reduces its quiescent current. This is particularly the case for applications with high input voltage, low output voltage and high switching frequencies. 3126f 16 For more information www.linear.com/LTC3126 LTC3126 Applications Information Input UVLO Thresholds on VIN1, VIN2 The undervoltage lockout threshold for each input, VIN1 and VIN2, is set by the voltage on the VSET1 and VSET2 pins respectively. A voltage between 0V and 1V on VSET1,2 linearly programs a corresponding UVLO threshold of zero to 20V. There is also an additional internal minimum undervoltage lockout threshold of 2.34V on each input which is always in effect independent of the voltage at the VSET1,2 pins. To allow an input to operate fully down to the internal minimum UVLO threshold, the respective VSET1,2 pin can be connected to ground. In most applications, the voltage at the VSET1 and VSET2 pin is established using a resistor divider from the VREF pin as shown in Figure 4. The corresponding rising UVLO threshold is given by the following equation: VUVLO1,2 = 20VSET1,2 = 20V R2 R1+R2 When neither input is valid (above its respective UVLO threshold), the current drawn from the VREF pin will add directly to the quiescent current of the higher voltage input (VIN1 or VIN2). Therefore, use of large value resistors in the VSET1,2 divider string will reduce the quiescent current. However, larger value resistors also result in lower immunity to noise and leakage currents. A reasonable compromise in most applications is to utilize a total resistor string impedance of 1M. LTC3126 VSET1,2 R2 LTC3126 VSET1,2 R2 VSET2,1 R3 3126 F05 Figure 5. Setting Both Input UVLO Thresholds Using a Single Resistor String Resistor R3 can be chosen independently and selecting R3 equal to 200k is a reasonable starting choice for most applications. The value of R2 and R1 can then be determined from the following equations where VUVLOH is the undervoltage lockout threshold on the higher voltage channel and VULVOL is the UVLO threshold on the lower voltage channel: V R2 = R3 UVLOH - 1 VUVLOL 20 - 1 R1= (R2+R3) VUVLOH If the resulting total resistance through the resistor chain (R1 + R2 + R3) is larger or smaller then desired, the choice of R3 can be adjusted in the appropriate direction and the calculation for R2 and R1 can be repeated. Input Hold-Up Capacitance VREF R1 VREF R1 GND 3126 F04 Figure 4. Setting the Input UVLO Thresholds To minimize quiescent current and eliminate an external resistor it is also possible to set both UVLO thresholds via a single resistor string as shown in Figure 5. The upper resistor divider tap is connected to whichever pin, VSET1 or VSET2, requires the higher UVLO threshold. The LTC3126 features internal micropower UVLO comparators which minimize the quiescent current required by the application. However, due to their low operating current, the UVLO comparators exhibit a significant delay when responding to an undervoltage condition. Sufficient input hold-up capacitance must be provided to ensure the voltage on the utilized channel remains sufficient to power the buck converter until the transition to the secondary channel is completed. Consider the example illustrated in Figure 6 where the LTC3126 is being powered by the priority input (VIN1) at 12.8V and the UVLO threshold on the VIN1 channel is 3126f For more information www.linear.com/LTC3126 17 LTC3126 Applications Information programmed to 10V. At time t1, the priority input is unplugged and the buck converter begins discharging the input capacitor. At time t2, the UVLO threshold is reached but the buck converter remains operating from the priority channel due to the comparator delay. At time t3, after comparator delay tDELAY, the buck converter switches over to the secondary input (VIN2) and the input capacitor on VIN1 maintains its voltage since there is no longer any current being drawn on that channel. In this example, the input capacitor on VIN1 must be large enough that VIN1 remains at sufficient voltage to maintain the output voltage in regulation until time t3. If VIN1 is allowed to drop lower than the regulated output voltage then the buck converter output will temporarily lose regulation during the transition. tDELAY VIN1 CIN = 2 ( 3.3V ) ( 2.5A ) ( 60s ) 2 2 0.80[(10V ) - ( 4V ) ] = 14.7 s * A = 14.7F V Therefore, in this example a minimum capacitor value of 15F or greater must be utilized on VIN1 to maintain regulation of the buck converter output throughout the transition to the secondary channel. In practice, an additional guardband should be included to account for variations in component tolerances and delays. Soft-Start 10V IIN2 t1 t2 t3 3126 F06 Figure 6. Waveforms During Transition from VIN1 to VIN2 The required value of hold-up capacitance, CIN, can be estimated from the following equation where VOUT is the buck converter regulated output voltage, ILOAD is the buck converter load current, is the buck converter efficiency, VUVLO is the falling UVLO threshold of the active channel and VMIN is the minimum required input voltage needed for the buck converter to maintain regulation. CIN = + 700mV = 4V. Finally, assuming an efficiency of 80%, the minimum required input hold-up capacitance on the priority channel can be calculated as: 2VOUT *ILOAD * tDELAY ( VUVLO2 - VMIN2 ) In the example from Figure 6, the UVLO threshold, VUVLO, is 10V. The typical comparator delay of tDELAY = 60s is specified in the Electrical Characteristics section of this data sheet. For the sake of this example, consider a buck converter output voltage of 3.3V with a 2.5A load. The buck converter dropout voltage at 2.5A is approximately 700mV. Therefore, the minimum buck converter input voltage, VMIN, required to maintain regulation is 3.3V The LTC3126 incorporates an internal soft-start circuit with a nominal duration of 7.5ms. The soft-start is implemented by a linearly increasing ramp of the error amplifier reference voltage during the soft-start duration. As a result, the duration of the soft-start period is largely unaffected by the size of the output capacitor or the output regulation voltage. Given the closed-loop nature of the soft-start implementation, the converter is able to respond to load transients that occur during the soft-start interval. The soft-start period is reset by thermal shutdown, when the buck converter is disabled via the ENA pin and when both inputs are in UVLO. VREF Output The VREF output is a regulated, temperature stable 1.00V voltage reference. It is intended primarily to be used to establish the VSET1 and VSET2 pin voltages. However, it can also be used for other functions as long as the total current drawn from the pin is limited to 1mA or less. In addition to that restriction, there is also a maximum amount of capacitance that can be placed on the VREF pin in order to maintain suitable phase margin in the internal pin driver. The maximum recommended capacitance on the VREF pin is 470pF or less. If the VREF pin is not being used in the application (i.e., there is no resistor from VREF to GND) then the VREF pin should be connected to VCC. The VREF pin cannot be left floating. The VREF pin is only powered when the part is enabled (ENA is high). 3126f 18 For more information www.linear.com/LTC3126 LTC3126 Applications Information Buck Converter Switching Frequency The LTC3126 buck converter utilizes fixed-frequency PWM to achieve low output ripple and low noise operation. The switching frequency can be set from 200kHz to 2.2MHz by appropriate selection of the RT resistor placed between the RT pin and ground. See the Quick Reference section for details on selecting the value for RT. Higher switching frequencies facilitate the use of smaller inductors as well as smaller input and output capacitors which results in a smaller solution size and reduced component height. However, higher switching frequencies also generally reduce conversion efficiency due to increased switching losses. The on-time of the buck converter SW pin decreases as the step-down ratio from VIN to VOUT increases and as the switching frequency is increased. The minimum switch on-time, tON(MIN), is the smallest duration on-time that the SW pin can generate. If the required on-time is shorter than the minimum on-time then the part will pulse skip to maintain regulation. Although regulation of the output will be maintained, pulse skipping results in lower frequency switching and increased output voltage ripple. In order to avoid pulse-skipping operation, the switching frequency should be selected to be less than fSW(MAX) as given by the following equation where tON(MIN) is the minimum SW pin on time with a typical value of 60ns: fSW(MAX) = VOUT VIN * tON(MIN) The SW minimum on-time is a function of load current and temperature as shown in the Typical Performance Characteristics section. Input Capacitors To ensure proper functioning of the buck converter, minimize EMI and reduce input ripple, the PVIN1 and PVIN2 pins must each be connected to a low ESR bypass capacitor with a value of at least 4.7F. Ceramic capacitors with X5R or X7R dielectric are recommended. Each bypass capacitor must be located as close as possible to the respective pin and should connect to the ground plane via the shortest route possible. When powered through an inductive connection such as a long cable, the inductance of the power source and the input bypass capacitor form a High-Q resonant LC filter. In such applications, hot-plugging into a powered source can lead to a significant voltage overshoot, even up to twice the nominal input source voltage. Care must be taken in such situations to ensure that the absolute maximum input voltage rating of the LTC3126 is not violated. See Linear Technology Application Note 88 for solutions to increase damping in the input filter and minimize this voltage overshoot. The VIN1 and VIN2 pins provide power to the VCC regulator and other internal circuitry. Each of these pins should be connected to a 0.1F bypass capacitor located as close to the pin as possible. Buck Output Capacitor A low ESR capacitor should be utilized at the output of the buck converter in order to minimize output voltage ripple. For most applications, a ceramic capacitor with X5R or X7R dielectric is the optimal choice. There is also a minimum required output capacitor value as specified in the Quick Reference section. The crossover frequency of the voltage control loop increases with lower output capacitance and therefore a minimum capacitance value is required to limit the bandwidth and ensure stability of the voltage feedback loop. Given that the loop gain is dependent on the voltage divider ratio, the minimum required output capacitor is a function of the output voltage as well. At lower output voltages, the loop gain is higher and a larger output capacitor is required to maintain a fixed loop crossover frequency. The larger recommended output capacitance at low output voltages also helps to reduce the magnitude of voltage steps on load transients in proportion to the reduced output voltage rail in order to maintain a constant percentage deviation. Increasing the value of the buck converter output capacitor will decrease the bandwidth of the feedback loop. If the output capacitor gets too large, the crossover frequency may decrease too far below the compensation zero leading to degraded phase margin and underdamped transient response. In such cases, the phase margin and transient performance can be improved by increasing the size 3126f For more information www.linear.com/LTC3126 19 LTC3126 Applications Information of the feedforward capacitor in parallel with the upper resistor divider resistor to restore the full bandwidth of the feedback loop. Feedforward Resistor In applications where there is a long connection between the feedback resistor divider and the point at which the output voltage is sensed, it is recommended that a 10k feedforward resistor (RFF) be added in series with the feedforward capacitor as shown in Figure 7 below. The feedforward resistor prevents high frequency noise on the VOUT trace from coupling into the sensitive FB node. The addition of a 10k feedforward resistor will have little impact on the frequency response of the control loop since the divider pole location is dominated by the values of resistors RTOP and RBOT. LTC3126 RTOP VOUT RBOT 3126 F07 Figure 7. Feedforward Resistor (RFF) for Improved Noise Robustness Inductor Selection The choice of inductor value influences both the efficiency and the magnitude of the output voltage ripple. Larger inductance values will reduce inductor current ripple and will therefore lead to lower output voltage ripple. For a fixed DC resistance, a larger value inductor will yield higher efficiency via reduced RMS and core losses. However, a larger inductor within a given inductor family will generally have a greater series resistance, thereby counteracting this efficiency advantage. The peak-to-peak current ripple, IL, given by the following equation will be largest at the highest input voltage experienced in the application. IL = VOUT VOUT 1- fSW *L VIN High values of inductor ripple current will reduce the output current capability of the converter since higher ripple increases the peak switch current and will therefore trip the current limit at a lighter load current. The maximum output current is equal to the current limit minus half the peak-to-peak ripple current as shown in the following equation where ILIMIT is the threshold of the high side switch current limit: IOUT(MAX) =ILIMIT - CFF FB GND RFF 10k A reasonable choice for ripple current is IL = 1A which represents 33% of the minimum current limit. The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current in order to prevent core saturation and loss of efficiency during operation. To optimize efficiency the inductor should have a low DC resistance. As a general guideline, the inductor resistance (ESR) should be approximately equal to the low side switch resistance (70m) or less. IL 2 In addition, there is a minimum inductor value required to maintain stability of the current loop as determined by the fixed internal slope compensation. Specifically, if the buck converter is going to be utilized at duty cycles over 50%, the inductance value must be at least equal to LMIN as given by the following equation: LMIN = MHz VOUT * H fSW 2V To ensure sufficient slope compensation if the external synchronization feature is being used, the inductor must be sized for the lowest possible switching frequency the part will experience which is determined by the internal oscillator frequency. PGOOD Output The open-drain PGOOD output is driven low whenever FB is more than +9.8%/-8.7% (typical) from the FB reference voltage. The PGOOD output is also driven low whenever the buck converter is disabled. The maximum voltage that can be applied to the PGOOD output is 5.5V. The PGOOD comparator has a deglitching delay of approximately 200s. 3126f 20 For more information www.linear.com/LTC3126 LTC3126 Applications Information VCC Regulators and Bootstrapping with EXTVCC The VCC rail powers the internal control circuitry and power device gate drivers of the LTC3126. Two internal low dropout linear regulators provide the ability to generate this rail from either VIN1 or VIN2. When the IC is disabled (ENA low) the VCC rail is powered by the higher voltage input, VIN1 or VIN2, regardless of the state of the VSET1, VSET2 and DIODE pins. When the IC is enabled, the input voltage comparators on the VSET1 and VSET2 pins become active and the VCC rail will be powered by the active channel. In ideal diode mode (DIODE high) the active channel is the valid input with the higher voltage. In priority mode (DIODE low) the active channel is VIN1 if VIN1 is valid or VIN2 otherwise (assuming it is valid). If both VIN1 and VIN2 are in UVLO then the higher voltage input will be utilized to power the VCC rail. A third linear regulator allows the VCC rail to be powered via the EXTVCC pin which can be connected to the buck converter output or an auxiliary rail with a voltage above 3.15V. When operating at high input voltages, the losses in the VCC regulator powered from the input voltage can become a significant factor in conversion efficiency and can even become a substantial source of power dissipation. A significant performance improvement can be obtained by connecting the EXTVCC input to the buck converter output so that the gate drive current is provided through the high efficiency buck converter rather than the less efficient linear regulator. This is of particular benefit at higher input voltages, lower output voltages and higher switching frequencies. The EXTVCC pin is only utilized to power the VCC rail when the buck converter is operating. Thermal Considerations The LTC3126 is designed to operate continuously up to its full rated 2.5A output current. However, when operating at high current levels there will be significant heat generated within the IC. In addition, in many applications the VCC regulator is operated with large input-to-output voltage differential resulting in significant levels of power dissipation in its pass element which can add significantly to the total power dissipated within the IC. To ensure full output current capability and optimal efficiency, careful consideration must be given to the thermal environment of the IC. This is even more important in applications that function over an extended ambient temperature range. Specifically, the exposed die attach pad of both the QFN and TSSOP packages must be soldered to the PC board and the PC board should be designed to maximize the conduction of heat out of the IC package. This can be accomplished by utilizing multiple vias from the die attach pad connection to other PCB layers containing a large area of exposed copper. If the die temperature exceeds approximately 170C, the IC will enter overtemperature shutdown and all switching will be inhibited. The part will remain disabled until the die cools by approximately 10C. The soft-start circuit is re-initialized in overtemperature shutdown to provide a smooth recovery when the fault condition is removed. PCB Layout Guidelines The LTC3126 buck converter switches large currents at high frequencies. Special attention must be paid to the PC board layout to ensure a stable, noise-free and efficient application circuit. Figures 6 and 7 show representative PC board layouts for each package option to outline some of the primary considerations. A few key guidelines are listed below. 1. The parasitic inductance and resistance of all circulating high current paths should be minimized. This can be accomplished by keeping the routes to the inductor, output capacitor and PVIN1/2 bypass capacitors as short and as wide as possible. Capacitor ground connections should via down to the ground plane by way of the shortest route possible. The bypass capacitors on PVIN1, PVIN2 and VCC should be placed as close to the IC as possible and should have the shortest possible return paths to ground. 2. The exposed pad in both packages provides one of the primary paths for heat generated within the package. The IC must be soldered down to the backpad and the backpad area should be filled with vias connecting it to the ground plane. 3126f For more information www.linear.com/LTC3126 21 LTC3126 Applications Information 3. There should be an uninterrupted ground plane under the entire converter in order to minimize the crosssectional area of the high frequency current loops. This minimizes EMI and reduces the inductive drops in these loops thereby minimizing SW pin overshoot and ringing. 4. Connections to the PVIN1, PVIN2 and SW pins should be made as wide as possible to reduce the series impedance. This will improve efficiency and reduce the thermal resistance. 5. To prevent large circulating currents in the ground plane from disrupting operation of the part, all small-signal grounds should either return directly to the small-signal ground pin (GND) or via down to the ground plane close to the GND pin and not near the power stage components. This includes the ground connections for the RT resistor, the FB resistor divider and the VSET1 and VSET2 resistor dividers. 6. Keep the routes connecting to the high impedance noise sensitive inputs (FB, RT, VSET1, VSET2) as short as possible to minimize noise pickup. 7. The BST1/BST2 pins transition at the switching frequency to the full input voltage. To minimize radiated noise and coupling, keep the routes connecting to the boost capacitors as short as possible and keep these routes away from all sensitive circuitry and pins (FB, RT, VSET1, VSET2). 8. The connection to the VIN1 pin (Pin 25) should be separate from the connection to the PVIN1 (Pin 24) and should have a separate 0.1F bypass capacitor. This will prevent noise from the PVIN1 trace from being coupled into the sensitive VIN1 pin. VIN1 VIN2 VIN2 28 27 26 25 24 23 VIN1 1 28 2 27 26 1 22 3 2 21 4 25 3 20 5 24 4 19 6 23 5 18 7 22 6 17 8 21 7 16 9 20 8 15 10 19 11 18 12 17 13 16 14 15 9 10 11 12 13 14 CONNECT TO VOUT VOUT CONNECT TO VOUT VIN2 ALL COMPONENTS DISPLAYED ABOVE SHOULD BE PLACED AS CLOSE TO THE IC AS POSSIBLE VIA TO GROUND PLANE 3126 F08 OUTLINE OF UNINTERRUPTED GROUND PLANE Figure 8. Recommended PC Board Layout for QFN Package ALL COMPONENTS DISPLAYED ABOVE SHOULD BE PLACED AS CLOSE TO THE IC AS POSSIBLE VIA TO GROUND PLANE VOUT VIN2 3126 F09 OUTLINE OF UNINTERRUPTED GROUND PLANE Figure 9. Recommended PC Board Layout for TSSOP Package 3126f 22 For more information www.linear.com/LTC3126 LTC3126 Typical Applications 12V, 1MHz Step-Down Converter with Dual Inputs 0.1F 13.1V TO 42V 13.1V TO 42V 4.7F 4.7F 4.7F 12V, 2MHz Step-Down Converter with Dual Inputs 0.1F 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND L1 6.8H 22pF 1M VOUT 12V COUT 2.5A 22F x2 13.1V TO 42V 13.1V TO 42V 4.7F L1: COILCRAFT XAL4030 COUT: TDK C4532X7R1E226M250KC 94% EFFICIENCY, VIN = 24V, 1A LOAD 92% EFFICIENCY, VIN = 36V, 2A LOAD 10A NO LOAD IQ AT VIN = 24V 450mV DROPOUT AT 1A LOAD 1.05V DROPOUT AT 2.5A LOAD 6V TO 42V 4.7F 4.7F 4.7F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND 3126 TA04 5V, 750kHz Step-Down Converter with Dual Inputs 6V TO 42V 4.7F 73.2k 33.2k 3126 TA03 0.1F 4.7F 0.1F 3126 TA05 L1 4.7H 33pF 1M VOUT 5V COUT 2.5A 47F x2 6V TO 42V 6V TO 42V 4.7F 4.7F 196k 44.2k L1 4.7H 12pF 1M VOUT 12V COUT 2.5A 33F 73.2k 16.5k L1: COILCRAFT XAL4030 COUT: CHEMI-CON KTS250B366M55N0B00 92% EFFICIENCY, VIN = 24V, 1.5A LOAD 89% EFFICIENCY, VIN = 36V, 1.5A LOAD 11A NO LOAD IQ AT VIN = 24V 0.6V DROPOUT AT 1A LOAD 1.1V DROPOUT AT 2.5A LOAD 5V, 2MHz Step-Down Converter with Dual Inputs 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND 0.1F 4.7F L1: COILCRAFT XAL4030 COUT: MURATA GRM43ER61A476KE19L 93% EFFICIENCY, VIN = 12V, 1A LOAD 90% EFFICIENCY, VIN = 24V, 1.5A LOAD 3A NO LOAD IQ AT VIN = 24V 330mV DROPOUT AT 1A LOAD 850mV DROPOUT AT 2.5A LOAD 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND 3126 TA06 L1 3.3H 10pF 1M VOUT 5V COUT 2.5A 22F x2 196k 16.5k L1: TOKO FDSD0518 COUT: MURATA GRM43ER71A226KE01L 91% EFFICIENCY, VIN = 12V, 1A LOAD 87% EFFICIENCY, VIN = 24V, 1.5A LOAD 3A NO LOAD IQ AT VIN = 24V 390mV DROPOUT AT 1A LOAD 680mV DROPOUT AT 2A LOAD 3126f For more information www.linear.com/LTC3126 23 LTC3126 Typical Applications 3.3V, 750kHz Step-Down Converter with Dual Inputs 0.1F 4.2V TO 42V 4.2V TO 42V 4.7F 4.7F 4.7F 3.3V, 2MHz Step-Down Converter with Dual Inputs 0.1F 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND L1 4.7H 10pF 909k VOUT 3.3V COUT 2.5A 47F 4.3V TO 25V 42V TRANSIENT* 4.7F 4.3V TO 25V 42V TRANSIENT* 4.7F 301k 44.2k 3126 TA07 4.7F L1: COILCRAFT XAL4030 91% EFFICIENCY, VIN = 12V, 1A LOAD 87% EFFICIENCY, VIN = 24V, 1A LOAD 2A NO LOAD IQ AT VIN = 24V 330mV DROPOUT AT 1A LOAD 660mV DROPOUT AT 2A LOAD 1.8V, 750kHz Step-Down Converter with Dual Inputs 0.1F 2.4V TO 36V 42V TRANSIENT* 4.7F 2.4V TO 36V 42V TRANSIENT* 4.7F 4.7F 3126 TA09 BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND 68pF 280k VOUT 1.8V COUT 2.5A 100F x2 2.4V TO 14V 42V TRANSIENT* 4.7F 2.4V TO 14V 42V TRANSIENT* 4.7F 232k 44.2k 15pF 909k VOUT 3.3V COUT 2.5A 22F x2 301k 16.5k L1: TOKO FDSD0518 COUT: MURATA GRM43ER71A226KE01L 88% EFFICIENCY, VIN = 12V, 1A LOAD 80% EFFICIENCY, VIN = 24V, 1A LOAD 4A NO LOAD IQ AT VIN = 24V 400mV DROPOUT AT 1A LOAD 750mV DROPOUT AT 2A LOAD 1.8V, 2MHz Step-Down Converter with Dual Inputs 0.1F L1 3.3H L1 3.3H 3126 TA08 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND 0.1F 4.7F L1: COILCRAFT XAL4030 COUT: AVX 12106D107KAT2A 86% EFFICIENCY, VIN = 12V, 1A LOAD 79% EFFICIENCY, VIN = 24V, 1.5A LOAD 5A NO LOAD IQ AT VIN = 24V 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC RT ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE GND PGND 3126 TA10 L1 2.2H 82pF 280k VOUT 1.8V COUT 2.5A 100F x2 232k 16.5k L1: TOKO FDSD0518 COUT: AVX 12106D107KAT2A 87% EFFICIENCY, VIN = 5V, 1A LOAD 80% EFFICIENCY, VIN = 12V, 1A LOAD 5A NO LOAD IQ AT VIN = 12V *The step-down converter can operate over the specified input voltage range without any pulse skipping for loads from 250mA to 2.5A. However, in all applications, the converter can operate from an input voltage as high as 42V, but pulse skipping may occur if operated above the specified voltage range. Pulse skipping is not detrimental to the IC, but can result in significant output voltage ripple and is therefore generally avoided while in nominal operating conditions. 3126f 24 For more information www.linear.com/LTC3126 LTC3126 Typical Applications Automotive and Photovoltaic Powered 5V USB Supply 0.1F AUTOMOTIVE 12V NOMINAL 8V TO 40V 18V PHOTOVOLTAIC PANEL 22F + 4.7F 309k + BST2 COM2 BST1 COM1 VIN2 PVIN2 SW EXTVCC VIN1 PVIN1 FB PVCC LTC3126 VCC ENA VREF PRIORITY VSET1 VALID1 VSET2 VALID2 PWM/SYNC PGOOD DIODE RT GND PGND 4.7F + 0.1F 432k 499k L1 4.7H 10pF VOUT 5V COUT 2.5A 47F 976k 191k 33.2k 3126 TA11a fSW = 1MHz VIN1 UVLO THRESHOLD = 15V VIN2 UVLO THRESHOLD = 8V L1: COILCRAFT XAL4030 Efficiency, VIN = 12V 100 Burst Mode OPERATION 90 EFFICIENCY (%) 80 70 60 50 40 PWM Mode 30 20 10 0 0.001 0.01 0.1 LOAD CURRENT (A) 1 4 3126 TA11b Photovoltaic Panel Disconnect (Switch to Automotive Input) Load Step, 250mA to 2.5A VIN1, VIN2 5V/DIV VOUT 200mV/DIV INDUCTOR CURRENT 1A/DIV 50s/DIV VIN = 18V 3126 TA11c VIN2 VIN1 VOUT 200mV/DIV INDUCTOR CURRENT 2A/DIV IIN2 2A/DIV 50s/DIV 3126 TA11d VIN1 = 18V VIN2 = 12.8V 2.5A LOAD 3126f For more information www.linear.com/LTC3126 25 LTC3126 Typical Applications 5V, 2A Supply from Wall Adapter and Lead-Acid Backup Battery 0.1F 12V WALL ADAPTER INPUT + 12V SEALED LEAD-ACID BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC ENA VREF 4.7F 47F ELECT + 0.1F 4.7F 4.7F 499k VSET1 VSET2 499k PWM/SYNC DIODE GND PRIORITY VALID1 VALID2 PGOOD RT PGND L1 4.7H 47F 10pF VOUT 5V 2A 976k 191k 33.2k 3126 TA12a fSW = 1MHz L1: COILCRAFT XAL5030 Efficiency, VIN = 12V 100 Load Step, 200mA to 2A Burst Mode OPERATION 90 VOUT 200mV/DIV EFFICIENCY (%) 80 70 60 INDUCTOR CURRENT 1A/DIV 50 40 PWM Mode 30 50s/DIV 3126 TA12c VIN1 = 12V 20 10 0 0.0001 0.001 0.01 0.1 LOAD CURRENT (A) 1 4 3126 TA12b Wall Adapter Plug-In Transient VIN1, VIN2 5V/DIV VIN2 VIN1, VIN2 5V/DIV VIN1 VOUT 200mV/DIV IIN1 1A/DIV INDUCTOR CURRENT 2A/DIV VIN2 VOUT 200mV/DIV IIN1 1A/DIV INDUCTOR CURRENT 2A/DIV 20s/DIV 2A LOAD Wall Adapter Disconnect Transient 3126 TA12d VIN1 50s/DIV 3126 TA12e 2A LOAD 3126f 26 For more information www.linear.com/LTC3126 LTC3126 Typical Applications 3.3V/2.5A Supply from 24V Wall Adapter and Lead-Acid Battery 0.1F 24V WALL ADAPTER 12V LEAD-ACID + 4.7F 4.7F 4.7F 499k 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC ENA PWM/SYNC PRIORITY VREF VALID1 VSET1 VALID2 VSET2 PGOOD RT DIODE GND PGND 499k L1 4.7H 12pF 1.13M VOUT 3.3V COUT 2.5A 47F x2 374k 33.2k 3126 TA13a fSW = 1MHz VIN1 UVLO THRESHOLD = 20V VIN2 UVLO THRESHOLD = 10V L1: WURTH 744 778 9004 Load Step, 250mA to 2.5A Soft-Start ENA 2V/DIV VOUT 200mV/DIV VOUT 2V/DIV PGOOD 5V/DIV INDUCTOR CURRENT 1A/DIV INDUCTOR CURRENT 1A/DIV 100s/DIV 3126 TA13b 2ms/DIV 3126 TA13c VIN = 24V Wall Adapter Plug-In Transient VIN1, VIN2 10V/DIV VIN1 Wall Adapter Disconnect Transient VIN1, VIN2 10V/DIV VIN2 VIN1 VIN2 VOUT 200mV/DIV IIN1 1A/DIV INDUCTOR CURRENT 2A/DIV VOUT 200mV/DIV IIN1 1A/DIV INDUCTOR CURRENT 2A/DIV 50s/DIV 3126 TA13d 50s/DIV 3126 TA13e 3126f For more information www.linear.com/LTC3126 27 LTC3126 Package Description Please refer to http://www.linear.com/product/LTC3126#packaging for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1712 Rev C) 0.70 0.05 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 3.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) 0.75 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 0.10 (2 SIDES) 3.50 REF 3.65 0.10 2.65 0.10 (UFD28) QFN 0816 REV C 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3126f 28 For more information www.linear.com/LTC3126 LTC3126 Package Description Please refer to http://www.linear.com/product/LTC3126#packaging for the most recent package drawings. FE Package 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation EB 9.60 - 9.80* (.378 - .386) 4.75 (.187) 4.75 (.187) 28 27 26 2524 23 22 21 20 1918 17 16 15 6.60 0.10 4.50 0.10 2.74 (.108) SEE NOTE 4 0.45 0.05 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 6.40 2.74 (.252) (.108) BSC 1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.25 REF 1.20 (.047) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE28 (EB) TSSOP REV K 0913 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3126f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC3126 29 LTC3126 Typical Application 3.3V Supply with 200ms Transient Ride-Through Capability 0.1F 12V INPUT RAIL L1 10H 0.1 4.7F D1 35V 4.7F ISN ISP SW LT1618 + 887k FB SHDN 33.2k 1000F 50V ELECT x3 VCC 4.7F 4.7F VIN 4.7F 0.1F BST2 COM2 BST1 COM1 VIN1 PVIN1 SW EXTVCC VIN2 PVIN2 FB PVCC LTC3126 VCC ENA 249k 2k D1: MBR0530 L1: SUMIDA CR43-100 L2: BOURNS SRN5020-4R7M 249k VSET1 VSET2 PWM/SYNC DIODE GND PRIORITY VALID1 VALID2 PGOOD RT VIN1 10V/DIV 100k 100k 33.2k 3126 TA02a Power-Up Waveforms VIN1 10V/DIV VIN2 10V/DIV VIN1 10V/DIV VIN2 20V/DIV VOUT 2V/DIV IIN1 500mA/DIV VOUT 2V/DIV IIN2 2A/DIV VOUT 2V/DIV 3126 TA02b 374k fSW = 1MHz VIN2 10V/DIV 100ms/DIV 1.13M PGND VOUT Hold-Up with Loss of Input Supply Transient Ride-Through VOUT 3.3V 47F 2A VCC VREF 10nF 10pF 100k 499k IADJ GND VC L2 4.7H 50ms/DIV 3126 TA02c 100ms/DIV 3126 TA02d Related Parts PART NUMBER DESCRIPTION COMMENTS LT(R)8609 42V, 2A (3A Peak) 2MHz Synchronous Step-Down Regulator with IQ = 2.5A VIN: 3V to 42V, IQ = 2.5A, ISD = 1A, MSOP-10E Package LTC3118 18V, 2A Buck-Boost DC/DC Converter with Low Loss Dual Input PowerPath VIN: 2.2V to 18V, IQ = 50A, ISD = 2A, TSSOP-28, QFN-24 Packages LT8610 42V, 2.5A Synchronous Step-Down Regulator VIN: 3.4V to 42V, IQ = 2.5A, ISD = 1A, MSOP-16 Package LTC4417 Prioritized PowerPath Controller Controller for External P-Channel MOSFETs, Three Channels, VIN: 2.5V to 36V, IQ = 28A, SSOP-24, QFN-24 Packages LTC3114-1 40V, 1A Synchronous 4-Switch Monolithic Buck-Boost DC/DC Converter VIN: 2.2V to 40V, VOUT: 2.7V to 40V, IQ = 30A, ISD = 3A, TSSOP-16, DFN-16 Packages LTC3115-1 40V, 2A Synchronous 4-Switch Monolithic Buck-Boost DC/DC Converter VIN: 2.7V to 40V, VOUT: 2.7V to 40V, IQ = 30A, ISD = 3A, TSSOP-20, DFN-16 Packages 3126f 30 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3126 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC3126 LT 0916 * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 2016