SC1405DISTRT - Semtech Corp.

POWER MANAGEMENT

1www.semtech.com

SC1405D

High Speed Synchronous Power

MOSFET Smart Driver

PRELIMINARY

Features

Applications

Revision: December 19, 2003

Typical Application Circuit

Description

The SC1405D is a Dual-MOSFET Driver with an internal

Overlap Protection Circuit to prevent shoot-through. Each

driver is capable of driving a 3000pF load in 15ns rise/

fall time and has ULTRA-LOW propagation delay from in-

put transition to the gate of the power FET’s. Adaptive

Overlap Protection circuit ensures that the synchronous

FET does not turn on until the top FET source has reached

a voltage low enough to prevent shoot-through. The de-

lay between the bottom gate going low to the top gate

transitioning high is externally programmable via a ca-

pacitor to minimize dead time. The bottom FET may be

disabled at light loads by keeping S_MOD low to trigger

asynchronous operation, thus saving the bottom FET’s

gate drive current and inductor ripple current.

An internal voltage reference allows threshold adjustment

for an Output Over-Voltage protection circuitry, indepen-

dent of the PWM controller. The device provides over-

voltage protection independant of the PWM feedback

loop with a unique “adaptive OVP” comparator which re-

jects noise but responds quickly to a true OVP situation.

Under-Voltage-Lock-Out circuit is included to guarantee

that both driver outputs are off when Vcc is less than or

equal to 4.5V (typ) at supply ramp up (4.35V at supply

ramp down). A CMOS output provides status indication

of the 5V supply. A low enable input places the IC in stand-

by mode, reducing supply current to less than 10µA.

Fast rise and fall times (15ns with 3000pf load)

14ns max. Propagation delay (BG going with low)

Adaptive and programmable shoot-through

protection

Adaptive overvoltage protection

Wide input voltage range (4.5-25V)

Programmable delay between MOSFET’s

Power saving asynchronous mode control

Output overvoltage protection/overtemp shutdown

Under-Voltage lock-out and power ready signal

Less than 10µA stand-by current (EN=low)

Power ready output signal

High frequency (to 1.2MHz) operation allows use of

small inductors and low cost caps in place of

electrolytics

TSSOP-14 and SOIC-8 EDP package

High Density/Fast transient microprocessor power

supplies

Motor Drives/Class-D amps

High efficiency portable computers

2 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Absolute Maximum Ratings

retemaraPlobmySsnoitidnoCmuminiMmumixaMstinU

egatloVylppuSV

XAMCC

3.0-7V

DNGPotTSBXAMV

DNGP-TSB

3.0-03V

NRDotTSBXAMV

NRD-TSB

3.0-7V

DNGPotNRDXAMV

NGP-NRD

CD2-52V

DNGPotNRDXAMV

NGP-NRD

Sn001,tneisnarT4-52V

DNGPotS_PVOXAMV

DNGP-SPVO

3.0-01V

,YDRP,EDOM,SPSD,OC,NE

DNGAotYALED

3.0-V

3.0+V

DNGPotDNGA 1-1+V

noitapissiDrewoPsuounitnoCdPT,C°52=bmaT

C°521=

T,C°52=esacT

C°521=

66.0

65.2 Ω

esaCotnoitcnuJecnadepmIlamrehT θ

04W/C°

otnoitcnuJecnadepmIlamrehT

tneibmA θ

051W/C°

egnaRerutarepmeTnoitcnuJT

04-521+C°

egnaRerutarepmeTegarotST

GTS

56-051+C°

.ceS01)gniredloS(erutarepmeTdaeLT

DAEL

003C°

NOTE:

(1) Specification refers to application circuit.

Unless specified: -40 < θJ < 125°C; VCC = 5V; 4V < VBST < 26V

Electrical Characteristics - DC Operating Specifications

retemaraPlobmySsnoitidnoCniMpyTxaMstinU

ylppuSrewoP

egatloVylppuSV

5.45 0.6V

tnerruCtnecseiuQybts_qIV0=NE01Aµ

gnitarepo,tnerruCtnecseiuQpo_qIV

V0=OC,V5=1Am

YDRP

egatloVtuptuOleveLhgiHV

Am01=daoll,V7.4=5.455.4V

egatloVtuptuOleveLwoLV

,dlohserhtOLVU<

Aµ01=daoll 1.02.0V

tnerruCkniSI

KNIS_O

V4.0=YDRPV501Am

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified

in the Electrical Characteristics section is not implied.

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

retemaraPlobmySsnoitidnoCniMpyTxaMstinU

RD_SPSD

egatloVtuptuOleveLhgiHV

Fp001=daolC,V6.4=51.4V

egatloVtuptuOleveLwoLV

Fp001=daolC,V6.4=50.0V

tuokcoLegatloVrednU

dlohserhTtratS 3.45.47.4V

siseretsyHsyhV50.0V

dlohserhTevitcAcigoLwolsiNE5.1V

noitcetorPegatlovrevO

dlohserhTpirTV

PIRT

71.1522.182.1V

siseretsyHsyhV

PVO

8.0V

evirdrevOVm05,yaleDpirT521ot0=t

C003074008sn

evirdrevOVm001,yaleDpirT521ot0=t

C521522004sn

DOM_S

egatloVtupnIleveLhgiHV

0.2V

egatloVtupnIleveLwoLV

8.0V

elbanE

egatloVtupnIleveLhgiHV

0.2V

egatloVtupnIleveLwoLV

8.0V

egatloVtupnIleveLhgiHV

0.2V

egatloVtupnIleveLwoLV

8.0V

nwodtuhSlamrehT

tnioPpirTerutarepmeTrevOT

PTO

561

siseretsyHT

TSYH

revirDediS-hgiH

tnerruCtuptuOkaePI

HKP

ecnatsiseRtuptuOcrsR

knisR

,sµ001<wpt,%2<elcycytud

V,C°521=JT

TSB

V-

NRD

,V5.4=

V+)crs(V0.4=

NRD

NRDV+)knis(V5.0=GTVro

Ω

evirDediS-woL

tnerruCtuptuOkaePI

LKP

ecnatsiseRtuptuOcrsR

knisR

,sµ001<wpt,%2<elcycytud

,C°521=JT

,V6.4=

)crs(V4=

Vro

RDWOL

)knis(V5.0=

2.1

0.1

Ω

Electrical Characteristics - DC Operating Specifications

4 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Electrical Characteristics - AC Operating Specifications

retemaraPlobmySsnoitidnoCniMpyTxaMstinU

revirDediShgiH

emitesirrt

1GT

V,Fn3=IC

TSB

V-

NRD

,V6.4=4132 sn

emitllafft

V,Fn3=IC

TSB

V-

NRD

,V6.4=2191 sn

,emityalednoitagaporp

hgihgniogGT hdpt

V,Fn3=IC

TSB

V-

NRD

,V6.4=

0=yaled-C 02 23 sn

,emityalednoitagaporp

wolgniogGT ldpt

V,Fn3=IC

TSB

V-

NRD

,V6.4=5142 sn

revirDediS-woL

emitesirrt

V,Fn3=IC

,V6.4=5142 sn

emitllafrt

V,Fn3=IC

,V6.4=3112 sn

,emityalednoitagaporp

hgihgniogGB hdpt

IHGB

V,Fn3=IC

TSB

V-

NRD

,V6.4=

0=yaled-C 21 91 sn

,emityalednoitagaporp

wolgniogGT ldpt

V,Fn3=IC

,V6.4=

NRD<V1721 sn

tuokcoLegatloV-rednU

pugnipmar5_Vhdpt

OLVU

hgiHsiNE 01 su

nwodgnipmar5_Vhdpt

OLVU

hgiHsiNE 01 su

YDRP

otwolmorfgninoitisnartsiNE

hgih YDRPhdpt

5_V> yaleD,dlohserhtOLVU

NEmorfderusaem>otV0.2

YDRP>V5.3

01 sµ

wolothgihorfgninoitisnartsiNEOLVUhdpt

5_V> yaleD,dlohserhtOLVU

NEmorfderusaem<otV8.0

YDRP< V5_Vfo%01

005 sµ

RD_SPSD

emitllaf/esirrt

.RDSPSD

V6.4=5_V,fp001=IC 02 sn

RD_SPSD,yalednoitagaporp

hgihgniog hdpt

RDSPSD

GBdnahgihseogDOM_S

wolseogDOM_Srohgihseog 01 sn

RD_SPSD,yalednoitagaporp

wolseog ldpt

RDSPSD

GBdnahgihseogDOM_S

wolseog 01 sn

NOTE:

(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Application Circuit - TSSOP-14

Timing Diagram

DSPS_DR

P_READY

PWM IN

+5V

I NPUT POWER

10uF, 6. 3V

++ +

+ ++

2. 2

.22uF

47pF

.1uF

MTB75N03

1N5819

SC1405

510

GND

OVP_S

BST

DELAY_C

S_MOD PGND

PRDY

DSPS_DR

DRN

Vcc

(20KHz-1MHz)

75A, 30V

<<< Output Feedback to PWM

Controller

Over-Voltage Sense

Application Circuit - SOIC-8 EDP

6 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Pin Configuration

Pin Descriptions

Top View

(14-Pin TSSOP)

#niPemaNniPnoitcnuFniP

1S_PVO noitcetorptesotderiuqersrotsisergnilacslanretxE.esnesnoitcetorpegatlovrevO

.dlohserht

2NE dna,GB,GT,wolnehW.ecivedehtfoyrtiucriclanretniehtselbanenipsiht,hgihnehW

.Aµ01nahtsselsi)V5(tnerrucylppusehtdnawoldecroferaYDRP

3DNG.DNGcigoL

4OC.srevirdTEFSOMehtotlangistupnilevel-LTT

5DOM_S nehW.noitareposuonorhcnysagnireggirt,wolebotGBsecroflangissiht,wolnehW

.langissihtfonoitcnufatonsiGB,hgih

6C_YALED noitagaporplanoitiddaehtstesDNGdnanipsihtneewtebdetcennocecnaticapacehT

onfI.Fp/sn1+sn02=yalednoitagaporplatoT.hgihgniogGTotwolgniogGBrofyaled

.sn02=yalednoitagarporpeht,detcennocsiroticapac

7YDRP siht,dlohserhtOLVUehtnahtsselsiCCVnehW.CCVfosutatsehtsetacidninipsihT

sihtdlohserhtOLVUehtotslauqeronahtretaergsiCCVnehW.wolnevirdsituptuo

.ytilibapacknisAµ01dnaevirdecruosAm01asahtuptuosihT.hgihseogtuptuo

8CCV otCCVmorfdetcennocebdluohsroticapaccimarecFµ1-22.A.V8-5foylppustupnI

.pihcehtotesolcyrevDNGP

9GB.TEFSOM)mottob(suonuorhcnysehtrofevirdtuptuO

01DNGP .)dnuorgrewop(nipecruosTEFsuonorhcnysehtottcennoC.dnuorgrewoP

11RD_SPSD nipsiht,hgihsiDOM-SnehW.langistuptuolevelLTT.evirDhctiwStnioPteScimanyD

.egatlovniprevirdGBehtswollof

21NRD nipsihT.s'TEFSOMsuonorhcnysdnagnihctiwsehtfonoitcnujehtotstcennocnipsihT

.noitarepognitceffatuohtiwDNGPotevitalermuminimV2-aotdetcejbusebnac

31GT.TEFSOM)edis-hgih(gnihctiwsehtrofevirdetagtuptuO

41TSB ehtpolevedotsnipNRDdnaTSBneewtebdetcennocsiroticapacA.nippartstooB

yllacipytsieulavroticapacehT.TEFSOMedis-hgihehtrofegatlovpartstoobgnitaolf

.)cimarec(Fµ1dnaFµ1.0neewteb

NOTE:NOTE:

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

Ordering Information

eciveD

)1(

egakcaPT(egnaRpmeT

)

RTSTID5041CS41-POSSTC°521ot°04-

Note:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Pin Configuration Ordering Information

Pin Descriptions

Note:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

eciveD

)1(

egakcaPT(egnaRpmeT

)

RTSID5041CSPDE8-CIOSC°521ot°04-

#niPemaNniPnoitcnuFniP

1NRD nipsihT.s'TEFSOMsuonorhcnysdnagnihctiwsehtfonoitcnujehtotstcennocnipsihT

.noitarepognitceffatuohtiwDNGPotevitalermuminimV2-aotdetcejbusebnac

2GT.TEFSOM)edis-hgih(gnihctiwsehtrofevirdetagtuptuO

3TSB

ehtpolevedotsnipNRDdnaTSBneewtebdetcennocsiroticapacA.nippartstooB

yllacipytsieulavroticapacehT.TEFSOMedis-hgihehtrofegatlovpartstoobgnitaolf

.)cimarec(Fµ1dnaFµ1.0neewteb

4NEGBdnaGT,wolnehW.ecivedehtfoyrtiucriclanretniehtselbanenipsiht,hgihnehW

.Aµ01nahtsselsi)V5(tnerrucylppusehtdnawoldecrofera

5OC.srevirdTEFSOMehtotlangistupnilevel-LTT

6CCV yrevDNGotV5morfdetcennocebdluohsroticapaccimarecFµ1-22.A.ylppusV5+

.nipsihtotesolc

7GB.TEFSOM)mottob(suonorhcnysehtrofevirdtuptuO

8DNG.dnuorG

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

GNDDRN

TOP VIEW

(POWER SO-8)

BGTG

VCCBST

COEN

9 NAMEBOTTOM

8 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Block Diagram

Applications Information

SC1405D

is designed to drive Low Rds_On power

MOSFET’s with ultra-low rise/fall times and propagation

delays. As the switching frequency of PWM controllers is

increased to reduce power supply volume and cost, fast

rise and fall times are necessary to minimize switching

losses (TOP MOSFET) and reduce Dead-time (BOTTOM

MOSFET) losses. While Low Rds_On MOSFET’s present

a power saving in I2R losses, the MOSFET’s die area is

larger and thus the effective input capacitance of the

MOSFET is increased. Often a 50% decrease in Rds_On

more than doubles the effective input gate charge, which

must be supplied by the driver. The Rds_On power sav-

ings can be offset by the switching and dead-time losses

with a suboptimum driver. While discrete solution can

achieve reasonable drive capability, implementing shoot-

through, programmable delay and other housekeeping

functions necessary for safe operation can become cum-

bersome and costly. The SC1405 family of parts pre-

sents a total solution for the high-speed, high power den-

sity applications. Wide input supply range of 4.5V-25V

allows use in battery powered applications, new high volt-

age, distributed power servers as well as Class-D ampli-

fiers.

Theory of Operation

The control input (CO) to the SC1405D is typically sup-

plied by a PWM controller that regulates the power sup-

ply output. (See Application Evaluation Schematic, Fig-

ure 3). The timing diagram demonstrates the sequence

of events by which the top and bottom drive signals are

applied. The shoot-through protection is implemented

by holding the bottom FET off until the voltage at the

phase node (intersection of top FET source, the output

inductor and the bottom FET drain) has dropped below

1V. This assures that the top FET has turned off and

that a direct current path does not exist between the

input supply and ground, a condition which both the top

and bottom FET’s are on momentarily. The top FET is

also prevented from turning on until the bottom FET is

off. This time is internally set to 20ns (typical) and may

be increased by adding a capacitor from the C-Delay pin

to GND. The delay is approximately 1ns/pf in addition to

the internal 20ns delay. The external capacitor may be

needed if multiple High input capacitance MOSFET’s are

used in parallel and the fall time is substantially greater

than 20ns.

It must be noted that increasing the dead-time by high

values of C-Delay capacitor will reduce efficiency since

the parallel Schottky or the bottom FET body diode will

have to conduct during dead-time.

Layout Guidelines

As with any high speed , high current circuit, proper lay-

out is critical in achieving optimum performance of the

SC1405D. The Evaluation board schematic (Refer to

figure 3) shows a dual phase synchronous design with all

surface mountable components.

While components connecting to C-Delay, OVP_S, EN,S-

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

MOD, DSPS_DR and PRDY are relatively noncritical, tight

placement and short, wide traces must be used in layout

of The Drives, DRN, and especially PGND pin. The top

gate driver supply voltage is provided by bootstrapping

the +5V supply and adding it the phase node voltage

(DRN). Since the bootstrap capacitor supplies the charge

to the TOP gate, it must be less than .5” away from the

SC1405. Ceramic X7R capacitors are a good choice for

supply bypassing near the chip. The Vcc pin capacitor

must also be less than .5” away from the SC1405. The

ground node of this capacitor, the SC1405 PGND pin

and the Source of the bottom FET must be very close to

each other, preferably with common PCB copper land

and multiple vias to the ground plane (if used). The par-

allel Schottky (if used) must be physically next to the

Bottom FETS Drain and source. Any trace or lead induc-

tance in these connections will drive current way from

the Schottky and allow it to flow through the FET’s Body

diode, thus reducing efficiency.

Preventing Inadvertent Bottom FET Turn-on

At high input voltages, (12V and greater) a fast turn-on

of the top FET creates a positive going spike on the Bot-

tom FET’s gate through the Miller capacitance, Crss of

the bottom FET. The voltage appearing on the gate due

to this spike is:

Vspike= Vin*crss

(Crass+ciss)

Where Ciss is the input gate capacitance of the bottom

FET. This is assuming that the impedance of the drive

path is too high compared to the instantaneous imped-

ance of the capacitors. (since dV/dT and thus the effec-

tive frequency is very high). If the BG pin of the SC1405D

is very close to the bottom FET, Vspike will be reduced

depending on trace inductance, rate if rise of current,

etc.

While not shown in Figure 3, a capacitor may be added

from the gate of the Bottom FET to its source, preferably

less than .5” away. This capacitor will be added to Ciss

in the above equation to reduce the effective spike volt-

age, Vspike.

The selection of the bottom MOSFET must be done with

attention paid to the Crss/Ciss ratio. A low ratio reduces

Applications Information

the Miller feedback and thus reduces Vspike. Also

MOSFETs with higher Turn-on threshold voltages will con-

duct at a higher voltage and will not turn on during the

spike. The MOSFET shown in the schematic has a 2 volt

threshold and will require approximately 5 volts Vgs to be

conducting, thus reducing the possibility of shoot-through.

A zero ohm bottom FET gate resistor will obviously help

keeping the gate voltage low.

Ultimately, slowing down the top FET by adding gate re-

sistance will reduce di/dt which will in turn make the ef-

fective impedance of the capacitors higher, thus allow-

ing the BG driver to hold the bottom gate voltage low.

Ringing on the Phase Node

The top MOSFET source must be close to the bottom

MOSFET drain to prevent ringing and the possibility of

the phase node going negative. This frequency is deter-

mined by:

Fring = (2 ∏* Sqrt(Lst*Coss))

Where:

Lst = The effective stray inductance of the top FET added

to trace inductance of the connection between top FET’s

source and the bottom FET’s drain added to the trace

resistance of the bottom FET’s ground connection.

Coss=Drain to source capacitance of bottom FET. If there

is a Schottky used, the capacitance of the Schottky is

added to the value.

Although this ringing does not pose any power losses

due to a fairly high Q, it could cause the phase node to

go too far negative, thus causing improper operation,

double pulsing or at worst driver damage. This ringing is

also an EMI nuisance due to its high resonant frequency.

Adding a capacitor, typically 1000-2000pf, in parallel with

Coss can often eliminate the EMI issue. If double puls-

ing is caused due to excessive ringing, placing 4.7-10

ohm resistor between the phase node and the DRN pin

of the SC1405 should eliminate the double pulsing.

The negative voltage spikes on the phase node adds to

the bootstrap capacitor voltage, thus increasing the volt-

age between VBST - VDRN. If the phase node negative

10 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

spikes are too large, the voltage on the boost capacitor

could exceed device’s absolute maximum rating of 8V.

To eliminate the effect of the ringing on the boost ca-

pacitor voltage, place a 4.7 - 10 Ohm resistor between

boost Schottky diode and Vcc to filter the negative spikes

on DRN Pin. Alternately, a Silicon diode, such as the

commonly available 1N4148 can substitute for the

Schottky diode and eliminate the need for the series re-

sistor.

Proper layout will guarantee minimum ringing and elimi-

nate the need for external components. Use of SO-8 or

other surface mount MOSFETs will reduce lead induc-

tance and their parasitic effects.

ASYNCHRONOUS OPERATION

The SC1405D can be configured to operate in Asynchro-

nous mode by pulling S-MOD to logic LOW, thus disabling

the bottom FET drive. This has the effect of saving power

at light loads since the bottom FET’s gate capacitance

does not have to charged at the switching frequency.

There can be a significant savings since the bottom driver

can supply up to 2A pulses to the FET at the switching

frequency. There is an additional efficiency benefit to

operating in asynchronous mode. When operating in syn-

chronous mode, the inductor current can go negative

Applications Information (Cont.)

and flow in reverse direction when the bottom FET is on

and the DC load is less than 1/2 inductor ripple current.

At that point, the inductor core and wire losses, depend-

ing on the magnitude of the ripple current, can be quite

significant. Operating in asynchronous mode at light loads

effectively only charges the inductor by as much as

needed to supply the load current, since the inductor

never completely discharges at light loads. DC regula-

tion can be an issue when operating in asynchronous

mode, depending on the type of controller used and mini-

mum load required to maintain regulation. If there are

no Shottkey diodes used in parallel with bottom FET, the

FET’s body diode will need to conduct in asynchronous

mode. The high voltage drop of this diode must be con-

sidered when determining the criteria for this mode of

operation.

DSPS DR

This pin produces an output which is a logical duplicate

of the bottom FET’s gate drive, if S-MOD is held LOW.

OVP_S/OVER TEMP SHUTDOWN

Output over-voltage protection (OVP) may be implemented

on the SC1405D independent of the PWM controller . A

voltage divider from the output is compared with the in-

ternal bandgap voltage of 1.2V (typical). Upon exceeding

this voltage, the overvoltage comparator disables the top

FET, while turning on the bottom FET to allow discharge

of the output capacitors excessive voltage through the

output inductor.

The SC1405D has a unique adaptive OVP circuit. Short

noise pulses, less than ~100ns are rejected completely;

longer pulses will trigger OVP if only of sufficient magni-

tude. A long term transient will trigger OVP with a smaller

magnitude. To assure proper tripping, bypass the resis-

tor from OVP_S pin to GND with a capacitor. The value of

this capacitor must be selected to achieve a time con-

stant equal to one switching period. Leave at least 250mV

headroom on the OVP pin to prevent false OVP events.

The SC1405D will shutdown if its TJ exceeds 165°C.

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

PIN Descriptions

Typical Characteristics

Performance diagrams, Application Evaluation Board.

PIN Descriptions Timing diagram:

Ch1: CO input

Ch2: TG drive

Ch3: BG non-overlap drive

Ch4: phase node

Iout = 20A (10A/phase)

Refer to Eval. Schematic

(fig.3)

Timing diagram:

Rise/Fall times

Ch1: TG drive

Ch2: BG drive

Cursor: TpdhTG

Iout = 20A (10A/phase)

Refer to Eval. Schematic

(fig.3)

VIN = 12V, VOUT = 1.6V. Top FET = IR7811 FDB7030(BL) Qgd = 23nc

12 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Typical Characteristics (Cont.)

Typical Delay vs. Overdrive (T=25C)

100

1000

10000

10 1000

Overdrive (mV)

Delay (nS)

Delay vs. Temp.

Delay vs. Overdrive

SC1405D OVP Delay vs. Temperature

0.00

100.00

200.00

300.00

400.00

500.00

600.00

-25 -5 15 35 55 75 95 115 135

Temperature (C)

Delay (nS)

50mV Overdrive 100mV Overdrive

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Outline Drawing -TSSOP-14

Land Pattern - TSSOP-14

14 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Outline Drawing - Power SOIC-8L

 2003 Semtech Corp. www.semtech.com

SC1405D

POWER MANAGEMENT

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805)498-2111 FAX (805)498-3804

Contact Information

Land Pattern - Power SOIC-8L