LTC3828EUH - ANALOG DEVICES

LTC3828

3828fc

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual, 2-Phase Step-Down

Controller with Tracking

The LTC

3828 is a dual high performance step-down

switching regulator controller that drives all N-channel

synchronous power MOSFET stages. A constant frequency

current mode architecture allows for a phase-lockable

frequency of up to 550kHz. The TRCKSS pin provides both

soft-start and tracking functions. Multiple LTC3828s can

be daisy-chained in applications requiring more than two

voltages to be tracked.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The precision 0.8V reference and power

good output indicator are compatible with a wide 4.5V to

28V (30V maximum) input supply range, encompassing

all battery chemistries.

The RUN pins control their respective channels indepen-

dently. The FCB/PLLIN pin selects among Burst Mode

operation, skip-cycle mode and continuous current mode.

Current foldback limits MOSFET dissipation during short-

circuit conditions. Reverse current and current foldback

functions are disabled during soft-start.

High Efﬁ ciency Dual 2.5V/3.3V Step-Down Converter with Tracking

n Telecom Infrastructure

n ASIC Power Supply

n Industry Equipment

L, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787,

6304066, 6580258

n Dual, 180° Phased Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

n Tracking for Both Outputs

n Constant Frequency Current Mode Control

n Wide VIN Range: 4.5V to 28V Operation

n Power Good Output Voltage Indicator

n Adjustable Soft-Start Current Ramping

n Foldback Output Current Limiting–

Disabled at Start-Up

n No Reverse Current During Soft-Start Interval

n Clock Output for 3-, 4-, 6-Phase Operation

n Dual N-Channel MOSFET Synchronous Drive

n ±1% Output Voltage Accuracy

n Phase-Lockable Fixed Frequency 260kHz to 550kHz

n OPTI-LOOP

Compensation Minimizes COUT

n Very Low Dropout Operation: 99% Duty Cycle

n Output Overvoltage Protection

n Small 28-Lead SSOP and 5mm × 5mm QFN

Packages

4.7µF

0.1µF

63.4k 1%

1000pF

3.2µH

220pF

1µF

CERAMIC

22µF

50V

CERAMIC

+47µF

0.01

20k

1% 20k

1% 15k

3.3V

0.1µF

42.5k

3.2µH

220pF

1000pF

+56µF

0.01

20k

15k

2.5V

TG1 TG2

BOOST1 BOOST2

SW1 SW2

BG1 BG2

SGND

PGND

SENSE1+SENSE2+

SENSE1–SENSE2–

VOSENSE1 VOSENSE2

ITH1 ITH2

VIN PGOOD INTVCC

RUN1 RUN2

4.5V TO 28V

3828 TA01

LTC3828

FCB/PLLIN

500kHz

TRCKSS1TRCKSS1TRCKSS2

63.4k 1%

LTC3828

3828fc

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (VIN) ........................ 30V to –0.3V

Top Side Driver Voltages

BOOST1, BOOST2 ................................. 36V to –0.3V

Switch Voltage (SW1, SW2) ........................ 30V to –5V

INTVCC, DRVCC, RUN1, RUN2, (BOOST1-SW1),

(BOOST2-SW2) ........................................... 7V to –0.3V

SENSE1+, SENSE2+, SENSE1–,

SENSE2– Voltages ........................ (1.1)INTVCC to –0.3V

FCB/PLLIN, PLLFLTR, CLKOUT,

PHSMD Voltage .................................. INTVCC to –0.3V

TRCKSS1, TRCKSS2 ............................. INTVCC to –0.3V

(Note 1)

PGOOD ...................................................... 5.5V to –0.3V

ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ... 2.7V to –0.3V

Peak Output Current <10µs (TG1, TG2, BG1, BG2) .... 3A

INTVCC Peak Output Current (Note 8) ................... 50mA

Operating Temperature Range (Note 7)

LTC3828E ............................................ –40°C to 85°C

Junction Temperature (Note 2) ............................ 125°C

Storage Temperature Range .................. –65°C to 125°C

Reﬂ ow Peak Body Temperature (UH Package) ..... 260°C

Lead Temperature (Soldering, 10 sec)

G Package ......................................................... 300°C

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

CLKOUT

PGOOD

BOOST1

TG1

SW1

VIN

INTVCC

PGND

BG1

BG2

SW2

TG2

BOOST2

RUN2

TRCKSS1

ITH1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

RUN1

FCB/PLLIN

SGND

TRCKSS2

SENSE2–

SENSE2+

ITH2

VOSENSE2

TJMAX = 125°C, θJA = 95°C/W

32 31 30 29 28 27 26 25

9 10 11 12 13

TOP VIEW

14 15 16

1VOSENSE1

PLLFLTR

RUN1

PHSMD

FCB/PLLIN

SGND

TRCKSS2

SW1

VIN

INTVCC

DRVCC

PGND

BG1

BG2

SW2

SENSE1–

SENSE1+

ITH1

TRCKSS1

CLKOUT

PGOOD

BOOST1

TG1

SENSE2–

SENSE2+

ITH2

VOSENSE2

RUN2

BOOST2

TG2

UH PACKAGE

32-LEAD (5mm s 5mm) PLASTIC QFN

TJMAX = 125°C, θJA = 34°C/W

EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3828EG#PBF LTC3828EG#TRPBF LTC3828EG 28-Lead Plastic SSOP –40°C to 85°C

LTC3828EUH#PBF LTC3828EUH#TRPBF 3828 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC3828

3828fc

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 15V, VRUN1, 2 = 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loops

VOSENSE1, 2 Regulated Feedback Voltage (Note 3); ITH1, 2 Voltage = 1.2V l0.792 0.800 0.808 V

IVOSENSE1, 2 Feedback Current (Note 3) ±5 ±50 nA

VREFLNREG Reference Voltage Line Regulation VIN = 4.6V to 28V (Note 3) 0.002 0.02 %/V

VLOADREG Output Voltage Load Regulation (Note 3)

Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V

Measured in Servo Loop; ΔITH Voltage = 1.2V to 2.0V

0.1

–0.1

0.5

–0.5

gm1, 2 Transconductance Ampliﬁ er gmITH1, 2 = 1.2V; Sink/Source 5µA; (Note 3) 1.3 mmho

gmGBW1, 2 Transconductance Ampliﬁ er GBW ITH1, 2 = 1.2V; (Note 3) 3 MHz

IQInput DC Supply Current

Normal Mode

Shutdown

(Note 4)

VOUT1 = 5V

VRUN/SS1, 2 = 0V

100

µA

VFCB Forced Continuous Threshold l0.76 0.800 0.84 V

IFCB Forced Continuous Pin Current VFCB = 0.85V –0.50 –0.18 –0.1 µA

VBINHIBIT Burst Inhibit (Constant Frequency)

Threshold

Measured at FCB pin 4.3 4.8 V

UVLO Undervoltage Lockout VIN Ramping Down l3.5 4 V

VOVL Feedback Overvoltage Lockout Measured at VOSENSE1, 2 l0.84 0.86 0.88 V

ISENSE Sense Pins Total Source Current (Each Channel); VSENSE1–, 2– = VSENSE1+, 2+ = 0V –90 –65 µA

DFMAX Maximum Duty Factor In Dropout 98 99.4 %

ITRCKSS1,2 Soft-Start Charge Current VTRCKSS1, 2 = 0.2V 0.5 1.2 µA

VRUN1, 2 ON RUN Pin ON Threshold VRUN1, VRUN2 Rising 1.0 1.5 2.0 V

VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V,VSENSE1–, 2– = 5V

VOSENSE1, 2 = 0.7V,VSENSE1–, 2– = 5V l

TG1, 2 tr

TG1, 2 tf

TG Transition Time:

Rise Time

Fall Time

(Note 5)

CLOAD = 3300pF

100

BG1, 2 tr

BG1, 2 tf

BG Transition Time:

Rise Time

Fall Time

(Note 5)

CLOAD = 3300pF

120

100

TG/BG t1D Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

CLOAD = 3300pF Each Driver 60 ns

BG/TG t2D Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

CLOAD = 3300pF Each Driver 80 ns

tON(MIN) Minimum On-Time Tested with a Square Wave (Note 6) 120 ns

INTVCC Linear Regulator

VINTVCC Internal VCC Voltage 6V < VIN < 30V 4.8 5.0 5.2 V

VLDO INT INTVCC Load Regulation ICC = 0mA to 20mA 0.2 2.0 %

Oscillator and Phase-Locked Loop

fNOM Nominal Frequency VPLLFLTR = 1.2V 360 400 440 kHz

fLOW Lowest Frequency VPLLFLTR = 0V 230 260 290 kHz

fHIGH Highest Frequency VPLLFLTR ≥ 2.4V 480 550 590 kHz

IPLLFLTR Phase Detector Output Current

Sinking Capability

Sourcing Capability

VPLLFLTR = 1.2V

fPLLIN < fNOM

fPLLIN > fNOM

–17

µA

LTC3828

3828fc

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formulas:

LTC3828UH: TJ = TA + (PD • 34°C/W)

LTC3828G: TJ = TA + (PD • 95°C/W)

Note 3: The IC is tested in a feedback loop that servos VITH1, 2 to a

speciﬁ ed voltage and measures the resultant VOSENSE1, 2.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 5: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 6: The minimum on-time condition is speciﬁ ed for an inductor

peak-to-peak ripple current ≥40% of IMAX (see minimum on-time

considerations in the Applications Information section).

Note 7: The LTC3828E is guaranteed to meet performance speciﬁ cations

over the –40°C to 85°C operating temperature range as assured by design,

characterization and correlation with statistical process controls.

Note 8: This parameter is guaranteed by design.

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁ ciency vs Output Current

and Mode (Figure 14)

Efﬁ ciency vs Output Current

(Figure 14)

Efﬁ ciency vs Input Voltage

(Figure 14)

OUTPUT CURRENT (A)

0.001

EFFICIENCY (%)

3828 G01

0.01 0.1 1

100

Burst Mode

OPERATION

FORCED

CONTINUOUS

MODE

CONSTANT

FREQUENCY

(BURST DISABLE)

VIN =15V

VOUT = 5V

f = 260kHz

OUTPUT CURRENT (A)

0.001 10

0.01 0.1 1

EFFICIENCY (%)

3828 G02

100

VOUT = 5V

f = 260kHz

VIN = 7V

VIN = 20V

VIN = 15V

INPUT VOLTAGE (V

EFFICIENCY (%)

100

3828 G03

10 15 20 30

VOUT = 5V

IOUT = 3A

f = 260kHz

TA = 25°C unless otherwise noted.

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 15V, VRUN1, 2 = 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PGOOD Output

VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V

IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA

VPG PGOOD Trip Level, Either Controller VOSENSE with Respect to Set Output Voltage

VOSENSE Ramping Down

VOSENSE Ramping Up

–6

–7.5

7.5

–9.5

9.5

LTC3828

3828fc

Oscillator Frequency vs

Temperature TRCKSS Current vs Temperature

Current Sense Pin Input Current vs

Temperature

Maximum Current Sense

Threshold vs Temperature INTVCC Voltage vs Temperature Load Regulation

Supply Current vs Input Voltage

(Figure 14) Internal 5V LDO Line Regulation

Undervoltage Lockout

vs Temperature

INPUT VOLTAGE (V)

SUPPLY CURRENT (µA)

1200

1000

800

600

400

200

05101520

3828 G04

25 30

BOTH CONTROLLERS ON

SHUTDOWN

INTVCC VOLTAGE (V)

3828 G05

5.2

5.0

4.8

4.6

4.4

4.2

4.0

INPUT VOLTAGE (V)

0 5 10 15 20 25 30

ILOAD = 1mA

TEMPERATURE (°C)

–50

3.8

3.6

3.4

3.2

3.0 100

3828 G06

–25 0 25 50 75 125

UNDERVOLTAGE LOCKOUT (V)

TEMPERATURE (°C)

–50

700

600

500

400

300

200

100

25 75

3828 G07

–25 0 50 100 125

FREQUENCY (kHz)

VPLLFLTR = 2.4V

VPLLFLTR = 1.2V

VPLLFLTR = 0V

TEMPERATURE (°C)

–50 25 75

–25 0 50 100 125

TRCKSS CURRENT (µA)

1.5

1.3

1.1

0.9

0.7

0.5

3828 G08

TEMPERATURE (°C)

–50 25 75

–25 0 50 100 125

3828 G09

CURRENT SENSE INPUT CURRENT (µA)

TEMPERATURE (°C)

–50 25 75

–25 0 50 100 125

VSENSE (mV)

3828 G10

VOUT = 5V

TEMPERATURE (°C)

–50 25 75

–25 0 50 100 125

5.1

5.0

4.9

4.8

4.7

3828 G11

INTVCC VOLTAGE (V)

LOAD CURRENT (A)

NORMALIZED VOUT (%)

–0.2

–0.1

3828 G12

–0.3

–0.4 1235

FCB = 0V

VIN = 15V

FIGURE 14

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise noted.

LTC3828

3828fc

TYPICAL PERFORMANCE CHARACTERISTICS

Current Sense Threshold vs

ITH Voltage

Dropout Voltage vs Output Current

(Figure 14) SENSE Pins Total Source Current

Soft Start-Up

(Figure 14, with Coincident

Tracking)

VITH (V)

VSENSE (mV)

–10

–20 2.0

3828 G16

0.5 1.0 1.5 2.5

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (V)

4.0

3828 G17

1.00.5 1.5 2.5 3.5

2.0 3.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VSENSE COMMON MODE VOLTAGE (V)

ISENSE (µA)

24356

3828 G18

100

–50

–100

Soft Start-Up

(Figure 14, with Ratiometric

Tracking)

Soft Start-Up

(Figure 14, with Internal Soft

Start-Up)

3828 G19

VOUT1

1V/DIV

VOUT2

1V/DIV

5ms/DIV

VIN = 12V

VOUT1 = 5V

VOUT2 = 3.3V 3828 G20

VOUT1

1V/DIV

VOUT2

1V/DIV

2ms/DIV

VIN = 12V

VOUT1 = 5V

VOUT2 = 3.3V 3828 G21

VOUT1

1V/DIV

VOUT2

1V/DIV

100µs/DIV

VIN = 12V

VOUT1 = 5V

VOUT2 = 3.3V

TA = 25°C unless otherwise noted.

Maximum Current Sense

Threshold vs Duty Factor

Maximum Current Sense

Threshold vs Percent of Nominal

Output Voltage (Foldback)

Maximum Current Sense

Threshold vs Sense Common

Mode Voltage

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

VSENSE (mV)

0.75

3828 G14

0.25 0.5 1.0

DUTY FACTOR (%)

VSENSE (mV)

3828 G13

020 40 100

60 80

COMM0N MODE VOLTAGE (V)

VSENSE (mV)

3828 G15

60 1235

LTC3828

3828fc

Load Step: Burst Mode Operation

(Figure 14)

Load Step: Continuous Mode

(Figure 14)

PIN FUNCTIONS

(SSOP/QFN)

Input Source/Capacitor

Instantaneous Current

(Figure 14)

3828 G22

VOUT1

100mV/DIV

VOUT2

100mV/DIV

IL1

2A/DIV

50µs/DIV

VIN = 12V

VOUT1 = 5V

VOUT2 = 3.3V

LOAD STEP = 0A TO 3A

WITH RATIOMETRIC TRACKING 3828 G23

VOUT1

100mV/DIV

VOUT2

100mV/DIV

IL1

2A/DIV

50µs/DIV

VIN = 12V

VOUT1 = 5V

VOUT2 = 3.3V

LOAD STEP = 0A TO 3A

WITH RATIOMETRIC TRACKING

3828 G24

SW1

20V/DIV

SW2

20V/DIV

IIN

25A/DIV

VIN

RIPPLE

50mV/DIV

500ns/DIV

VIN = 12V

VOUT1 = 5V

VOUT2 = 3.3V

IOUT5 = IOUT3.3 = 2A

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C unless otherwise noted.

Burst Mode Operation

(Figure 14)

Constant Frequency (Burst

Inhibit) Operation (Figure 14)

3828 G25

VOUT

20mV/DIV

1A/DIV

100µs/DIV

VIN = 12V

VOUT = 5V

VFCB = OPEN

IOUT = 20mA 3828 G26

VOUT

20mV/DIV

0.5A/DIV

2µs/DIV

VIN = 12V

VOUT = 5V

VFCB = 5V

IOUT = 20mA

ITH1, ITH2 (Pins 2, 13/Pins 30, 12): Error Ampliﬁ er Output

and Switching Regulator Compensation Point. Each as-

sociated channels’ current comparator trip point increases

with this control voltage.

PHSMD (Pin 4, QFN Only): Control input to phase selector

which determines the phase relationship between control-

ler 1, controller 2 and the clockout signal.

VOSENSE1, VOSENSE2 (Pins 5, 14/Pins 1, 13): Error Ampliﬁ er

Feedback Input. Receives the remotely-sensed feedback

voltage for each controller from an external resistive divider

across the output.

PLLFLTR (Pin 6/Pin 2): Filter Connection for Phase-Locked

Loop. Alternatively, this pin can be driven with an AC or

DC voltage source to vary the frequency of the internal

oscillator.

FCB/PLLIN (Pin 8/Pin 5): Forced Continuous Control Input

and External Synchronization Input to Phase Detector. Pull-

ing this pin below 0.8V will force continuous synchronous

operation. Feeding an external clock signal will synchronize

the LTC3828 to the external clock.

LTC3828

3828fc

PIN FUNCTIONS

SGND (Pin 9/Pin 6): Small-Signal Ground. Common to

both controllers, this pin must be routed separately from

high current grounds to the common (–) terminals of the

COUT capacitors.

TRCKSS2, TRCKSS1 (Pins 10, 1/Pins 7, 29): Soft-Start

and Output Voltage Tracking Inputs. When one channel is

conﬁ gured to be the master of two outputs a capacitor to

ground at this pin sets the ramp rate. The slave channel

tracks the output of the master channel by reproducing the

VFB voltage of the master channel with a resistor divider

and applying that voltage to its track pin. An internal 1.2µA

soft-start current is always charging these pins.

SENSE2–, SENSE1– (Pins 11, 4/Pins 10, 32): The (–)

Input to the Differential Current Comparators.

SENSE2+, SENSE1+ (Pins 12, 3/Pins 11, 31): The (+)

Input to the Differential Current Comparators. The ITH pin

voltage and controlled offsets between the SENSE– and

SENSE+ pins in conjunction with RSENSE set the current

trip threshold.

RUN2, RUN1 (Pins 15, 7/Pins 14, 3): Run Control Inputs.

Forcing RUN pins below 1V would shut down the circuitry

required for that particular channel. Forcing the RUN pins

over 2V would turn on the IC.

BOOST2, BOOST1 (Pins 16, 26/Pins 15, 26): Bootstrapped

Supplies to the Topside Floating Drivers. Capacitors

are connected between the boost and switch pins and

Schottky diodes are tied between the boost and INTVCC

pins. Voltage swing at the boost pins is from INTVCC to

(VIN + INTVCC).

TG2, TG1 (Pins 17, 25/Pins 16, 25): High Current Gate

Drives for Top N-Channel MOSFETs. These are the outputs

of ﬂ oating drivers with a voltage swing equal to INTVCC

– 0.5V superimposed on the switch node voltage SW.

SW2, SW1 (Pins 18, 24/Pins 17, 24): Switch Node

Connections to Inductors. Voltage swing at these pins

is from a Schottky diode (external) voltage drop below

ground to VIN.

BG2, BG1 (Pins 19, 20/Pins 18, 19): High Current Gate

Drives for Bottom (Synchronous) N-Channel MOSFETs.

Voltage swing at these pins is from ground to INTVCC.

PGND (Pin 21/Pin 20): Driver Power Ground. Connects to

the sources of bottom (synchronous) N-channel MOSFETs,

anodes of the Schottky rectiﬁ ers and the (–) terminal(s)

of CIN.

DRVCC (Pin 21 QFN Only): External Power Input to Gate

Drives. It can be connected with INTVCC together and use

INTVCC as gate drives power supply.

INTVCC (Pin 22/Pin 22): Output of the Internal 5V Linear

Low Dropout Regulator. The driver and control circuits are

powered from this voltage source. Must be decoupled to

power ground with a minimum of 4.7µF tantalum or other

low ESR capacitor.

VIN (Pin 23/Pin 23): Main Supply Pin. A bypass capaci-

tor should be tied between this pin and the signal ground

pin.

PGOOD (Pin 27/Pin 27): Open-Drain Logic Output. PGOOD

is pulled to ground when the voltage on either VOSENSE

pin is not within ±7.5% of its set point.

CLKOUT (Pin 28/Pin 28): Output clock signal available to

daisy-chain other controller ICs for additional MOSFET

driver stages/phases.

NC (Pins 8, 9 QFN Only): These “no connect” pins are

not tied internally to anything. On the PC layout, these pin

landings should be connected to the SGND plane under

the IC.

Exposed Pad (Pin 33, QFN Only): Signal Ground. Must

be soldered to the PCB, providing a local ground for the

control components of the IC, and be tied to the PGND

pin under the IC.

(SSOP/QFN)

LTC3828

3828fc

BLOCK DIAGRAM

SWITCH

LOGIC

–

VIN

4.5V BINH

CLK2

CLK1

0.18µA

–

FCB

–

0.8V

VREF

INTERNAL

SUPPLY

RLP

CLP

FCB/PLLIN

INTVCC

SGND (UH PACKAGE PAD)

5V LDO REG

SHDN

0.55V

TOP

BOOST

TG CB

CIN

PGND

BOT BG

DRVCC

VIN

OUT

3828 FD/F01

RSENSE

VOSENSE

DROP

OUT

DET

RUN

SOFT-

START

BOT

TOP ON

OSCILLATOR

PHASE DET

PLLFLTR

CLKOUT

FCB

0.86V

0.80V OV

VFB

–

4(VFB)

RST

SHDN

RUN

ITH CC

CC2

4s VFB

0.86V

SLOPE COMP

3mV

–

SENSE–

SENSE+

INTVCC

30k

45k

2.4V

45k

30k

100k

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

CSS

+– –+

PHASE LOGIC

PHSMD

–

PGOOD VOSENSE1

VOSENSE2

0.86V

0.74V

0.86V

0.74V

PLL

DETECTOR

TRCKSS

1.2µA

DRVCC

Figure 1

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

Main Control Loop

The IC uses a constant frequency, current mode step-down

architecture with the two controller channels operating

180 degrees out of phase. During normal operation, each

top MOSFET is turned on when the clock for that channel

sets the RS latch, and turned off when the main current

comparator, I1, resets the RS latch. The peak inductor

current at which I1 resets the RS latch is controlled by

the voltage on the ITH pin, which is the output of each

error ampliﬁ er EA. The VOSENSE pin receives the voltage

feedback signal, which is compared to the internal refer-

ence voltage by the EA. When the load current increases,

it causes a slight decrease in VOSENSE relative to the 0.8V

reference, which in turn causes the ITH voltage to increase

until the average inductor current matches the new load

current. After the top MOSFET has turned off, the bottom

MOSFET is turned on until either the inductor current

starts to reverse, as indicated by current comparator I2,

or the beginning of the next cycle.

The top MOSFET drivers are biased from ﬂ oating bootstrap

capacitor, CB, which normally is recharged during each off

cycle through an external diode when the top MOSFET

turns off. As VIN decreases to a voltage close to VOUT

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET off for about 400ns every

tenth cycle to allow CB to recharge.

The main control loop is shut down by pulling the RUN

pin low. When the RUN pin reaches 1.5V, the main control

loop is enabled. When both RUN1 and RUN2 are low,

all controller functions are shut down, including the 5V

regulator.

Low Current Operation

The FCB/PLLIN pin is a multifunction pin providing two

functions: 1) to accept external clock signal; and 2) to

select among three modes of light load operations. When

the FCB/PLLIN pin voltage is below 0.75V, the control-

ler forces continuous PWM current mode operation. In

this mode, the top and bottom MOSFETs are alternately

turned on to maintain the output voltage independent of

direction of inductor current. When the FCB/PLLIN pin is

below VINTVCC – 0.7V but greater than 0.8V, the controller

enters Burst Mode operation. Burst Mode operation sets

a minimum output current level before inhibiting the top

switch and turns off the synchronous MOSFET(s) when

the inductor current goes negative. This combination of

requirements will, at low currents, force the ITH pin below

a voltage threshold that will temporarily inhibit turn-on of

both output MOSFETs until the output voltage drops. There

is 60mV of hysteresis in the burst comparator B tied to

the ITH pin. This hysteresis produces output signals to the

MOSFETs that turn them on for several cycles, followed by

a variable “sleep” interval depending upon the load current.

The resultant output voltage ripple is held to a very small

value by having the hysteretic comparator after the error

ampliﬁ er gain block. When the FCB/PLLIN pin voltage is

above 4.8V, the controller operates in constant frequency

mode and the synchronous MOSFET is turned off when

inductor current nears zero in each cycle.

In order to prevent erratic operation if no external con-

nections are made to the FCB/PLLIN pin, the FCB/PLLIN

pin has a 0.18µA internal current source pulling the pin

high.

The following table summarizes the possible states avail-

able on the FCB/PLLIN pin:

Table 1

FCB/PLLIN PIN CONDITION

0V to 0.75V Forced Continuous Both Controllers

(Current Reversal Allowed—

Burst Inhibited)

0.85V < VFCB/PLLIN < 4.3V

or Open

Minimum Peak Current Induces

Burst Mode Operation

No Current Reversal Allowed

>4.8V Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed

No Minimum Peak Current

Besides providing a logic input to select light load op-

eration mode, the FCB/PLLIN pin acts as the input for

external clock synchronization. Upon detecting the pres-

ence of an external clock signal, channel 1 will lock on to

this external clock and this will be followed by channel 2

(see Frequency Synchronization section). The LTC3828

defaults to forced continuous mode when sychronized to

an external clock.

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the FCB/PLLIN pin.

The output of the phase detector at the PLLFLTR pin is

also the DC frequency control input of the oscillator that

operates over a 260kHz to 550kHz range corresponding

to a DC voltage input from 0V to 2.4V. When locked, the

PLL aligns the turn on of the top MOSFET to the rising

edge of the synchronizing signal.

The internal master oscillator runs at a frequency twelve

times that of each phase switching frequency. The PHSMD

pin (UH package only) determines the relative phases

between the internal controllers as well as the CLKOUT

signal as shown in Table 2. The phases tabulated are rela-

tive to zero phase being deﬁ ned as the rising edge of the

top gate (TG1) driver output of controller 1.

Table 2

VPHSMD GND OPEN INTVCC

Controller 1 0° 0° 0°

Controller 2 180° 180° 240°

CLKOUT 60° 90° 120°

The CLKOUT signal can be used to synchronize additional

power stages in a multiphase power supply solution feeding

a single, high current output or separate outputs. Input

capacitance ESR requirements and efﬁ ciency losses are

substantially reduced because the peak current drawn from

the input capacitor is effectively divided by the number of

phases used and power loss is proportional to the RMS

current squared. A 2-phase, single output voltage imple-

mentation can reduce input path power loss by 75% and

radically reduce the required RMS current rating of the

input capacitor(s).

In the G28 package, CLKOUT is 90° out of phase with

channel 1 and channel 2.

Constant Frequency Operation

When the FCB/PLLIN pin is tied to INTVCC, Burst Mode

operation is disabled and the forced minimum output

current requirement is removed. This provides constant

frequency, discontinuous current (preventing reverse

inductor current) operation over the widest possible output

current range. This constant frequency operation is not

as efﬁ cient as Burst Mode operation, but does provide a

lower noise, constant frequency operating mode down

to approximately 1% of the designed maximum output

current.

Continuous Current (PWM) Operation

Tying the FCB/PLLIN pin to ground will force continuous

current operation. This is the least efﬁ cient operating mode,

but may be desirable in certain applications. The output

can source or sink current in this mode. When sinking

current while in forced continuous operation, current will

be forced back into the main power supply potentially

boosting the input supply level.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internal

MOSFET. The MOSFET turns on and pulls the pin down

when the enabled channel’s output is not within ±7.5% of

the nominal output level as determined by the feedback

resistor divider. When the enabled channel’s output meets

the ±7.5% requirement, the MOSFET is turned off within

10µs and the pin is allowed to be pulled up by an external

resistor to source of up to 5.5V. If either channel 1 or chan-

nel 2 is shut down by driving its RUN pin low, PGOOD will

ignore the state of that channel’s ouput.

Foldback Current

Foldback current limiting is activated when the output

voltage falls below 70% of its nominal level. If a short

is present, a safe, low output current is provided due to

internal current foldback and actual power wasted is low

due to the efﬁ cient nature of the current mode switching

regulator. This function is disabled at start-up.

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC3728 and the LTC3828 family of dual high efﬁ -

ciency DC/DC controllers brings the considerable beneﬁ ts

of 2-phase operation to portable applications for the ﬁ rst

time. Notebook computers, PDAs, handheld terminals and

automotive electronics will all beneﬁ t from the lower input

ﬁ ltering requirement, reduced electromagnetic interference

(EMI) and increased efﬁ ciency associated with 2-phase

operation.

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single-phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current ﬂ owing from the

input capacitor, requiring the use of more expensive input

capacitors and increasing both EMI and losses in the input

capacitor and battery.

With 2-phase operation, the two channels of the dual-

switching regulator are operated 180 degrees out of phase.

This effectively interleaves the current pulses drawn by the

switches, greatly reducing the overlap time where they add

together. The result is a signiﬁ cant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁ ciency.

Figure 2 compares the input waveforms for a representa-

tive single-phase dual switching regulator to the LTC3828

2-phase dual switching regulator. An actual measurement of

the RMS input current under these conditions shows that

2-phase operation dropped the input current from 2.6ARMS

to 1.9ARMS. While this is an impressive reduction in itself,

remember that the power losses are proportional to IRMS2,

meaning that the actual power wasted is reduced by a fac-

tor of 1.86. The reduced input ripple voltage also means

less power is lost in the input power path, which could

include batteries, switches, trace/connector resistances

and protection circuitry. Improvements in both conducted

and radiated EMI also directly accrue as a result of the

reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage VIN (Duty Cycle = VOUT/VIN). Figure 3 shows how

the RMS input current varies for single-phase and 2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

It can readily be seen that the advantages of 2-phase opera-

tion are not just limited to a narrow operating range, but

in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce

the input capacitor requirement to that for just one channel

operating at maximum current and 50% duty cycle.

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

100mA/DIV

IN(MEAS) = 2.6ARMS IN(MEAS) = 1.9ARMS

(a) (b)

Figure 2. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC3828 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efﬁ ciency

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

INPUT VOLTAGE (V)

INPUT RMS CURRENT (A)

3.0

2.5

2.0

1.5

1.0

0.5

010 20 30 40

3828 F03

SINGLE-PHASE

DUAL CONTROLLER

2-PHASE

DUAL CONTROLLER

VO1 = 5V/3A

VO2 = 3.3V/3A

Figure 3. RMS Input Current Comparison

APPLICATIONS INFORMATION

Output Voltage Tracking

The LTC3828 allows the user to program how the channel

outputs ramp up by means of the TRCKSS pins. Through

these pins, the channel outputs can be set up to either

coincidentally or ratiometrically tracking, as shown in

Figure 4.

The TRCKSS pins act as clamps on the channels’ reference

voltages. VOUT is referenced to the TRCKSS voltage when

the TRCKSS < 0.8V and to the internal precision reference

when TRCKSS > 0.8V.

To implement the tracking in Figure 4a, connect an extra

resistive divider to the output of the master channel and

connect its midpoint to the slave channel’s TRCKSS pin.

The ratio of this divider should be selected the same as

that of channel 2’s feedback divider (Figure 5). In this

tracking mode, the master channel’s output must be

set higher than slave channel’s output. To implement

the ratiometric tracking in Figure 4b, no extra divider is

needed; simply connect one of TRCKSS pins to the other

channel’s VFB pin (Figure 5).

TIME

(4a) Coincident Tracking

VOUT1

VOUT2

OUTPUT VOLTAGE

TIME 3828 F04

(4b) Ratiometric Tracking

VOUT1

VOUT2

OUTPUT VOLTAGE

Figure 4. Two Different Modes of Output Voltage Tracking

LTC3828

3828fc

APPLICATIONS INFORMATION

By selecting different resistors, the LTC3828 can achieve

different modes of tracking including the two in Figure 4.

Figure 6 helps to explaining the tracking function. At the

input stage of an error ampliﬁ er, two diodes are used to

clamp the equivalent reference voltage and an additional

diode is used to match the shifted common mode voltage.

The top two current sources are of the same value. When

the TRCKSS voltage is low, switch S1 is on and VOSENSE

follows the TRCKSS voltage. When the TRCKSS voltage

is close to 0.8V, the reference voltage, switch S1, is off

and VOSENSE follows the reference voltage. The regulation

for both channels’ outputs are not affected by the tracking

mode. In the ratiometric tracking mode, the two channels

do not exhibit cross talk.

The number of resistors in Figure 5a can be further reduced

with the scheme in Figure 7.

In a system that requires more than two tracked supplies,

multiple LTC3828s can be daisy-chained through the

TRCKSS1 pin. TRCKSS1 clamps channel 1’s reference in

the same manner TRCKSS2 clamps channel 2. To eliminate

the possibility of multiple LTC3828s coming on at different

times, only the master LTC3828’s TRCKSS1 pin should

be connected to a soft-start capacitor. Figure 8 shows the

circuit with four outputs. Three of them are programmed

in the coincident mode while the fourth one tracks ratio-

metrically. If output tracking is not needed, the TRCKSS pins

are used as soft start-up pins. The capacitors connected

to those pins set the soft-start ramping up speed.

Figure 15 is a basic LTC3828 application circuit. External

component selection is driven by the load requirement,

and begins with the selection of RSENSE and the inductor

value. Next, the power MOSFETs and D1 are selected.

Finally, CIN and COUT are selected. The circuit shown in

Figure 15 is conﬁ gured for operation up to an input voltage

of 28V (limited by the external MOSFETs).

RSENSE Selection For Output Current

RSENSE is chosen based on the required output current.

The current comparator has a maximum threshold of

75mV/RSENSE and an input common mode range of SGND

R3 R1

R4 R2

VOUT2

(5a) Coincident Tracking Setup

VOSENSE1

TRCKSS2

VOSENSE2

VOUT1

VOUT2

3828 F05

(5b) Ratiometric Tracking Setup

VOSENSE1

TRCKSS2

VOSENSE2

VOUT1

Figure 5. Setup for Coincident and Ratiometric Tracking

OUT OUT

208

408

⎛

⎝

⎜⎞

⎠

⎟

.–, .–

–

TRCKSS

0.8V

VOSENSE

3828 F06

R1 R4

VOUT1 VOUT2

TO TRCKSS2 PIN

TO VOSENSE1 PIN

TO VOSENSE2 PIN

R2 R5

3828 F07

Figure 7. Alternative Setup for Coincident Tracking

OUT OUT

308

508

+=+==

⎛

.–, .–

⎝⎝

⎜⎞

⎠

⎟

Figure 6. Equivalent Input Circuit of

Error Ampliﬁ er of Channel 2

LTC3828

3828fc

APPLICATIONS INFORMATION

to 1.1(INTVCC). The current comparator threshold sets the

peak of the inductor current, yielding a maximum average

output current IMAX equal to the peak value less half the

peak-to-peak ripple current, ΔIL.

Allowing a margin for variations in the IC and external

component values yields:

RmV

SENSE

MAX

=50

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to the

internal compensation required to meet stability criterion

for buck regulators operating at greater than 50% duty

factor. A curve is provided to estimate this reduction in

peak output current level depending upon the operating

duty factor.

Operating Frequency

The IC uses a constant frequency phase-lockable ar-

chitecture with the frequency determined by an internal

capacitor. This capacitor is charged by a ﬁ xed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 9. As the operating frequency

is increased the gate charge losses will be higher, reducing

efﬁ ciency (see Efﬁ ciency Considerations). The maximum

switching frequency is approximately 550kHz.

VOSENSE1

CSS

R3R1

VOUT1

R2 R2

VOSENSE2

VOUT2

VOUT4

VOUT3

TRCKSS1

TRCKSS2

LTC3828

“MASTER”

TRCKSS1

VOSENSE1 VOSENSE2

TRCKSS2

LTC3828

“SLAVE”

(8a) Circuit Setup

TIME 3828 F08

(8b) Output Voltage

VOUT1

VOUT3

VOUT4

VOUT2

OUTPUT VOLTAGE

Figure 8. Four Outputs with Tracking and Ratiometric Sequencing

OUT OUT OUT

208

123

===

.–, .–.88 15

208

–, .–

VOUT

⎛

⎝

⎜⎞

⎠

⎟

OPERATING FREQUENCY (kHz)

200 300 400 500 600

PLLFLTR PIN VOLTAGE (V)

3828 F09

2.5

2.0

1.5

1.0

0.5

Figure 9. PLLFLTR Pin Voltage vs Frequency

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efﬁ ciency. A higher

frequency generally results in lower efﬁ ciency because

LTC3828

3828fc

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

The inductor value has a direct effect on ripple current.

The inductor ripple current ΔIL decreases with higher

inductance or frequency and increases with higher VIN:

ΔIfL

L OUT OUT

=⎛

⎝

⎜⎞

⎠

⎟

()( ) –

Accepting larger values of ΔIL allows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is ΔIL = 0.3(IMAX). The maximum

ΔIL occurs at the maximum input voltage.

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit determined by RSENSE. Lower

inductor values (higher ΔIL) will cause this to occur at

lower load currents, which can cause a dip in efﬁ ciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

Inductor Selection

Usually, high inductance is preferred for small current

ripple and low core loss. Unfortunately, increased induc-

tance requires more turns of wire or small air gap of the

inductor, resulting in high copper loss or low saturation

current. Once the value of L is known, the actual inductor

must be selected. There are two popular types of core

material of commercial available inductors.

Ferrite core inductors usually have very low core loss and

are preferred at high switching frequencies, so design

goals can concentrate on copper loss and preventing

saturation. However, ferrite core saturates “hard”, which

means that inductance collapses abruptly when the peak

design current is exceeded. This results in an abrupt in-

crease in inductor ripple current and consequent output

voltage ripple. One advantage of the LTC3828 is its current

mode control that detects and limits cycle-by-cycle peak

inductor current. Therefore, accurate and fast protection

is achieved if the inductor is saturated in steady state or

during transient mode.

Powder iron inductors usually saturate “soft”, which

means the inductance drops in a linear fashion when the

current increases. However, the core loss of the powder

iron inductor is usually higher than the ferrite inductor. So

design with high switching frequency should pay attention

to the inductor core loss too.

Inductor manufacturers usually provide inductance, DCR,

(peak) saturation current and (DC) heating current ratings

in the inductor data sheet. A good supply design should

not exceed the saturation and heating current rating of

the inductor.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each

controller in the LTC3828: One N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for

the bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCC voltage.

This voltage is typically 5V during start-up. Consequently,

logic-level threshold MOSFETs must be used in most ap-

plications. The only exception is if low input voltage is ex-

pected (VIN < 5V); then, sub-logic level threshold MOSFETs

(VGS(TH) < 3V) should be used. Pay close attention to the

BVDSS speciﬁ cation for the MOSFETs as well; most of the

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”

resistance, RDS(ON), Miller capacitance, CMILLER, input

voltage and maximum output current. Miller capacitance,

CMILLER, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers’ data

sheet. CMILLER is equal to the increase in gate charge

along the horizontal axis while the curve is approximately

ﬂ at divided by the speciﬁ ed change in VDS. This result is

then multiplied by the ratio of the application applied VDS

to the Gate charge curve speciﬁ ed VDS. When the IC is

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

Main SwitchDuty Cycle V

OUT

APPLICATIONS INFORMATION

LTC3828

3828fc

Synchronous SwitchDuty Cycle VV

IN OUT

=–

The MOSFET power dissipations at maximum output

current are given by:

VIR

VIRC

VVV

MAIN OUT

IN MAX DS ON

IN MAX DR MILLER

INTVCC THMIN THMIN

()

⎛

⎝

⎜⎞

⎠

⎟

()( )

⎡

⎣

⎢⎤

⎦

⎥

()

δ()

•

–

PVV

VIR

SYNC IN OUT

MAX DS ON

()

–()

21δ

where δ is the temperature dependency of RDS(ON) and

RDR (approximately 2) is the effective driver resistance

at the MOSFET’s Miller threshold voltage. VTHMIN is the

typical MOSFET minimum threshold voltage.

Both MOSFETs have I2R losses while the topside N-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For VIN < 12V

the high current efﬁ ciency generally improves with larger

MOSFETs, while for VIN ≥ 12V the transition losses rapidly

increase to the point that the use of a higher RDS(ON) device

with lower CMILLER actually provides higher efﬁ ciency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short circuit when the synchronous switch is on close

to 100% of the period.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

The Schottky diode D1 shown in Figure 1 conducts during

the dead-time between the conduction of the two power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the dead-

time and requiring a reverse recovery period that could

cost efﬁ ciency at high VIN. A 1A to 3A Schottky is generally

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance.

CIN and COUT Selection

The selection of CIN is simpliﬁ ed by the multiphase ar-

chitecture and its impact on the worst-case RMS current

drawn through the input network (battery/fuse/capacitor).

It can be shown that the worst-case RMS current occurs

when only one controller is operating. The controller with

the highest (VOUT)(IOUT) product needs to be used in the

formula below to determine the maximum RMS current

requirement. Increasing the output current, drawn from

the other out-of-phase controller, will actually decrease the

input RMS ripple current from this maximum value (see

Figure 3). The out-of-phase technique typically reduces

the input capacitor’s RMS ripple current by a factor of

30% to 70% when compared to a single phase power

supply solution.

The type of input capacitor, value and ESR rating have

efﬁ ciency effects that need to be considered in the selec-

tion process. The capacitance value chosen should be

sufﬁ cient to store adequate charge to keep high peak

battery currents down. 20µF to 40µF is usually sufﬁ cient

for a 25W output supply operating at 260kHz. The ESR of

the capacitor is important for capacitor power dissipation

as well as overall battery efﬁ ciency. All of the power (RMS

ripple current • ESR) not only heats up the capacitor but

wastes power from the battery.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON

and switcher-rated electrolytic capacitors can be used

as input capacitors, but each has drawbacks: ceramic

voltage coefﬁ cients are very high and may have audible

piezoelectric effects; tantalums need to be surge rated;

OS-CONs suffer from higher inductance, larger case size

and limited surface-mount applicability; electrolytics’

higher ESR and dryout possibility require several to be

used. Multiphase systems allow the lowest amount of

capacitance overall. As little as one 22µF or two to three

10µF ceramic capacitors are an ideal choice in a 20W to

35W power supply due to their extremely low ESR. Even

though the capacitance at 20V is substantially below their

rating at zero bias, very low ESR loss makes ceramics

APPLICATIONS INFORMATION

LTC3828

3828fc

an ideal candidate for highest efﬁ ciency battery operated

systems. Also consider parallel ceramic and high quality

electrolytic capacitors as an effective means of achieving

ESR and bulk capacitance goals.

In continuous mode, the source current of the top N-chan-

nel MOSFET is a square wave of duty cycle VOUT/VIN. To

prevent large voltage transients, a low ESR input capaci-

tor sized for the maximum RMS current of one channel

must be used. The maximum RMS capacitor current is

given by:

C quiredI I

VVV

IN RMS MAX

OUT IN OUT

≈−

()

[]

This formula has a maximum at VIN = 2VOUT

, where

IRMS = IOUT/2. This simple worst-case condition is com-

monly used for design because even signiﬁ cant deviations

do not offer much relief. Note that capacitor manufacturer’s

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the capaci-

tor, or to choose a capacitor rated at a higher temperature

than required. Several capacitors may also be paralleled

to meet size or height requirements in the design. Always

consult the manufacturer if there is any question.

The beneﬁ t of the LTC3828 multiphase clocking can be

calculated by using the equation above for the higher

power controller and then calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power lost is lower when

both controllers are operating due to the interleaving of

current pulses through the input capacitor’s ESR. This is

why the input capacitor’s requirement calculated above for

the worst-case controller is adequate for the dual controller

design. Remember that input protection fuse resistance,

battery resistance and PC board trace resistance losses are

also reduced due to the reduced peak currents in a multi-

phase system. The overall beneﬁ t of a multiphase design

will only be fully realized when the source impedance of

the power supply/battery is included in the efﬁ ciency test-

ing. The drains of the two top MOSFETS should be placed

within 1cm of each other and share a common CIN(s).

Separating the drains and CIN may produce undesirable

voltage and current resonances at VIN.

The selection of COUT is driven by the required output

voltage ripple and load transient response. Both the ca-

pacitor effective series resistance (ESR) and capacitance

determine the output ripple:

ΔV I ESR fC

OUT L OUT

≈Δ +

⎛

⎝

⎜⎞

⎠

⎟

•1

where f = operating frequency, COUT = output capacitance

and ΔIL = ripple current in the inductor. The output ripple

is highest at maximum input voltage since ΔIL increases

with input voltage.

Usually, ceramic capacitors are used to minimize the output

voltage ripple because of their ultralow ESR. Currently,

multilayer ceramic capacitors have capacitor values up to

hundreds of µF. However, the capacitance of the ceramic

capacitors usually decreases with increased DC bias volt-

age and ambient temperature. In general, X5R or X7R type

capacitors are recommended for high performance solu-

tions. The OPTI-LOOP current mode control of LTC3828

provides stable, high performance transient response

even with all ceramic output capacitors. Manufactures

such as TDK, Taiyo Yuden, Murata and AVX provide high

performance ceramic capacitors.

When high capacitance is needed, especially for load

transient requirement, low ESR polymerized electrolytic

capacitors such as Sanyo POSCAP or Panasonic SP capaci-

tor can be used in parallel with ceramic capacitors. Other

high performance electolytic capacitor manufacturers

include AVX, KEMET and NEC. With LTC3828, a com-

bination of ceramic and low ESR electrolytic capacitors

can provide a low ripple, fast transient, high density and

cost-effective solution. Consult manufacturers for speciﬁ c

recommendations.

INTVCC Regulator

An internal P-channel low dropout regulator produces 5V

at the INTVCC pin from the VIN supply pin. INTVCC powers

the drivers and internal circuitry within the IC. The INTVCC

pin regulator can supply a peak current of 50mA and must

be bypassed to ground with a minimum of 4.7µF tantalum,

10µF special polymer, or low ESR type electrolytic capaci-

tor. A 1µF ceramic capacitor placed directly adjacent to the

INTVCC and PGND IC pins is highly recommended. Good

APPLICATIONS INFORMATION

LTC3828

3828fc

bypassing is necessary to supply the high transient cur-

rents required by the MOSFET gate drivers and to prevent

interaction between channels.

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the IC to be exceeded.

The system supply current is normally dominated by the

gate charge current. Additional external loading of the

INTVCC also needs to be taken into account for the power

dissipation calculations.

The absolute maximum rating for the INTVCC Pin is 50mA.

To prevent maximum junction temperature from being

exceeded, the input supply current must be checked

operating in continuous mode at maximum VIN.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors, CB, connected to the BOOST

pins supply the gate drive voltages for the topside MOSFETs.

Capacitor CB in the Functional Diagram is charged though

external diode DB from INTVCC when the SW pin is low.

When one of the topside MOSFETs is to be turned on, the

driver places the CB voltage across the gate source of the

desired MOSFET. This enhances the MOSFET and turns on

the topside switch. The switch node voltage, SW, rises to

VIN and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: VBOOST

= VIN + VINTVCC. The value of the boost capacitor, CB,

needs to be 100 times that of the total input capacitance

of the topside MOSFET(s). The reverse breakdown of the

external Schottky diode must be greater than VIN(MAX).

When adjusting the gate-drive level, the ﬁ nal arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efﬁ ciency has

improved. If there is no change in input current, then there

is no change in efﬁ ciency.

Output Voltage

The output voltages are each set by an external feedback

resistive divider carefully placed across the output capaci-

tor. The resultant feedback signal is compared with the

internal precision 0.800V voltage reference by the error

ampliﬁ er. The output voltage is given by the equation:

OUT =+

⎛

⎝

⎜⎞

⎠

⎟

08 1 2

where R1 and R2 are deﬁ ned in Figure 1.

SENSE+/SENSE– Pins

The common mode input range of the current comparator

sense pins is from 0V to (1.1)INTVCC. Continuous linear

operation is guaranteed throughout this range allowing

output voltage setting from 0.8V to 7.7V. A differential

NPN input stage is biased with internal resistors from an

internal 2.4V source as shown in the Functional Diagram.

This requires that current either be sourced or sunk from

the SENSE pins depending on the output voltage. If the

output voltage is below 2.4V current will ﬂ ow out of both

SENSE pins to the main output. The output can be easily

preloaded by the VOUT resistive divider to compensate

for the current comparator’s negative input bias current.

The maximum current ﬂ owing out of each pair of SENSE

pins is:

SENSE+ + ISENSE– = (2.4V – VOUT)/24k

Since VOSENSE is servoed to the 0.8V reference voltage,

we can choose R1 in Figure 1 to have a maximum value

to absorb this current.

MAX OUT

124

() .

.–

=⎛

⎝

⎜⎞

⎠

⎟

for VOUT < 2.4V

Regulating an output voltage of 1.8V, the maximum value

of R1 should be 32k. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the

sense currents; however, R1 is still bounded by the VOSENSE

feedback current.

RUN and Soft-Start

The LTC3828 RUN pins shut down their respective chan-

nels independently. The LTC3828 is put in a low quiescent

current state (IQ < 30µA) if both RUN pin voltages are

below 1V. TRCKSS pins are actively pulled to ground in

this shutdown state. Once the RUN pin voltages are above

1.5V, the respective channel of the LTC3828 is powered

APPLICATIONS INFORMATION

LTC3828

3828fc

up. The LTC3828 has the ability to either soft-start by

itself with an external soft-start capacitor or tracking the

output of the other channel or supply. When the device

is conﬁ gured to soft-start by itself, an external soft-start

capacitor should be connected to the TRCKSS pin. A soft-

start current of 1.2µA is to charge the soft-start capacitor

CSS. Note that soft-start during this mode is achieved not

by limiting the maximum output current of the controller

but by controlling the ramp rate of the output voltage.

As a matter of fact, current foldback is defeated during

soft-start or tracking. During this phase, the LTC3828 is

basically ramping the reference voltage until this voltage

is 7.5% below the 0.8V reference. The total soft-start time

can be estimated as:

SOFT-START = 0.925 • 0.8V • CSS/1.2µA

The LTC3828 is designed such that the TRCKSS pin is not

actively pulled down if only one of the channels is shut

down. In this case, the TRCKSS pin voltage could be higher

than 0.8V. If this particular channel is powered up again,

the soft-start for this particular channel is provided by an

internal soft-start timer about 450µs. The internal soft-start

timer will also be in effect if the LTC3828 is trying to track

an output supply that is already powered up.

In any case, the force continuous mode is disabled and

PGOOD signal is forced low during the ﬁ rst 90% of the

soft-start phase. This time can be estimated for external

soft-start as:

FORCE = 0.9 • 0.925 • 0.8V • CSS/1.2µA

For internal soft-start, it will be 450µs.

Fault Conditions: Current Limit and Current Foldback

The current comparators have a maximum sense volt-

age of 75mV resulting in a maximum MOSFET current

of 75mV/RSENSE. The maximum value of current limit

generally occurs with the largest VIN at the highest ambi-

ent temperature, conditions that cause the highest power

dissipation in the top MOSFET.

Each controller includes current foldback to help further

limit load current when the output is shorted to ground. If

the output falls below 70% of its nominal output level, then

the maximum sense voltage is progressively lowered from

75mV to 25mV. Under short-circuit conditions with very

low duty cycles, the controller will begin cycle skipping

in order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time, tON(MIN),

of each controller (typically 200ns), the input voltage and

inductor value:

ΔIL(SC) = tON(MIN) (VIN/L)

The resulting short-circuit current is:

ImV

SC SENSE LSC

=25 1

–()

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

much higher than nominal levels. The crowbar causes huge

currents to ﬂ ow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

A comparator monitors the output for overvoltage con-

ditions. The comparator (OV) detects overvoltage faults

greater than 7.5% above the nominal output voltage. When

this condition is sensed, the top MOSFET is turned off and

the bottom MOSFET is turned on until the overvoltage

condition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and will

therefore allow a switching regulator system having a poor

PC layout to function while the design is being debugged.

The bottom MOSFET remains on continuously for as long

as the OV condition persists; if VOUT returns to a safe level,

normal operation automatically resumes. A shorted top

MOSFET will result in a high current condition which will

open the system fuse. The switching regulator will regulate

properly with a leaky top MOSFET by altering the duty

cycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This al-

lows the top MOSFET turn-on to be locked to the rising

edge of an external source. The frequency range of the

voltage controlled oscillator is ±50% around the center

APPLICATIONS INFORMATION

LTC3828

3828fc

frequency fO. A voltage applied to the PLLFLTR pin of 1.2V

corresponds to a frequency of approximately 400kHz. The

nominal operating frequency range of the IC is 260kHz to

550kHz.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the ex-

ternal and internal oscillators. This type of phase detector

will not lock up on input frequencies close to the harmonics

of the VCO center frequency. The PLL hold-in range, ΔfH,

is equal to the capture range, ΔfC:

ΔfH = ΔfC = ±0.5 fO (260kHz-550kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

ﬁ lter network on the PLLFLTR pin.

If the external frequency, fPLLIN, is greater than the oscillator

frequency, fOSC, current is sourced continuously, pulling

up the PLLFLTR pin. When the external frequency is less

than fOSC, current is sunk continuously, pulling down

the PLLFLTR pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to the

phase difference. Thus the voltage on the PLLFLTR pin is

adjusted until the phase and frequency of the external and

internal oscillators are identical. At this stable operating

point the phase comparator output is open and the ﬁ lter

capacitor CLP holds the voltage. The IC’s FCB/PLLIN pin

must be driven from a low impedance source such as a

logic gate located close to the pin. When using multiple

ICs for a phase-locked system, the PLLFLTR pin of the

master oscillator should be biased at a voltage that will

guarantee the slave oscillator(s) ability to lock onto the

master’s frequency. A DC voltage of 0.7V to 1.7V applied

to the master oscillator’s PLLFLTR pin is recommended

in order to meet this requirement. The resultant operating

frequency can range from 300kHz to 500kHz.

The loop ﬁ lter components (CLP

, RLP) smooth out the cur-

rent pulses from the phase detector and provide a stable

input to the voltage controlled oscillator. The ﬁ lter compo-

nents CLP and RLP determine how fast the loop acquires

lock. Typically RLP =10k and CLP is 0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time dura-

tion that each controller is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

ON MIN OUT

() ()

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for each controller is approximately

120ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about 300ns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a signiﬁ cant amount of cycle skipping can occur with cor-

respondingly larger current and voltage ripple.

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

output voltage excursions under worst-case transient

loading conditions. The open-loop DC gain of the control

loop is reduced depending upon the maximum load step

speciﬁ cations. Voltage positioning can easily be added

to either or both controllers by loading the ITH pin with

a resistive divider having a Thevenin equivalent voltage

source equal to the midpoint operating voltage range of

the error ampliﬁ er, or 1.2V (see Figure 10).

APPLICATIONS INFORMATION

ITH

RT1

INTVCC

3828 F10

LTC3828

RT2

Figure 10. Active Voltage Positioning Applied to the LTC3828

LTC3828

3828fc

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error ampliﬁ er.

The maximum output voltage deviation can theoretically

be reduced to half or alternatively the amount of output

capacitance can be reduced for a particular application. A

complete explanation is included in Design Solutions 10.

(See www.linear.com)

Efﬁ ciency Considerations

The percent efﬁ ciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁ ciency and which change would

produce the most improvement. Percent efﬁ ciency can

be expressed as:

%Efﬁ ciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3828 circuits: 1) IC VIN current, 2) INTVCC

regulator current, 3) I2R losses, 4) Topside MOSFET

transition losses.

1. The VIN current has two components: the ﬁ rst is the DC

supply current given in the Electrical Characteristics table,

which excludes MOSFET driver and control currents; VIN

current typically results in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high

to low again, a packet of charge dQ moves from INTVCC

to ground. The resulting dQ/dt is a current out of INTVCC

that is typically much larger than the control circuit current.

In continuous mode, IGATECHG =f(QT + QB), where QT and

QB are the gate charges of the topside and bottom side

MOSFETs.

3. I2R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current ﬂ ows through L and

RSENSE, but is “chopped” between the topside MOSFET

and the synchronous MOSFET. If the two MOSFETs have

approximately the same RDS(ON), then the resistance of

one MOSFET can simply be summed with the resistances

of L, RSENSE and ESR to obtain I2R losses. For example, if

each RDS(ON) = 30m, RL = 50m, RSENSE = 10m and

RESR = 40m (sum of both input and output capacitance

losses), then the total resistance is 130m. This results

in losses ranging from 3% to 13% as the output current

increases from 1A to 5A for a 5V output, or a 4% to 20%

loss for a 3.3V output. Efﬁ ciency varies as the inverse

square of VOUT for the same external components and

output power level. The combined effects of increasingly

lower output voltages and higher currents required by

high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁ cant only when operating at high input

voltages (typically 15V or greater). Transition losses can

be estimated from:

Transition Loss = V

()

⎛

⎝

⎜⎞

⎠

⎟

()

()()

⎛

⎝

⎜⎞

⎠

⎟

••

–

VV V

MAX DR

MILLER

TH TH

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁ ciency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

losses can be minimized by making sure that CIN has ad-

equate charge storage and very low ESR at the switching

frequency. A 25W supply will typically require a minimum of

20µF to 40µF of capacitance having a maximum of 20m to

50m of ESR. The LTC3828 2-phase architecture typically

halves this input capacitance requirement over competing

solutions. Other losses including Schottky conduction

losses during dead-time and inductor core losses generally

account for less than 2% total additional loss.

APPLICATIONS INFORMATION

LTC3828

3828fc

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to ΔILOAD (ESR), where ESR is the effective

series resistance of COUT

. ΔILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or ring-

ing, which would indicate a stability problem. OPTI-LOOP

compensation allows the transient response to be optimized

over a wide range of output capacitance and ESR values.

The availability of the ITH pin not only allows optimization

of control loop behavior but also provides a DC coupled

and AC ﬁ ltered closed-loop response test point. The DC

step, rise time and settling at this test point truly reﬂ ects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The ITH external components shown

in the Figure 15 circuit will provide an adequate starting

point for most applications.

The ITH series RC-CC ﬁ lter sets the dominant pole-zero

loop compensation. The values can be modiﬁ ed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁ nal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1µs to 10µs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

is why it is better to look at the ITH pin signal which is in

the feedback loop and is the ﬁ ltered and compensated

control loop response. The gain of the loop will be in-

creased by increasing RC and the bandwidth of the loop

will be increased by decreasing CC. If RC is increased by

the same factor that CC is decreased, the zero frequency

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT

, causing a rapid drop in VOUT

. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • CLOAD. Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current

to about 200mA.

Automotive and Low VIN Considerations

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserve or even recharge battery packs during operation.

But before you connect, be advised: you are plugging into

the supply from hell. The main power line in an automobile

is the source of a number of nasty potential transients, in-

cluding load-dump, reverse-battery and double-battery.

Load-dump is the result of a loose battery cable. When the

cable breaks connection, the ﬁ eld collapse in the alterna-

tor can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow-truck operators ﬁ nding that a 24V jump start cranks

cold engines faster than 12V.

The network shown in Figure 11a is the most straight-

forward approach to protect a DC/DC converter from the

ravages of an automotive power line. The series diode

prevents current from ﬂ owing during reverse-battery,

while the transient suppressor clamps the input voltage

APPLICATIONS INFORMATION

LTC3828

3828fc

during load-dump. Note that the transient suppressor

should not conduct during double-battery operation, but

must still clamp the input voltage below breakdown of the

converter. Although the LTC3828 have a maximum input

voltage of 30V, most applications will also be limited to

30V by the MOSFET BVDSS.

occurs at the maximum input voltage. Tie the PLLFLTR

pin to a resistive divider from the INTVCC pin, generating

0.7V for 300kHz operation. The minimum inductance for

30% ripple current is:

ΔIV

LOUT OUT

=⎛

⎝

⎜⎞

⎠

⎟

()( ) –1

A 4.7µH inductor will produce 23% ripple current and a

3.3µH will result in 33%. The peak inductor current will

be the maximum DC value plus one half the ripple cur-

rent, or 5.84A, for the 3.3µH value. Increasing the ripple

current will also help ensure that the minimum on-time

of 100ns is not violated. The minimum on-time occurs at

maximum VIN:

V kHz ns

ON MIN OUT

IN MAX

()

== =

22 300 273

The RSENSE resistor value can be calculated by using the

maximum current sense voltage speciﬁ cation with some

accommodation for tolerances:

RmV

SENSE ≤≈Ω

584 001

Since the output voltage is below 2.4V the output resis-

tive divider will need to be sized to not only set the output

voltage but also to absorb the SENSE pin’s speciﬁ ed input

current.

VV k

MAX

OUT

124

24 08

24 18 32

() .

.–

.–.

=⎛

⎝

⎜⎞

⎠

⎟

=⎛

⎝

⎜⎞

⎠

⎟=

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

The power dissipation on the topside MOSFET can be easily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

results in: RDS(ON) = 0.035/0.022, CMILLER = 215pF. At

maximum input voltage with T(estimated) = 50°C:

APPLICATIONS INFORMATION

VIN

3828 F11a

LTC3828

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

50A IPK RATING

12V

Figure 11a. Automotive Application Protection

For applications where the main input power is 5V, tie the

VIN, INTVCC and DRVCC pins together and tie the combined

pins to the 5V input with a 1 or 2.2 resistor as shown

in Figure 11b to minimize the voltage drop caused by the

gate charge current. This will override the INTVCC regula-

tor and will prevent INTVCC from dropping too low due to

the dropout voltage. Make sure the INTVCC voltage is at

or exceeds the RDS(ON) test voltage for the MOSFET which

is typically 4.5V for logic-level devices.

Figure 11b. Setup for a 5V Input

RVIN

1Ω

CIN

*LTC3828EUH ONLY

3828 F11b

CINTVCC

4.7µF +

LTC3828

INTVCC

VIN

DRVCC*

Design Example

As a design example for one channel, assume VIN =

12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A

and f = 300kHz.

The inductance value is chosen ﬁ rst based on a 30% ripple

current assumption. The highest value of ripple current

LTC3828

3828fc

APPLICATIONS INFORMATION

VCC

VApF

kHz mW

MAIN =

()

+°°

[]

()

⎛

⎝

⎜⎞

⎠

⎟Ω

()( )

⎡

⎣

⎢⎤

⎦

⎥

()

22 5 1 0 005 50 25

0 035 22 5

24 215

523

23 300 332

.( . )( – ) •

.•

–. .

A short-circuit to ground will result in a folded back cur-

rent of:

ImV ns V

SC =Ωμ

⎛

⎝

⎜⎞

⎠

⎟=

001

120 22

33 21

.–()

with a typical value of RDS(ON) and δ = (0.005/°C)(20) =

0.1. The resulting power dissipated in the bottom MOSFET

is:

PVV

SYNC =

()( )

()

22 1 8

22 2 1 1 125 0 022

100

–. ...

which is less than under full-load conditions.

CIN is chosen for an RMS current rating of at least 3A at

temperature assuming only this channel is on. COUT is

chosen with an ESR of 0.02 for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

ORIPPLE = RESR (ΔIL) = 0.02(1.67A) = 33mVP-P

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 12. The Figure 13 illustrates the

current waveforms present in the various branches of the

2-phase synchronous regulators operating in the continu-

ous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located

within 1cm of each other with a common drain connection

at CIN? Do not attempt to split the input decoupling for

the two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return of

CINTVCC must return to the combined COUT (–) terminals.

The path formed by the top N-channel MOSFET, Schottky

diode and the CIN capacitor should have short leads and

PC trace lengths. The output capacitor (–) terminals should

be connected as close as possible to the (–) terminals

of the input capacitor by placing the capacitors next to

each other and away from the Schottky loop described

above.

3. Do the LTC3828 VOSENSE pins’ resistive dividers connect

to the (+) terminals of COUT? The resistive divider must

be connected between the (+) terminal of COUT and signal

ground. The R2 and R4 connections should not be along

the high current input feeds from the input capacitor(s).

4. Are the SENSE– and SENSE+ leads routed together with

minimum PC trace spacing? The ﬁ lter capacitor between

SENSE+ and SENSE– should be as close as possible to

the IC. Ensure accurate current sensing with Kelvin con-

nections at the SENSE resistor.

5. Is the INTVCC decoupling capacitor connected close to

the IC, between the INTVCC and the power ground pins?

This capacitor carries the MOSFET drivers current peaks.

An additional 1µF ceramic capacitor placed immediately

next to the INTVCC and PGND pins can help improve noise

performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from the

opposites channel’s voltage and current sensing feedback

pins. All of these nodes have very large and fast moving

signals and therefore should be kept on the “output side”

of the LTC3828 and occupy minimum PC trace area.

7. Use a modiﬁ ed “star ground” technique: a low imped-

ance, large copper area central grounding point on the same

side of the PC board as the input and output capacitors with

tie-ins for the bottom of the INTVCC decoupling capacitor,

the bottom of the voltage feedback resistive divider and

the SGND pin of the IC.

LTC3828

3828fc

APPLICATIONS INFORMATION

TRCKSS1

ITH1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

RUN1

FCB/PLLIN

SGND

TRCKSS2

SENSE2–

SENSE2+

ITH2

VOSENSE2

CLKOUT

PGOOD

BOOST1

TG1

SW1

VIN

INTVCC

PGND

BG1

BG2

SW2

TG2

BOOST2

RUN2

LTC3828

fIN

CB1

CB2

CINTVCC

CVIN

CIN

RIN

VIN

PGOOD

RPU VPULL_UP

<5.5V RSENSE1

RSENSE2

M1 M2

M3 M4

COUT2

VOUT2

VOUT1

COUT1

R1 R2

R3 R4

3828 F12

Figure 12. LTC3828 Recommended Printed Circuit Layout Diagram

LTC3828

3828fc

APPLICATIONS INFORMATION

RL1

SW1 RSENSE1 VOUT1

COUT1

VIN

CERAMIC

CIN

RIN +

RL2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

SW2

3728 F11

RSENSE2 VOUT2

COUT2

CERAMIC

Figure 13. Branch Current Waveforms

LTC3828

3828fc

APPLICATIONS INFORMATION

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output voltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequency of operation should be maintained over the input

voltage range down to dropout and until the output load

drops below the low current operation threshold—typically

10% to 20% of the maximum designed current level in

Burst Mode operation.

The duty cycle percentage should be maintained from cycle

to cycle in a well-designed, low noise PCB implementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regula-

tor bandwidth optimization is not required. Only after

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difﬁ cult region of operation is when one

controller channel is nearing its current comparator trip

point when the other channel is turning on its top MOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

Reduce VIN from its nominal level to verify operation

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

for inductive coupling between CIN, Schottky and the top

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

LTC3828

3828fc

APPLICATIONS INFORMATION

TRCKSS1

ITH1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

RUN1

FCB/PLLIN

SGND

TRCKSS2

SENSE2–

SENSE2+

ITH2

VOSENSE2

CLKOUT

PGOOD

BOOST1

TG1

SW1

VIN

INTVCC

PGND

BG1

BG2

SW2

TG2

BOOST2

RUN2

LTC3828EG

CB1

0.22µF

CB2

0.22µF

CINTVCC

4.7µF

CVIN

0.1µF

CIN

22µF 50V

RIN

10

PGOOD

RPU VPULL_UP

<5.5V

RSENSE1

0.015

4.7µH

RSENSE2

0.01

4.7µH

M1 M2

M3 M4

COUT2

180µF 4V

COUT1

150µF 6.3V

VOUT2

3.3V

VOUT1

VIN

7V TO 28V

20k 1%

105k 1%

20k 1%

63.4k 1%

3828 F14

33pF

180pF

1000pF

0.1µF

1000pF

15k

158k30k

1mF

1µF

CERAMIC

1µF

CERAMIC

2nF 10

10

2nF 10

10

Figure 14. LTC3828 High Efﬁ ciency Low Noise 5V/3A,

3.3V/5A, Regulator with Ratiometric Tracking

LTC3828

3828fc

APPLICATIONS INFORMATION

TRCKSS1

ITH1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

RUN1

FCB/PLLIN

SGND

TRCKSS2

SENSE2–

SENSE2+

ITH2

VOSENSE2

CLKOUT

PGOOD

BOOST1

TG1

SW1

VIN

INTVCC

PGND

BG1

BG2

SW2

TG2

BOOST2

RUN2

LTC3828EG

fIN

CB1

0.22µF

CB2

0.22µF

CINTVCC

4.7µF

CVIN

0.1µF

CIN

22µF 16V

RIN

10

PGOOD

RPU VPULL_UP

<5.5V

RSENSE1

6m

0.68µH

RSENSE2

6m

1µH

M1 M2

M3 M4

COUT2

220µF 4V

COUT1

330µF 2.5V

VOUT2

3.3V

VOUT1

1.5V

VIN

12V

20k 1%

17.4k 1%

20k 1%

63.4k 1%

3828 F15

33pF

180pF

500kHz

180pF

1000pF

0.1µF

1000pF

15k

10k

4.7k

26.1k30k

1µF

CERAMIC

1µF

CERAMIC

2nF 10

10

2nF 10

10

Figure 15. LTC3828 High Efﬁ ciency Low Noise 1.5V/7A,

3.3V/7A, 500kHz Regualtor with Ratiometric Tracking

LTC3828

3828fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

G28 SSOP 0204

0.09 – 0.25

(.0035 – .010)

0° – 8°

0.55 – 0.95

(.022 – .037)

5.00 – 5.60**

(.197 – .221)

7.40 – 8.20

(.291 – .323)

12345678 9 10 11 12 1413

9.90 – 10.50*

(.390 – .413)

2526 22 21 20 19 18 17 16 1523242728

2.0

(.079)

MAX

0.05

(.002)

MIN

0.65

(.0256)

BSC 0.22 – 0.38

(.009 – .015)

TYP

MILLIMETERS

(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

0.42 ±0.03 0.65 BSC

5.3 – 5.7

7.8 – 8.2

RECOMMENDED SOLDER PAD LAYOUT

1.25 ±0.12

5.00 p 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES)

3.45 p 0.10

0.75 p 0.05 R = 0.115

TYP

0.25 p 0.05

(UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 s 45o CHAMFER

R = 0.05

TYP

0.70 p0.05

3.50 REF

(4 SIDES)

4.10

p0.05

5.50

p0.05

0.25 p 0.05

PACKAGE

OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.45 p 0.05

LTC3828

3828fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0109 REV C • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PHASMD

CLKOUT

TG1

TG2

0°

90°

OPEN

180°

LTC3729

BUCK: 2.5V/15A

PLLIN

TG1

TG2

90°

270°

LTC3828

BUCK: 1.5V/15A

2.5VO/30A

CIN

IIN

12VIN

*INPUT RIPPLE CURRENT CANCELLATION

INCREASES THE RIPPLE FREQUENCY AND

REDUCES THE RMS INPUT RIPPLE CURRENT

THUS, SAVING INPUT CAPACITORS

IIN*

1.5VO/15A

1.8VO/15A

3828 F16

BUCK: 1.8V/15A

Figure 16. Multioutput PolyPhase Application

PART NUMBER DESCRIPTION COMMENTS

LTC1628/LTC1628-PG/

LTC1628-SYNC

2-Phase, Dual Output Synchronous Step-Down

DC/DC Controllers

Reduces CIN and COUT

, Power Good Output Signal, Synchronizable,

3.5V ≤ VIN ≤ 36V, IOUT up to 20A, 0.8V ≤ VOUT ≤ 5V

LTC1629/

LTC1629-PG

20A to 200A PolyPhase

Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All

Surface Mount Components, No Heat Sink, VIN up to 36V

LTC1702A No RSENSE 2-Phase Dual Synchronous Step-Down

Controller

550kHz, No Sense Resistor

LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID 3.5V ≤ VIN ≤ 36V, VID Sets VOUT1, PGOOD

LT1709/LT1709-8 High Efﬁ ciency, 2-Phase Synchronous Step-Down

Switching Regulators with 5-Bit VID

1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures

Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V

LTC1735 High Efﬁ ciency Synchronous Step-Down

Switching Regulator

Output Fault Protection, 16-Pin SSOP

LTC1778/LTC1778-1 No RSENSE™ Current Mode Synchronous Step-Down

Controllers

Up to 97% Efﬁ ciency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),

IOUT up to 20A

LTC1929/LTC1929-PG 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components,

No Heat Sinks, 3.5V ≤ VIN ≤ 36V

LTC3708 Dual, 2-Phase, DC/DC Controller with Output Tracking Current Mode, No RSENSE, Up/Down Tracking, Synchronizable

LTC3711 No RSENSE Current Mode Synchronous Step-Down

Controller with Digital 5-Bit Interface

Up to 97% Efﬁ ciency, Ideal for Pentium

III Processors,

0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V, IOUT up to 20A

LTC3728 Dual, 550kHz, 2-Phase Synchronous Step-Down

Controller

Dual 180° Phased Controllers, VIN 3.5V to 35V, 99% Duty Cycle,

5mm × 5mm QFN, SSOP-28

LTC3729 20A to 200A, 550kHz PolyPhase Synchronous

Controller

Expandable from 2-Phase to 12-Phase, Uses all Surface Mount

Components, VIN up to 36V

LTC3731 3- to 12-Phase Step-Down Synchronous Controller 60A to 240A Output Current, 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V

LTC3770 Fast, No RSENSE Step-Down Synchronous Controller

with Margining, Tracking, PLL

± 0.67% 0.6V Reference Voltage; Programmable Margining; True

Current Mode; 4V ≤ VIN ≤ 32V

PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.