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DATA SHEET
DESCRIPTION
The
µ
PD4702 is 8-bit up/down counters for an incremental encoder. Two-phase (A, B) incremental input signals are
phase-differentiated, and on each signal edge, an up-count is executed if the A phase is leading, or a down-count if the
B phase is leading. Eight-bit count data is output in real time. A carry output and borrow output are also provided for counter
overflow and underflow.
The
µ
PD4704 is also available; use of these enables the count width to be extended.
1993
INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER
CMOS INTEGRATED CIRCUITS
µ
PD4702
MOS INTEGRATED CIRCUIT
FEATURES
•Incremental inputs (A, B)
•On-chip phase discrimination circuit (up-count mode
when the phase order is A → B, down-count mode
when B → A) 4-multiplication count method
•On-chip edge detection circuit
•8-bit up/down counter latch output
•Carry output, borrow output
•Count data output controllable (3-state output)
•CMOS, single +5 V power supply
ORDERING INFORMATION
Part Number Package
µ
PD4702C 20-pin plastic DIP (7.62 mm (300) )
µ
PD4702G 20-pin plastic SOP (7.62 mm (300) )
PIN CONFIGURATION (Top View)
PIN NAMES
A2-phase incremental signal inputs
B
Reset : Counter reset input
STB : Latch strobe signal input
OE : Output control signal input
CD0 to CD7:Count data outputs
Carry : Carry pulse output
Borrow : Borrow pulse output
Document No. S14940EJ3V0DS00 (3rd edition)
(Previous No. IC-3304A)
Date Published January 2004 N CP(K)
Printed in Japan
1
2
3
4
5
6
7
8
9
10
Reset
A
B
NC
CD0
CD1
CD2
CD3
NC
VSS
VDD
Carry
Borrow
STB
OE
CD7
CD6
CD5
CD4
NC
20
19
18
17
16
15
14
13
12
11
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
The mark shows major revised points.
★
2
µ
PD4702
Data Sheet S14940EJ3V0DS
BLOCK DIAGRAM
PIN FUNCTIONS
Function
Incremental signal A phase and B phase signal input pins (Schmitt input)
Count data output pins. Activated when OE is “L”, high impedance outputs when OE is “H”.
8-bit counter carry signal output pin (active-low)
8-bit counter borrow signal output pin (active-low)
8-bit counter reset signal output pin
Counter is reset when this pin is “H”.
Count data output control signal input pin
Counter data output latch signal. Data is latched on the fall of STB, and is held while STB
= “L”.
Power supply input pin
Ground pin
Pin Name Input/Output
A, B Input
(Schmitt)
CD0 to CD7Output
(3-state)
Carry Output
Borrow Output
RESET Input
(Schmitt)
OE Input
STB Input
VDD –
GND –
Reset
A
B
Phase
Discrimination
Edge Detection
8-Bit Up/Down Counter
8-Bit Latch
3-State Output
Carry
Borrow
STB
OE
CD0 to CD7
3
µ
PD4702
Data Sheet S14940EJ3V0DS
1. DESCRIPTION OF OPERATIONS
(1) Count operation
The
µ
PD4702 incorporates a phase discrimination circuit, and counts by 4-multiplication of the A and B input 2-phase
pulses. Therefore, a count operation is performed by an A input edge and a B input edge.
Figure 1–1. Count Operation Timing Chart
(2) Latch operation
An R-S flip-flop is inserted in the strobe input of the latch circuit as shown in Figure 1–2, and when STB changes from
“H” to “L” during a count operation, the internal latch signal STB remains at “H” until the end of the count operation. Therefore,
the count value is latched correctly even if STB input is performed asynchronously from the A and B input (if STB changes
from “H” to “L” within tSABSTB (40 ns) after the A input or B input edge, the latch contents will be either the pre-count or post-
count value). However, when a
µ
PD4704 is added, the correct value cannot be latched if all digits are latched simultaneously
when a carry or borrow is generated (the high-order digit may be latched before carry/borrow transmission).
Figure 1–2. STB Input Circuit
From Phase Discrimination Circuit
(Count Pulse)
STB
STB
Latched
when L
A, B Inputs
STB
tSABSTB
If tSABSTB is 40 ns or longer, the post-count value
is in
p
ut to the latch.
Forward (Up-Count) Reverse (Down-Count)
A Input
Count Operation
B Input
24 3 11 3 5 4 2 0
4
µ
PD4702
Data Sheet S14940EJ3V0DS
(3) Carry & borrow outputs
If the counter performs an up-count operation when the count value is 0FFH, an active-low pulse is output to the Carry
output (the pulse width is 25 ns MIN. 120 ns MAX. irrespective of the A/B phase input cycle. Similarly, if the counter performs
a down-count operation when the count value is 00H, an active-low pulse is output to the Borrow output.
A Borrow pulse is also output if a down-count operation is performed while RESET is “H” (during a reset), and therefore,
when a
µ
PD4704 is added, a reset must be executed at the same time.
5
µ
PD4702
Data Sheet S14940EJ3V0DS
2. OPERATING PRECAUTIONS
As the
µ
PD4702 incorporates an 8-bit counter, a large transient current flows in the case of a count value which changes
all the bits (such as 00H ↔ 0FFH or 7FH ↔ 080H). This will cause misoperation unless the impedance of the power supply
line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1
µ
F) be connected between
VDD and VSS right next to the IC as shown in Figure 2–1.
Figure 2–1. Decoupling Capacitor
C:0.1
µ
F tantalum electrolytic laminated
ceramic capacitor, etc.
Also, if a pulse shorter than the phase difference time tSAB (70 ns) is input to the A/ B phase inputs, this will result in a
miscount. Therefore, if this kind of pulse is to be input because of encoder bounds, etc., a filter should be inserted in the
A & B phase inputs.
Figure 2–2. A & B Phase Input Pulses
If PW is at 70 ns or more, the count value remains the same before and after pulse input. (UP count → DOWN count
or DOWN count → UP count is implemented, and therefore the the result is no change in the count value.)
µ
PD4702
VDD
VSS
+5 V
C
A Phase (or B Phase)
B Phase (or A Phase)
PW
If a pulse such that PW < 70 ns is input
in the A or B phase, there is a danger of
a miscount.
6
µ
PD4702
Data Sheet S14940EJ3V0DS
PARAMETER SYMBOL RATING UNIT
Supply voltage VDD –0.5 to +7.0 V
Input voltage VI–1.0 to VDD +1.0 V
Output voltage VO–0.5 to VDD +0.5 V
Operating temperature Topt –40 to +85 °C
Storage temperature Tstg –65 to +150 °C
Permissible loss PD500 (DIP) 200 (SOP) mW
PARAMETER SYMBOL TEST CONDITIONS
RATING
UNIT
MIN. MAX.
Input voltage high VIL 0.8 V
Input voltage low
VIH A, B, Reset 2.6 V
VIH Other than the above 2.2 V
Output voltage low VOL IOL = 12 mA 0.45 V
Output voltage high VOH IOH = –4 mA VDD – 0.8 V
Static consumption current IDD VI = VDD, VSS 50
µ
A
Input current IIVI = VDD, VSS –1.0 1.0
µ
A
3-state output leak current IOFF –10 10
µ
A
Dynamic consumption current IDD dyn fIN = 3.6 MHz, CL = 50 pF 12 mA
Hysteresis voltage VHA, B, Reset 0.2 V
PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT
Cycle tCYAB fIN = 3.6 MHz 280 ns
High-level width tPWABH 140 ns
A, B Low-level width tPWABL 140 ns
Phase difference time tSAB 70 ns
Setting time tSRSAB 0ns
Reset time tDRSCD 60 ns
Output delay tDABCD 100 ns
CD0 to CD7Output delay tDOECD 50 ns
Output delay tDSTBCD 60 ns
Float time tFOECD 40 ns
Carry Output delay tDABCB 120 ns
Borrow Output pulse width tPWCB 25 120 ns
RESET Reset pulse width tPWRS 40 ns
STB Setting time tSABSTB 40 ns
3. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS = 0 V)
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %)
AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5 V ±10 %)
7
µ
PD4702
Data Sheet S14940EJ3V0DS
AC Timings
Figure 3–1. Two-Phase Signal Input Timing
Figure 3–2. Count Data Output Timing
Figure 3–3. Carry/Borrow Signal Output Timing
tCYAB
tPWABL
tSABtSAB
tPWABLtPWABH
tCYAB
tSABtSAB
tPWABH
A
B
tPWRS
Reset tSRSAB tSABSTB
tDRSCD tDABCD tDSTBCD
tDOECD tFOECD
A/B
CD0–7
OE
STB
Borrow
Carry
A/B
(CD) (0FEH) (0FFH) (00) (01) (00) (0FFH) (0FEH) (0FDH)
tDABCB
tPWCB tDABCB
tPWCB
8
µ
PD4702
Data Sheet S14940EJ3V0DS
Consumption Current Measurement Circuit
AC Test Input Waveform
A
B
STB
OE D
7
D
1
D
0
C
L
C
L
C
L
V
DD
2.6 V
0.8 V
STB input connected to V
DD
or
OE input connected to V
SS
.
Load on all outputs, C
L
= 50 pF.
Measurement Conditions
A, B inputs
f
IN
= 3.6 MHz
VIH
VIL
VIH = 2.6 V (A, B, RESET inputs)
VIH = 2.2 V (inputs other than A, B, RESET)
VIL = 0.8 V
Timing measurement is performed at 1.5 V.
9
µ
PD4702
Data Sheet S14940EJ3V0DS
4. SAMPLE APPLICATION CIRCUITS
16-bit counter
µ
PD4702
µ
PD4704
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
Data Bus
Incremental Rotary Encoder
8
88
RESET
CS
L
CS
H
A
B
STB
OE
Carry
Borrow
CD
0
CD
7
R
UP
Down
STB
OE
CD
0
CD
7
R
10
µ
PD4702
Data Sheet S14940EJ3V0DS
5. PACKAGE DRAWINGS
★
110
20 11
20-PIN PLASTIC DIP (7.62mm(300))
ITEM MILLIMETERS
NOTES
1. Each lead centerline is located within 0.25 mm of
its true position (T.P.) at maximum material condition.
P20C-100-300A,C-2
N0.25
R0∼15°
A25.40 MAX.
B1.27 MAX.
F1.1 MIN.
G3.5±0.3
J5.08 MAX.
K7.62 (T.P.)
C2.54 (T.P.)
D0.50±0.10
H0.51 MIN.
I4.31 MAX.
L6.4
M0.25+0.10
−0.05
2. ltem "K" to center of leads when formed parallel.
M
R
M
I
H
G
F
DN
C
B
K
P0.9 MIN.
PL
A
J
11
µ
PD4702
Data Sheet S14940EJ3V0DS
110
1120
S
−3°
ITEM MILLIMETERS
A
B
C
E
F
G
H
J
12.7±0.3
1.27 (T.P.)
1.8 MAX.
1.55±0.05
7.7±0.3
0.78 MAX.
0.12
1.1
M
0.1±0.1
N
P20GM-50-300B, C-7
P3°+7°
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
D0.42+0.08
−0.07
K0.22+0.08
−0.07
L0.6±0.2
0.10
detail of lead end
I5.6±0.2
M
P
G
CB
D
E
F
N
20-PIN PLASTIC SOP (7.62 mm (300))
S
M
H
K
L
J
I
A
12
µ
PD4702
Data Sheet S14940EJ3V0DS
6. RECOMMENDED SOLDERING CONDITIONS
The
µ
PD4702 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
TYPES OF SURFACE MOUNT DEVICE
µ
PD4702G
Soldering process Soldering conditions Symbol
Infrared ray reflow Peak package’s surface temperature: 235 °C or below, IR35-00-3
Reflow time: 30 seconds or below (210 °C or higher),
Number of reflow process: 3, Exposure limit* : None
VPS Peak package’s surface temperature: 215 °C or below, VP15-00-3
Reflow time: 40 seconds or below (200 °C or higher),
Number of reflow process: 3, Exposure limit* : None
Wave soldering Solder temperature: 260 °C or below, WS60-00-1
Flow time: 10 seconds or below,
Number of flow process: 1, Exposure limit* : None
Partial heating method Terminal temperature: 300 °C or below,
Flow time: 10 seconds or below,
Exposure limit* : None
*Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Caution Do not use different soldering methods together (except for partial heating) .
★
TYPES OF THROUGH HOLE MOUNT DEVICE
µ
PD4702C
Process Conditions
Wave soldering Solder temperature: 260 °C or below,
(only to leads) Flow time: 10 seconds or below
Partial Heating Method Pin temperature: 300 °C or below,
Heat time: 3 seconds or less (per each lead).
Caution For through-hole device, the wave soldering process must be applied only to leads, and make sure that
the package body does not get jet soldered.
13
µ
PD4702
Data Sheet S14940EJ3V0DS
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades on NEC Semiconductor Devices (C11531E)
Guide to Quality Assurance for Semiconductor devices (MEI-1202)
Semiconductor Selection Guide - Products and Packages - (X13769X)
★
14
µ
PD4702
Data Sheet S14940EJ3V0DS
NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
PD4702
The information in this document is current as of January, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
