REV 1.1.7 2/6/03
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X9279
Single Digitally-Controlled (XDCP
TM
) Potentiometer
FEATURES
• 256 Resistor Taps
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100
Ω
typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 5µA Max
•V
CC
: 2.7V to 5.5V Operation
• 50K
Ω
, 100K
Ω
versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale
Package)
• Low Power CMOS
DESCRIPTION
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. The potentiometer has associated with it
a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Single Supply / Low Power / 256-tap / 2-Wire Bus
A
PPLICATION
N
OTES
AND
D
EVELOPMENT
S
YSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
FUNCTIONAL DIAGRAM
256-taps
50KΩ and 100KΩ
RH
RL
RW
POT
VCC
VSS
2-Wire
Bus
wiper
Interface
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
16 Bytes
Bus
Interface
and Control
Address
Data
Status
Write
Read
Transfer
Inc/Dec
Control
X9279
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DETAILED FUNCTIONAL DIAGRAM
DR0 DR1
DR2 DR3
WIPER
COUNTER
REGISTER
(WCR)
RH
RL
DATA
RW
INTERFACE
AND
CONTROL
CIRCUITRY
VCC
VSS
256-taps
50KΩ and 100KΩ
Bank 0
Bank 1 Bank 2 Bank 3
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
A0
SCL
SDA
A1
A2
WP
Control
Power On Recall
DR0 DR1
DR2 DR3
DR0 DR1
DR2 DR3
DR0 DR1
DR2 DR3
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
X9279
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PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
TSSOP
Pin
CSP Symbol Function
1 B2, B3 NC No Connect
2 A4 A0 Device Address for 2-Wire bus.
3 C2, C3 NC No Connect
4 B4 A2 Device Address for 2-Wire bus.
5 C4 SCL Serial Clock for 2-Wire bus.
6 D4 SDA Serial Data Input/Output for 2-Wire bus.
7D3 V
SS
System Ground.
8D2 WP
Hardware Write Protect
9 D1 A1 Device Address for 2-Wire bus.
10 C1 A3 Device Address for 2 wire-bus.
11 B1 R
W
Wiper Terminal of the Potentiometer.
12 A1 R
H
High Terminal of the Potentiometer.
13 A2 R
L
Low Terminal of the Potentiometer.
14 A3 V
CC
System Supply Voltage.
VCC
RL
VSS
1
2
3
4
5
6
78
14
13
12
11
10
9
A0
RW
SCL
A2
TSSOP
RH
X9279
NC
NC
SDA
A3
WP
A1
A0 VCC RLRH
A2 NC NC RW
SCL NC NC A3
SDA VSS WP A1
A
B
C
D
4321
CSP
X9279
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PIN DESCRIPTIONS
Bus Interface Pins
S
ERIAL
D
ATA
I
NPUT
/O
UTPUT
(SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
S
ERIAL
C
LOCK
(SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9279.
D
EVICE
A
DDRESS
(A2 - A0)
The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9279. A maximum of 8 devices may occupy the 2-
Wire serial bus.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
S
YSTEM
S
UPPLY
V
OLTAGE
(V
CC
)
AND
S
UPPLY
G
ROUND
(V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin
is the system ground.
Other Pins
N
O
C
ONNECT
No connect pins should be left open. This pins are used
for Xicor manufacturing and testing purposes.
H
ARDWARE
W
RITE
P
ROTECT
I
NPUT
(WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
X9279
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PRINCIPLES OF OPERATION
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description.
– Serial Interface Description.
– Instruction and Register Description.
Array Description
The X9279 is comprised of a resistor array (see Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
≥
V
H
,
V
L
, V
W
. The V
CC
ramp rate specification is always in
effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
RH
RL
RW
8 8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
WIPER
(WCR)
BANK_0 Only
(DR0) (DR1)
(DR2) (DR3)
X9279
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SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9279 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9279 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9279 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9279 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
DATA
OUTPUT
FROM
TRANSMITTER
189
DATA
OUTPUT
FROM
RECEIVER
START ACKNOWLEDGE
X9279
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Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9279
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9279 is still busy with the write operation no ACK
will be returned. If the X9279 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
FLOW 1: ACK Polling Sequence
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte ( ID and A)
The first byte sent to the X9279 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device ID for the X9279; this is fixed as 0101[B] (refer
to Table 1).
The A[2:0] bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2-A0 input pins. The slave address is
externally specified by the user. The X9279 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9279 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2-A0 inputs can
be actively driven by CMOS input signals or tied to VCC
or VSS.
Instruction Byte (I)
The next byte sent to the X9279 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [2:0]. The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9279 is single POT, the P0=0. The format is shown in
Table 2.
Register Bank Selection (RB, RA, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for Data Register to Wiper Counter
Register operations.
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for 2-Wire write and read
operations. The Data Registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction Issue STOP
No
Yes
Yes
Proceed
Issue STOP
No
Proceed
X9279
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Register Selection (R0 to R3) Table Register Bank Selection (Bank 0 to Bank 3) Table
RB RA
Register
Selection Operations
0 0 0 Data Register Read and Write;
Wiper Counter Register
Operations
0 1 1 Data Register Read and Write;
Wiper Counter Register
Operations
1 0 2 Data Register Read and Write;
Wiper Counter Register
Operations
1 1 3 Data Register Read and Write;
Wiper Counter Register
Operations
P1 P0
Bank
Selection Operations
0 0 0 Data Register Read and Write;
Wiper Counter Register
Operations
0 1 1 Data Register Read and Write
Only
1 0 2 Data Register Read and Write
Only
1 1 3 Data Register Read and Write
Only
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
ID3 ID2 ID1 ID0 0 A2 A1 A0
0101
(MSB) (LSB)
Device Type
Identifier Set to 0
for proper operation
Internal Slave
Address
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
Instruction Opcode
Register
Pot Selection (Bank Selection)
Set to P0=0 for potentiometer operations
Selection
P1 and P0 are used also for register Bank Selection
for 2-Wire Register Write and Read operations
Register Selection
Register Selected RB RA
DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1
X9279
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Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3 I2 I1 I0 RB RA P1P0
Read Wiper Counter
Register
10010 0 0 0Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
10100 0 0 0Write new value to the Wiper Counter
Register
Read Data Register 10111/01/01/01/0Read the contents of the Data Register pointed
to by P1-P0 and RB-RA
Write Data Register 11001/01/01/01/0Write new value to the Data Register
pointed to by P1-P0 and RB-RA
XFR Data Register to
Wiper Counter Register
11011/01/00 0Transfer the contents of the Data Register
pointed to by RB-RA (Bank 0 only) to the Wiper
Counter Register
XFR Wiper Counter
Register to Data Register
11101/01/00 0Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)
Increment/Decrement
Wiper Counter Register
00100 0 0 0Enable Increment/decrement of the Wiper
Counter Register
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9279 contains contains a Wiper Counter
Register, for the DCP potentiometer. The Wiper
Counter Register can be envisioned as a 8-bit parallel
and serial load counter with its outputs decoded to
select one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9279 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR. The DR0
value of Bank 0 is the default value.
Data Registers (DR)
The potentiometer has four 8-bit nonvolatile Data
Registers (DR3-DR0). These can be read or written
directly by the host. Data can also be transferred
between any of the four Data Registers and the
associated Wiper Counter Register. All operations
changing data in one of the Data Registers is a
nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
X9279
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Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVV
(MSB) (LSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NV NV NV NV NV NV NV NV
MSB LSB
Instructions
Four of the seven instructions are three bytes in length.
These instructions are:
–Read Wiper Counter Register – read the current
wiper position of the potentiometer,
–Write Wiper Counter Register – change current
wiper position of the potentiometer,
–Read Data Register – read the contents of the
selected Data Register;
–Write Data Register – write a new value to the
selected Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its four
associated registers (Bank 0).
Two instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9279; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register. These instructions are:
–XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
–XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9279 has responded with
an acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards
the RH terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instruction format for more details.
Figure 3. Two-Byte Instruction Sequence
These commands only valid when P1=P0=0
S
T
A
R
T
0 101
0A2 A0 A
C
K
I3 I2 I1 I0 RB RA P1 A
C
K
SCL
SDA
S
T
O
P
00
ID3 ID2 ID1 ID0 P0
Device ID Internal Instruction
Opcode
Address Register
Address
Pot/Bank
Address
A1
X9279
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Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Squence
Figure 6. Increment/Decrement Timing Limits
I3 I2 I1 I0 RB RA
0
ID3 ID2
ID1
ID0
Device ID External Instruction
Opcode
Address Register
Address
Pot/Bank
Address
0
WCR[7:0] valid only when P1=P0=0;
or
Data Register D[7:0] for all values of P1 and P0
S
T
A
R
T
0 101
A2 A1 A0 A
C
K
P1 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
I3 I2 I1 I0
0
ID3 ID2 ID1 ID0
Device ID External Instruction
Opcode
Address
Register
Address
Pot/Bank
Address
0
S
T
A
R
T
0101
A2 A1 A0 A
C
K
RA P1 P0 A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
RB
SCL
SDA
VW/RW
INC/DEC
CMD
Issued
Voltage Out
tWRID
X9279
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INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
Wiper Position
(Sent by X9279 on SDA) M
A
C
K
S
T
O
P
0 1 0 1 0A 2A 1A 0 10010000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
01010A 2A 1A 0 10100000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
Wiper Position
(Sent by X9279 on SDA) M
A
C
K
S
T
O
P
01010A 2A 1A 0 1011RBRAP1 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
Wiper Position
(Sent by Master on SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0A 2A 1A 0 1100RBRAP1 P0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0A 2A 1A 0 1110RBRA00
X9279
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Transfer Data Register (DR) to Wiper Counter Register (WCR)
Increment/Decrement Wiper Counter Register (WCR)
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
S
T
O
P
01010A 2A 1A 0 1101RBRA00
S
T
A
R
T
Device Type
Identifier
Device
Addresses S
A
C
K
Instruction
Opcode
DR/Bank
Addresses S
A
C
K
Increment/Decrement
(Sent by Master on SDA) S
T
O
P
0 1 0 10A 2A 1A 0 00100000 I/DI/D....I/DI/D
X9279
Characteristics subject to change without notice. 14 of 24
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ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCL, SDA any address input
with respect to VSS..................................–1V to +7V
∆V = | (VH–VL) |.................................................... 5.5V
Lead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds).................................................. ±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Device Supply Voltage (VCC)(4) Limits
X9279 5V ±10%
X9279-2.7 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (RH – RL) / 255, single pot
(4) During power up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
RTOTAL End to End Resistance 100 kΩT version
RTOTAL End to End Resistance 50 kΩU version
End to End Resistance Tolerance ±20 %
Power Rating 50 mW 25°C, each pot
IW Wiper Current ±3 mA
RWWiper Resistance 300 ΩIW = ± 3mA @ VCC = 3V
RWWiper Resistance 150 ΩIW = ± 3mA @ VCC = 5V
VTERM Voltage on any RH or RL Pin VSS VCC VV
SS = 0V
Noise -120 dBV/ Hz Ref: 1V
Resolution 0.4 %
Absolute Linearity (1) ±1 MI(3) Rw(n)(actual) – Rw(n)(expected)(5)
Relative Linearity (2) ±0.2 MI(3) Rw(n + 1) – [Rw(n) + MI](5)
Temperature Coefficient of
RTOTAL
±300 ppm/°C
Ratiometric Temp. Coefficient 20 ppm/°C
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Macro model
X9279
Characteristics subject to change without notice. 15 of 24
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
ICC1 VCC supply current
(active)
3mAf
SCL = 400KHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read
and
ICC2 VCC supply current
(nonvolatile write)
5mAf
SCL = 400KHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
ISB VCC current (standby) 5 µAV
CC = +6V; VIN = VSS or VCC;
SDA = VCC; (for 2-Wire, Standby State
only)
ILI Input leakage current 10 µAV
IN = VSS to VCC
ILO Output leakage current 10 µAV
OUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 1 V
VIL Input LOW voltage –1 VCC x 0.3 V
VOL Output LOW voltage 0.4 V IOL = 3mA
VOH Output HIGH voltage
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Units Test Conditions
CIN/OUT(6) Input / Output capacitance (SDA) 8 pF VOUT = 0V
CIN(6) Input capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V
Symbol Parameter Min. Max. Units
tr VCC(6) VCC Power-up rate 0.2 50 V/ms
tPUR(7) Power-up to initiation of read operation 1 ms
tPUW(7) Power-up to initiation of write operation 50 ms
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9279
Characteristics subject to change without notice. 16 of 24
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EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter Min. Max. Units
fSCL Clock Frequency 400 kHz
tCYC Clock Cycle Time 2500 ns
tHIGH Clock High Time 600 ns
tLOW Clock Low Time 1300 ns
tSU:STA Start Setup Time 600 ns
tHD:STA Start Hold Time 600 ns
tSU:STO Stop Setup Time 600 ns
tSU:DAT SDA Data Input Setup Time 100 ns
tHD:DAT SDA Data Input Hold Time 30 ns
tRSCL and SDA Rise Time 300 ns
tF SCL and SDA Fall Time 300 ns
tAA SCL Low to SDA Data Output Valid Time 0.9 µs
tDH SDA Data Output Hold Time 0 ns
TINoise Suppression Time Constant at SCL and SDA inputs 50 ns
tBUF Bus Free Time (Prior to Any Transmission) 1200 ns
tSU:WPA A0, A1 Setup Time 0 ns
tHD:WPA A0, A1 Hold Time 0 ns
Symbol Parameter Typ. Max. Units
tWR High-voltage write cycle time (store instructions) 5 10 ms
5V
1533Ω
100pF
SDA pin RH
10pF
CLCL
RW
RTOTAL
CW
25pF
10pF
RL
SPICE Macromodel
3V
867Ω
100pF
SDA pin
X9279
Characteristics subject to change without notice. 17 of 24
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XDCP TIMING
SYMBOL TABLE
.
Symbol Parameter Min. Max. Units
tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9279
Characteristics subject to change without notice. 18 of 24
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TIMING DIAGRAMS
Start and Stop Timing
Input Timing
Output Timing
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9279
Characteristics subject to change without notice. 19 of 24
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XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
SCL
SDA
VWx
(STOP)
LSB
tWRL
SDA
SCL ...
...
...
WP
A0, A1
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9279
Characteristics subject to change without notice. 20 of 24
REV 1.1.7 2/6/03 www.xicor.com
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
100KΩ
10KΩ10KΩ
10KΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9279
Characteristics subject to change without notice. 21 of 24
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Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9279
Characteristics subject to change without notice. 22 of 24
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
See Detail “A”
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5).252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0∞ – 8∞
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
DetailA (20X)
X9279
Characteristics subject to change without notice. 23 of 24
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Ball Matrix:
4321
AA0 Vcc RLRH
BA2 NC NC RW
CSCL NC NC A3
DSDA Vss WP A1
Package Dimensions
Symbol
Millimeters
Min Nominal Max
Package Width a 2.593 2.623 2.653
Package Length b 2.771 2.801 2.831
Package Height c 0.644 0.677 0.710
Body Thickness d 0.444 0.457 0.470
Ball Height e 0.200 0.220 0.240
Ball Diameter f 0.300 0.320 0.340
Ball Pitch – Width j 0.5
Ball Pitch – Length k 0.5
Ball to Edge Spacing – Width l 0.537 0.562 0.587
Ball to Edge Spacing – Length m 0.626 0.651 0.676
16-Bump Chip Scale Package (CSP B16)
Package Outline Drawing
f
m
j
lk
b
ad
e
e
c
Top View (Marking Side) Bottom View (Bumped Side) Side View
Side View
A4 A3 A2 A1
B4 B3 B2 B1
C4 C3 C2 C1
D4 D3 D2 D1
9279TRB
YWW I
LOT #
X9279
Characteristics subject to change without notice. 24 of 24
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
©Xicor, Inc. 2003 Patents Pending
REV 1.1.7 2/6/03 www.xicor.com
ORDERING INFORMATION
Device VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead TSSOP
B = 16-Lead CSP
Potentiometer Organization
Pot
T = 100KΩ
U = 50KΩ
X9279 P T VY
