
Double Pulse Test Board GA100SBJT12-FR4
Sept 2014 http://www.genesicsemi.com/ Pg 1 of 6
Double Pulse Test Board
Features Compatible
1200 V, 100 A Testing
Low Series Inductance Design
Wide, 6 oz. Copper Current Traces
Multiple DUT and FWD Connections for Long Life
Compatible with GeneSiC Gate Drive Mounting
Low Resistance and Inductance Gate Drive Connection
TO-247 Packaged Commercial SJTs
TO-257 Packaged High Temperature SJTs
TO-258 Packaged High Temperature SJTs
TO-46 Packaged High Temperature SJTs
Electrical Characteristics
Parameter Symbol Conditions Value Unit Notes
Test Voltage Maximum VDS, MAX 1200 V
Drain Current Maximum ID, MAX 100 A
Capacitor Bank Cbank 5.0 µF
Parasitic Inductance Ls HV = 800 V, ID = 6 A 62.5 nH
Maximum Stored Energy Emax HV = 1200 V 3.6 J
Overview
The GeneSiC Double Pulse Test Board is designed for performing double
pulse switching tests on GeneSiC SiC Junction Transistors (SJT) as well
as other three terminal switching transistors. It is designed using low ESL
capacitors and PCB traces to feature a low parasitic series inductance
(LS) current path. This is necessary to record data which is most
representative of the device under test (DUT) and minimize testing circuit
distortions. The board is capable of reaching a maximum of
1200 V and 100 A for high power device testing. An external load inductor,
DUT, and free-wheeling diode (FWD) are soldered to the board without
sockets for the lowest possible contact resistance and inductance.
GeneSiC pin compatible gate drive boards may be mounted directly on
to the Test Board for ease of use while also having a short, low inductance
path to the DUT gate pin connection.
Figure 2: GeneSiC Semiconductor Switching Test Board Schematic
VDS, MAX = 1200 V
ID, MAX = 100 A
Figure 1: GeneSiC Semi Double Pulse Test Board