THAT 300 Series
Low-Noise Matched
Transistor Array ICs
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; US
A
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2010, THAT Corporation. Document 600041 Rev 02
FEATURES
• 4 Matched NPN Transistors
º 300 typical hfe of 100
º 300A minimum hfe of 150
º 300B minimum hfe of 300
• 4 Matched PNP Transistors
º 320 typical hfe of 75
• 2 Matched PNP and 2 Matched NPN
Transistors
º 340 PNP typical hfe of 75
º 340 NPN typical hfe of 100
• Low Voltage Noise
º 0.75 nV/ √Hz (PNP)
º 0.8 nV/ √Hz (NPN)
• High Speed
ºf
T = 350 MHz (NPN)
ºf
T = 325 MHz (PNP)
• 500 μV matching between devices
• Dielectrically Isolated for low crosstalk
and high DC isolation
• 36V VCEO
APPLICATIONS
• Low Noise Front Ends
• Microphone Preamplifiers
• Log/Antilog Amplifiers
• Current Sources
• Current Mirrors
• Multipliers
The THAT 300, 320 and 340 are large
geometry, 4-transistor, monolithic NPN and/or PNP
arrays. They exhibit both high speed and low noise,
with excellent parameter matching between transis-
tors of the same gender. Typical base-spreading
resistance is 25 Ω for the PNP devices (30 Ω for the
low-gain NPNs), so their resulting voltage noise is
under 1 nV/√Hz. This makes the 300 series ideally
suited for low-noise amplifier input stages, log ampli-
fiers, and many other applications. The four-NPN
transistor array is available in versions selected for
hfe with minimums of 150 (300A) or 300 (300B).
Fabricated in a dielectrically isolated, comple-
mentary bipolar process, each transistor is electri-
cally insulated from the others by a layer of
insulating oxide (not the reverse-biased PN junctions
used in conventional arrays). As a result, they exhibit
inter-device crosstalk and DC isolation similar to
that of discrete transistors. The resulting low
collector-to-substrate capacitance produces a typical
NPN fT of 350 MHz (325 MHz for the PNPs).
Substrate biasing is not required for normal opera-
tion, though the substrate should be ac-grounded to
optimize speed and minimize crosstalk.
An eight-transistor bare-die array with similar
performance characteristics (the THAT 380G) is also
available from THAT Corporation. Please contact us
directly or through your local distributor for more
information. Military-grade temperature range
packages are available from TT Semiconductor (see
www.ttsemiconductor.com for more information).
Description
SO14340S14-U DIP14
2-Matched NPN Transistors and
2-Matched PNP Transistors
340P14-U SO14320S14-U DIP14
4-Matched PNP Transistors
320P14-U SO144-Matched NPN Transistors, Beta = 300 min.300BS14-U SO144-Matched NPN Transistors, Beta = 150 min.300AS14-U SO14300S14-U DIP14
4-Matched NPN Transistors, Beta = 60 min.
300P14-U
Package
ConfigurationPart Number
Table 1. Ordering Information
Document 600041 Rev 02 Page 2 of 5 THAT 300 Series Transistor Array ICs
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2010, THAT Corporation. All rights reserved.
NPN Collector-Emitter Voltage (BVCEO) 36 V
NPN Collector-Base Voltage (BVCBO) 36V
PNP Collector-Emitter Voltage (BVCEO) –36 V
PNP Collector-Base Voltage (BVCBO) –36 V
Collector-Substrate Voltage (BVCS) ± 100 V
Collector Current 30 mA
Emitter Current 30 mA
Operating Temperature Range (TOP) -40 to +85 °C
Maximum Junction Temperature (TJMAX) +125 °C
Storage Temperature (TST) -45 to +125 °C
Absolute Maximum Ratin
g
s2,3
SPECIFICATIONS1
TH
A
T 300
13
12
Q2
1
2
3
Q1
4
5
6
7
Q3
SUB 11
10
9
8
Q4
SUB
14
TH
A
T 320
13
12
Q2
11
10
9
8
Q4
SUB
1
2
3
4
5
6
7
Q1
Q3
SUB
14
TH
A
T 340
13
12
Q2
11
10
9
8
Q4
SUB
1
2
3
4
5
6
7
Q1
Q3
SUB
14
Figure 1. 300 Pinout Figure 2. 320 Pinout Figure 3. 340 Pinout
V—0.05——0.05——0.05—
IC = 1 mA, IB = 100μA
VCE(SAT)
NPN Collector Saturation Voltage
Ω
—TBD——TBD——30—VCB = 10 V, IC = 1 mArbb
NPN Base Spreading Resistance
Ω
—2——2——2—
VCB = 0V, 10 μA < IC < 10mA
rBE
NPN Bulk Resistance
pA—25——25——25—VCB = 25 VICBO
NPN Collector-Base Leakage
Current
nA
nA
300
—
100
1
—
—
600
—
200
2
—
—
1500
—
500
5
—
—
IC = 1 mA
IC = 10 μA
IOS
NPN ΔIB
300: |IB1-IB2| ; |IB3-IB4|
340: |IB1-IB2|
mV
mV
3
—
0.5
0.5
—
—
3
—
0.5
0.5
—
—
3
—
0.5
0.5
—
—
IC = 1 mA
IC = 10 mA
VOS
NPN ΔVBE
300: |VBE1-VBE2| ; |VBE3-VBE4|
340: |VBE1-VBE2|
MHz—350——350——350—IC = 1 mA, VCB = 10VfT
NPN Gain-Bandwidth Product
nV√Hz
—1——0.9——0.8—VCB = 10V, IC = 1 mA, 1kHzeN
NPN Noise Voltage Density
%—4——4——4—VCB = 10V, IC = 1mA
Δhfe
NPN Current Gain Matching
—
—
—
—
300
—
—
—
—
—
150
—
—
—
100
100
60
—
VCB = 10 V, IC = 1 mA
IC = 10 µA
hfe
NPN Current gain
MaxTypMinMaxTypMinMaxTypMin Units300B300A300 / 340(Q1,Q2)ConditionsSymbolParameter
NPN Electrical Characteristics2
THAT 300 Series Transistor Array ICs Page 3 of 5 Document 600041 Rev 02
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; US
A
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2010, THAT Corporation. All rights reserved.
SPECIFICATIONS1 (Cont’d)
Parameter Symbol Conditions Min Typ Max Units
PNP Current Gain hfe VCB = -10 V
IC = -1 mA 50 75 —
IC = -10 μA — 75 —
PNP Current Gain Matching Δhfe VCB = -10 V, IC = -1 mA — 5 — %
PNP Noise Voltage Density eNVCB = -10 V, IC = -1 mA, 1 kHz — 0.75 — nV√Hz
PNP Gain-Bandwidth Product fTIC = -1 mA, VCB = -10 V — 325 — MHz
PNP ΔVBE VOS IC = -1 mA — 0.5 3 mV
320: |VBE1-VBE2| ; |VBE3-VBE4| IC = -10 μA — 0.5 — mV
340: |VBE1-VBE2|
PNP ΔIBIOS IC = -1 mA — 700 1800 nA
320: |IB1-IB2| ; |IB3-IB4|I
C = -10 μA—7—nA
340: |IB1-IB2|
PNP Collector-Base Leakage Current ICBO VCB = -25 V — –25 — pA
PNP Bulk Resistance rBE VCB = 0 V, -10μA > IC> -10 mA — 2 — Ω
PNP Base Spreading Resistance rbb VCB = -10 V, IC = -1 mA — 25 — Ω
PNP Collector Saturation Voltage VCE(SAT) IC = -1 mA, IB = -100 μA — –0.05 — V
PNP Output Capacitance COB VCB = -10 V, IE = 0 mA, 100 kHz — 3 — pF
PNP Breakdown Voltage BVCEO IC = -10 mAdc, IB = 0 -36 -40 — V
Input Capacitance CEBO IC = 0 mA, VEB = 0 V — 6 — pF
PNP Electrical Characteristics2
1. All specifications are subject to change without notice.
2. Unless otherwise noted, TA = 25ºC.
3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; the
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
pF
—
5
——
5
——
5
—
IC = 0 mA, VEB = 0 VCEBO
Input Capacitance
V—4036—4036—4036
IC = 10 μAdc, IB = 0
BVCEO
NPN Breakdown Voltage
pF—3——3——3—VCB = 10V, IE = 0mA, 100kHzCOB
NPN Output Capacitance
MaxTypMinMaxTypMinMaxTypMin Units300B300A300 / 340(Q1,Q2)ConditionsSymbolParameter
NPN Electrical Characteristics2 (cont’d)
The THAT 300, 320 and 340 are available in 14-pin
PDIP and 14-pin surface mount (SOIC) packages.
Package dimensions are shown below.
The 300-series packages are entirely lead-free. The
lead-frames are copper, plated with successive layers of
nickel, palladium, and gold. This approach makes it
possible to solder these devices using lead-free and lead-
bearing solders.
Neither the lead-frames nor the plastic mold
compounds used in the 300-series contains any hazard-
ous substances as specified in the European Union's
Directive on the Restriction of the Use of Certain Hazard-
ous Substances in Electrical and Electronic Equipment
2002/95/EG of January 27, 2003. The surface-mount
package is suitable for use in a 100% tin solder process.
Document 600041 Rev 02 Page 4 of 5 THAT 300 Series Transistor Array ICs
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2010, THAT Corporation. All rights reserved.
0.750±0.004
(19.05±0.10)
0.25±.004
(6.35±0.10)
0. 30 ±0.02
(7.62 ±0.5)
0.060
(1.52)
0.075
(1.91)
0.10 Typ.
(2.54)
0.018
(0.46)
0.125±0.004
(3.18±0.10)
Typ.
1
0.010
(0.25)
Figure 4. Dual-In-Line Package Outline
0.050
(1.27)
Typ
0.245
(6.2)
Max
0.157
(3.99)
Max
0. 018 (0.46)
Max
0. 344 (8.74)
Max 0.069
(1.75)
Max 0.010
(0.25)
Max
1
Figure 5. Surface-Mount Package Outline
Packagin
g
and Soldering Information
Parameter Symbol Conditions Typ Units
Through-hole package See Fig. 4 for dimensions 14 Pin PDIP
Thermal Resistance θJA DIP package soldered to board 100 ºC/W
Environmental Regulation Compliance Complies with January 27, 2003 RoHS requirements
Surface mount package See Fig. 5 for dimensions 14 Pin SOP
Thermal Resistance θJA SO package soldered to board 100 ºC/W
Soldering Reflow Profile JEDEC JESD22-A113-D (250 ºC)
Moisture Sensitivity Level MSL Above-referenced JEDEC soldering profile 1
Environmental Regulation Compliance Complies with RoHS requirements
Package Characteristics
THAT 300 Series Transistor Array ICs Page 5 of 5 Document 600041 Rev 02
THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; US
A
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2010, THAT Corporation. All rights reserved.
THAT Corporation believes all the information furnished in this data sheet is accurate and reliable. However we assum
e
no responsibility for its use nor for any infringements of third-party intellectual property which may result from its use.
LIFE SUPPORT POLICY
THAT Corporation ICs are not designed for use in life support equipment where a malfunction of our ICs might
reasonably result in injury or death. Customers who use or sell our ICs for such life suport application do so at their
own risk, and shall hold THAT Corporation harmless from any and all claims, damages, suits, or expenses resulting
from such use or sale.
CAUTION: THIS IS AN ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICE
Electrostatic charges in the range of several kV can accumulate on the human body as well as test and assembly equip-
ment. This device can be damaged by the currents generated by electrostatic discharge from bodies and equipment.
Moreover, the transistors in this device are unprotected in order to maximize performance and flexibility. Accordingly,
they are more sensitive to ESD damage than many other ICs which include protection devices at their inputs. Note that
all of the pins are susceptible.
Use ESD-preventative measures when storing and handling this device. Unused devices should be stored in conductive
packaging. Packaging should be discharged to the destination socket before the devices are removed from their
packages. ESD damage can occur to these devices even after they are installed in a board-level assembly. Circuits
should include specific and appropriate ESD protection.
Revision History
—
1
2
3
3
4
5
-Added high hfe versions Models 300A and 300B with
accompanying specifications and information.
-Revised Features, Applications, and Description sections
-Revised Maximum Rating section
-Added NPN Breakdown Voltage spec.
-Added PNP Breakdown Voltage spec.
-Added Packaging Characteristics Table.
-Revised disclaimer text
Sept. 2010246002
2Changed Max. Operating Temperature from 70 °C to
85 °C.
April 2010239301
ReleaseApril 2004—00
PageChangesDateECORevision
THAT and c are registered trademarks of THAT Corporation.
